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• 1.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS).
Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

• 2.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)

A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

• 3.
KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Univ Gothenburg, Sweden. KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Univ Gothenburg, Sweden.
Order of magnitude improvement of nano-contact spin torque nano-oscillator performance2017In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 9, no 5, p. 1896-1900Article in journal (Refereed)

Spin torque nano-oscillators (STNO) represent a unique class of nano-scale microwave signal generators and offer a combination of intriguing properties, such as nano sized footprint, ultrafast modulation rates, and highly tunable microwave frequencies from 100 MHz to close to 100 GHz. However, their low output power and relatively high threshold current still limit their applicability and must be improved. In this study, we investigate the influence of the bottom Cu electrode thickness (t(Cu)) in nano-contact STNOs based on Co/Cu/NiFe GMR stacks and with nano-contact diameters ranging from 60 to 500 nm. Increasing t(Cu) from 10 to 70 nm results in a 40% reduction of the threshold current, an order of magnitude higher microwave output power, and close to two orders of magnitude better power conversion efficiency. Numerical simulations of the current distribution suggest that these dramatic improvements originate from a strongly reduced lateral current spread in the magneto-dynamically active region.

• 4.
KTH, School of Engineering Sciences (SCI), Applied Physics.
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Engineering Sciences (SCI), Applied Physics.
Order of magnitude improvement of nano-contact spin torque nano-oscillator performance2017In: 2017 IEEE International Magnetics Conference, INTERMAG 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, article id 8007567Conference paper (Refereed)

Spin torque nano-oscillators [1,2] (STNO) represent a unique class of nano-scale microwave signal generators where spin transfer torque [3-5] (STT) from a direct spin-polarized current drives and controls the auto-oscillation of the local free layer magnetization, which through its oscillating magnetoresistance transforms the direct current into a tunable microwave voltage.

• 5.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
Electrical conduction through a 2D InP-based photonic crystal - art. no. 63220J2006In: Tuning the Optic Response of Photonic Bandgap Structures III / [ed] Braun, PV; Weiss, SM, 2006, Vol. 6322, p. J3220-J3220Conference paper (Refereed)

This work investigates the current transport across two-dimensional PhCs dry etched into InP-based low-index-contrast vertical structures using Ar/Cl-2 chemically assisted ion beam etching. The electrical conduction through the PhC field is influenced by the surface potential at the hole sidewalls, which is modified by dry etching. The measured current-voltage (I-V) characteristics are linear before but show a current saturation at higher voltages. This behaviour is confirmed by simulations performed by ISE-TCAD software. We investigate the dependence of the conductance of the PhC area as a function of the geometry of the photonic crystal as well as the material parameters. By comparing the experimental and simulated conductance of the PhC, we deduce that the Fermi level is pinned at 0.1 eV below the conduction band edge. The method presented here can be used for evaluating etching processes and surface passivation methods. It is also applicable for other material systems and sheds new light on current driven PhC tuning.

• 6.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP. KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP. KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP. KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
Carrier transport through a dry-etched InP-based two-dimensional photonic crystal2007In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 101, no 12, p. 123101-1-123101-6Article in journal (Refereed)

The electrical conduction across a two-dimensional photonic crystal (PhC) fabricated by Ar/Cl-2 chemically assisted ion beam etching in n-doped InP is influenced by the surface potential of the hole sidewalls, modified by dry etching. Carrier transport across photonic crystal fields with different lattice parameters is investigated. For a given lattice period the PhC resistivity increases with the air fill factor and for a given air fill factor it increases as the lattice period is reduced. The measured current-voltage characteristics show clear ohmic behavior at lower voltages followed by current saturation at higher voltages. This behavior is confirmed by finite element ISE TCAD (TM) simulations. The observed current saturation is attributed to electric-field-induced saturation of the electron drift velocity. From the measured and simulated conductance for the different PhC fields we show that it is possible to determine the sidewall depletion region width and hence the surface potential. We find that at the hole sidewalls the etching induces a Fermi level pinning at about 0.12 eV below the conduction band edge, a value much lower than the bare InP surface potential. The results indicate that for n-InP the volume available for conduction in the etched PhCs approaches the geometrically defined volume as the doping is increased.

• 7. Bonetti, Stefano
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Direct observation and imaging of a spin-wave soliton with p−like symmetry2015In: Nature Communications, ISSN 2041-1723, E-ISSN 2041-1723, Vol. 6, article id 8889Article in journal (Refereed)

The prediction and realization of magnetic excitations driven by electrical currents via the spin transfer torque effect, enables novel magnetic nano-devices where spin-waves can be used to process and store information. The functional control of such devices relies on understanding the properties of non-linear spin-wave excitations. It has been demonstrated that spin waves can show both an itinerant character, but also appear as localized solitons. So far, it was assumed that localized solitons have essentially cylindrical, s−like symmetry. Using a newly developed high-sensitivity time-resolved magnetic x-ray microscopy, we instead observe the emergence of a novel localized soliton excitation with a nodal line, i.e. with p−like symmetry. Micromagnetic simulations identify the physical mechanism that controls the transition from s− to p−like solitons. Our results suggest a potential new pathway to design artificial atoms with tunable dynamical states using nanoscale magnetic devices.

fulltext
• 8.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Current Gain Degradation in 4H-SiC Power BJTs2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 702-705Article in journal (Refereed)

SiC airs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.

• 9.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 10, p. 2664-2670Article in journal (Refereed)

The influence of the emitter-base geometry on the current gain has been investigated by means of measurements and simulations. Particular attention has been placed on the emitter width and on the distance between the emitter edge and the base contact. When the emitter width is decreased from 40 to 8 mu m, the current gain is reduced by 20%, whereas when the distance between the base contact and the emitter edge is decreased from 5 to 2 mu m, the current gain is reduced by 10%. Simulations have been used to investigate the reasons for the current gain reduction. The reduction of the emitter width induces two mechanisms of current gain reduction: earlier forward biasing of the base-collector junction and higher recombination in the emitter region. Both mechanisms result from the higher current density flowing under the emitter region. Placing the base contact very close to the emitter edge increases the base current by increasing the gradient of the electron concentration toward the base contact. The effect of increasing the base doping in the extrinsic region has been simulated, and the results demonstrate that the current gain can be improved if a high doping concentration in the range of 5 x 10(18) cm(-3) is used.

• 10.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 3, p. 704-711Article in journal (Refereed)

Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10(-15) cm(2), and a trap concentration of 2 x 10(12) cm(-2). Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base ( which has a doping concentration of 3 x 10(17) cm(-3)) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.

• 11.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Temperature Modeling and Characterization of the Current Gain in 4H-SiC Power BJTs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, p. 1061-1064Article in journal (Refereed)

The current gain of 4H-SiC BJTs has been modeled using interface traps between SIC and SiO2 to describe surface recombination, by a positive temperature dependence of the carrier lifetime in the base region and by bandgap narrowing in the emitter region. The interface traps have been modeled by one single level at 1 eV above the valence band, with capture cross section of 1 x 10(-15) cm(2) and concentration of 2 x 10(12) cm(-2). The temperature behavior of SiC BJTs has been simulated and the results have been compared with measurements. An analysis of the carrier concentration has been performed in order to describe the mechanisms for fall-off of the current gain at high collector current. At room temperature high injection in the base and forward biasing of the base-collector junction occur simultaneously causing an abrupt drop of the current gain. At higher temperatures high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the only acting mechanism for the current gain fall-off at high collector current. This mechanism and the negative temperature dependence of the carrier mobility can also explain the reduction of the knee current for gain fall-off with increasing temperature. Simulations with different emitter widths have been also performed and analyzed to characterize the emitter size effect. Higher current density caused by reducing the emitter width introduces higher carrier recombination in the emitter region, leading to a reduction of the current gain.

• 12.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 2081-2087Article in journal (Refereed)

The ON-resistance of silicon carbide bipolar transistors is characterized and simulated. Output characteristics are compared at different base currents and different temperatures in order to validate the physical model parameters. A good agreement is obtained, and the key factors, which limit the improvement of R-ON, are identified. Surface recombination and material quality play an important role in improving device performances, but the device design is also crucial. Based on simulation results, a design that can enhance the conductivity modulation in the lowly doped drift region is proposed. By increasing the base doping in the extrinsic region, it is possible to meet the requirements of having low voltage drop, high current density, and satisfactory forced current gain. According to simulation results, if the doping is 5 x 10(18) cm(-3), it is possible to conduct 200 A/cm(2) at V-CE = 1 V by having a forced current gain of about 8, which represents a large improvement, compared with the simulated value of only one in the standard design.

• 13.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Investigation of Current Gain Degradation in 4H-SiC Power BJTs2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1131-1134Article in journal (Refereed)

The current gain degradation of 4H-SiC BJTs with no significant drift of the on-resistance is investigated. Electrical stress on devices with different emitter widths suggests that the device design can influence the degradation behavior. Analysis of the base current extrapolated from the Gummel plot indicates that the reduction of the carrier lifetime in the base region could be the cause for the degradation of the gain. However, analysis of the base current of the base-emitter diode shows that the degradation of the passivation layer could also influence the reduction of the current gain.

• 14.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Univ Gothenburg, Sweden.
Spin-Torque and Spin-Hall Nano-Oscillators2016In: Proceedings of the IEEE, ISSN 0018-9219, E-ISSN 1558-2256, Vol. 104, no 10, p. 1919-1945, article id 7505988Article in journal (Refereed)

This paper reviews the state of the art in spin-torque and spin-Hall-effect-driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential.

• 15.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Department of Physics, University of Gothenburg. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Department of Physics, University of Gothenburg and Department of Physics, Indian Institute of Technology. Department of Physics, University of Gothenburg. Department of Physics, University of Gothenburg. Department of Physics, University of Gothenburg. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Department of Physics, University of Gothenburg and Nanosc AB.
Spin-Torque and Spin-Hall Nano-OscillatorsIn: Proceedings of the IEEE, ISSN 0018-9219, E-ISSN 1558-2256Article in journal (Refereed)

This paper reviews the state of the art in spin-torque and spin Hall effect driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential.

fulltext
• 16.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I: Analytical Model of the MTJ STO2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1037-1044Article in journal (Refereed)

Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.

• 17.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II: Verilog-A Model Implementation2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1045-1051Article in journal (Refereed)

The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.

• 18.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Integration of GMR-based spin torque oscillators and CMOS circuitry2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 111, p. 91-99Article in journal (Refereed)

This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

• 19.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
Strain balance approach for optimized signal-to-noise ratio in SiGe quantum well bolometers2009In: ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, 2009, p. 101-104Conference paper (Refereed)

This work presents thermal and electrical characterization of SiGe/Si multi-quantum wells (MQWs) with different layer profiles in complete bolometer structures. The thermal property of the bolometers was studied by measuring thermal coefficient of resistivity (TCR) through I-V curves for five temperatures (25, 40, 55, 80 and 100°C) and for four different pixel areas. The results show a strong dependency of TCR on the Si/SiGe layer thickness and the presence of dopant impurity in the MQW. The noise measurements of MQWs were performed carefully by eliminating all external contributions and the noise spectroscopy provided the noise characteristic parameters. The results demonstrate that the noise depends on the geometric size of the MQW and it increases with decreasing of the pixel area. The investigations show the noise level in the bolometer structures is sensitive to any dopant segregation from the contact layers.

• 20. Donetti, L.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Hole effective mass in silicon inversion layers with different substrate orientations and channel directions2011In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 110, no 6, p. 063711-Article in journal (Refereed)

We explore the possibility to define an effective mass parameter to describe hole transport in inversion layers in bulk MOSFETs and silicon-on-insulator devices. To do so, we employ an accurate and computationally efficient self-consistent simulator based on the six-band k . p model. The valence band structure is computed for different substrate orientations and silicon layer thicknesses and is then characterized through the calculation of different effective masses taking account of the channel direction. The effective masses for quantization and density of states are extracted from the computed energy levels and subband populations, respectively. For the transport mass, a weighted averaging procedure is introduced and justified by comparing the results with hole mobility from experiments and simulations.

• 21. Donetti, L.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
On the effective mass of holes in inversion layers2011In: International Conference on Ultimate Integration on Silicon, 2011, p. 50-53Conference paper (Refereed)

We study hole inversion layers in bulk MOSFETs and silicon-on-insulator devices employing a self-consistent simulator based on the six-band kp model. Valence Band structure is computed for different device orientations and silicon layer thicknesses, and then it is characterized through the calculation of different effective masses.

• 22. Driussi, F.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
On the electron mobility enhancement in biaxially strained Si MOSFETs2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 4, p. 498-505Article in journal (Refereed)

This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.

• 23.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Dependence of the colored frequency noise in spin torque oscillators on current and magnetic field2014In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 104, no 9, p. 092405-Article in journal (Refereed)

The nano-scale spin torque oscillator (STO) is a compelling device for on-chip, highly tunable microwave frequency signal generation. Currently, one of the most important challenges for the STO is to increase its longer-time frequency stability by decreasing the 1/f frequency noise, but its high level makes even its measurement impossible using the phase noise mode of spectrum analyzers. Here, we present a custom made time-domain measurement system with 150MHz measurement bandwidth making possible the investigation of the variation of the 1/f as well as the white frequency noise in a STO over a large set of operating points covering 18-25GHz. The 1/f level is found to be highly dependent on the oscillation amplitude-frequency non-linearity and the vicinity of unexcited oscillation modes. These findings elucidate the need for a quantitative theoretical treatment of the low-frequency, colored frequency noise in STOs. Based on the results, we suggest that the 1/f frequency noise possibly can be decreased by improving the microstructural quality of the metallic thin films.

• 24.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Material Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Material Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Material Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Material Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Material Physics, Material Physics, MF.
1/f and white frequency noise in a synchronized spin torque oscillator pair2011In: 56th Annual Conference on Magnetism and Magnetic Materials, 2011, p. 504-504Conference paper (Refereed)
• 25.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Göteborgs universitet. NanOsc AB. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. Göteborgs universitet. Göteborgs universitet. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. Göteborgs universitet. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Nonlinearity, frequency stability and device-to-device variability in nano-contact spin torque oscillators with grainy thin filmsManuscript (preprint) (Other academic)

In nano-contact spin torque oscillators with a frequency range of 10-65 GHz, the propagating spin wave mode attracts interest due both to its high frequency stability and prospective use in magnonic devices. Its dependence of the frequency on the bias current however displays device-to-device variability on the order of several hundred MHz, with device specific nonlinearities that can be either continuous or discontinuous and have negative impact on the frequency stability. A model for this behavior is however still lacking. By using micromagnetic simulations, we investigate the impact of imperfections in the spin wave-carrying free magnetic layer and find that nonlinearities can be created when the propagating spin wave is reflected back to the active region. The oscillation then self-locks at the frequency of the resonant wavelength, resulting in a standing spin wave pattern. Simulations including nine randomly generated film structures with 30 nm-sized grains and exchange-reduced inter-grain boundaries give qualitative and partially quantitative agreement with experimental measurements. The results point out the spin wave-reflecting grain boundaries as a source of device nonlinearity, manufacturing variability and frequency destabilization.

• 26.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. NanOsc AB. NanOsc AB. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
Triple mode-jumping in a spin torque oscillator2013In: 2013 22nd International Conference on Noise and Fluctuations, ICNF 2013, New York: IEEE conference proceedings, 2013, p. 6578965-Conference paper (Refereed)

In a nano-contact Co/Cu/NiFe spin torque oscillator, mode-jumping between up to three frequencies within 22.5-24.0 GHz is electrically observed in the time domain. The measurements reveal toggling between two states with differing oscillation amplitude, of which the low-amplitude state is further divided into two rapidly alternating modes. Analysis of the mode dwell time statistics and the total time spent in each mode is carried out, and it is found that in both aspects the balance between the modes is greatly altered with the DC drive current.

modejumping
• 27.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators2019In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 5, p. 670-673Article in journal (Refereed)

Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

• 28.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
High frequency performance of SiGeCHBTs with selectively & non-selectively grown collector2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 138-141Article in journal (Refereed)

Two high-frequency heterojunction bipolar transistor (HBT) architectures based on SiGeC have been fabricated and characterized. Different collector designs were applied either by using selective epitaxial growth doped with phosphorous or by non-selective epitaxial growth doped with arsenic. Both designs have a non-selectively deposited SiGeC base doped with boron and a poly-crystalline emitter doped with phosphorous. Both HBT designs exhibit similar electrical characteristics with a peak DC current gain of around 1600 and a BVCEO of 1.8V. The cut-off frequency (f(T)) and maximum frequency of oscillation (f(max)) vary from 40-80 GHz and 15-30 GHz, respectively, depending on lateral design relations. Good high frequency performance for a device with a selectively grown collector is demonstrated for the first time.

• 29.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Experimental Study of Degradation in 4H-SiC BJTs by Means of Electrical Characterization and Electroluminescence2010In: SILICON CARBIDE AND RELATED MATERIALS 2009 / [ed] Bauer AJ; Friedrichs P; Krieger M; Pensl G; Rupp R; Seyller T, 2010, Vol. 645-648, p. 1037-1040Conference paper (Refereed)

SiC power bipolar junction transistors (BJTs), for high voltage applications, have been studied under elevated temperature and electrical stress conditions. Electroluminescence has been used to capture effects of defect motion and growth, in complete transistor structures, leading to a quantifiable degradation in the electrical performance. The observed degradation of current gain (beta) and on-resistance (RON) was relatively modest and saturated after a limited stress time, resulting in stable device performance. The characteristic wavelength (450 nm) of the electroluminescence, or light emission, in the visual and near infrared (NIR) range, coupled to the shape of the defects indicates that basal plane dislocations and stacking faults are involved.

• 30.
KTH, School of Electrical Engineering (EES), Microsystem Technology.
KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Electrical Engineering (EES), Microsystem Technology. KTH, School of Electrical Engineering (EES), Microsystem Technology. KTH, School of Electrical Engineering (EES), Microsystem Technology.
3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching2012In: Advanced Functional Materials, ISSN 1616-301X, E-ISSN 1616-3028, Vol. 22, no 19, p. 4004-4008Article in journal (Refereed)

A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro- and nanostructures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The method is demonstrated by fabricating 3D structures made of two and three silicon layers, including suspended beams that are 40 nm thick, 500 nm wide, and 4 μm long, and patterned lines that are 33 nm wide.

fulltext
• 31.
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201). KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Applied Material Physics. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. FEI Electron Optics. KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201). KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
3D Patterning of Si Micro and Nano Structures by Focused Ion Beam Implantation, Si Deposition and Selective Si Etching2012Conference paper (Other academic)
• 32.
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201). KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201). KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
Layer-by-layer 3D printing of Si micro- and nanostructures by Si deposition, ion implantation and selective Si etching2012In: 12th IEEE Conference on Nanotechnology (IEEE-NANO), 2012, IEEE conference proceedings, 2012, p. 1-4Conference paper (Refereed)

In this paper we report a method for layer-by-layer printing of three-dimensional (3D) silicon (Si) micro- and nanostructures. This fabrication method is based on a sequence of alternating steps of chemical vapor deposition of Si and local implantation of gallium (Ga+) ions by focused ion beam (FIB) writing. The defined 3D structures are formed in a final step by selectively wet etching the non-implanted Si in potassium hydroxide (KOH). We demonstrate the viability of the method by fabricating 2 and 3-layer 3D Si structures, including suspended beams and patterned lines with dimensions on the nm-scale.

fulltext
• 33.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 11, p. 1170-1172Article in journal (Refereed)

Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of similar to 1.2 x 10(13) cm(-2) in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single-and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.

• 34. Grahn, J. V.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
A low-complexity 62-GHz f(T) SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 549-554Article in journal (Refereed)

A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor deposition at reduced pressure was used for low-temperature SiGe epitaxy. Following SiGe epitaxy, the process temperature budget was kept very low with 900 degrees C for 10 s as the highest temperature step. A very high current gain of almost 2000 and cut off frequency of 62 GHz were achieved for a uniform 12% Ge profile. The breakdown voltage BVCEO and forward Early voltage were equal to 2.9 and 6.5 V, respectively.

• 35.
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201). KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics. KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
Process considerations for layer-by-layer 3D patterning of silicon, using ion implantation, silicon deposition, and selective silicon etching2012In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 30, no 6, p. 06FF05-Article in journal (Refereed)

The authors study suitable process parameters, and the resulting pattern formation, in additive layer-by-layer fabrication of arbitrarily shaped three-dimensional (3D) silicon (Si) micro- and nanostructures. The layer-by-layer fabrication process investigated is based on alternating steps of chemical vapor deposition of Si and local implantation of gallium ions by focused ion beam writing. In a final step, the defined 3D structures are formed by etching the Si in potassium hydroxide, where the ion implantation provides the etching selectivity.

fulltext
• 36.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
Influence of self heating in a BiCMOS on SOI technology2004In: ESSCIRC 2004: Proceedings of the 34th European Solid-State Device Research Conference, NEW YORK: IEEE , 2004, p. 337-340Conference paper (Refereed)

Self heating in a 0.25mum BiCMOS technology with different isolation structures is characterized. Thermal resistance values for single- and multiple-emitter devices are extracted and reported. The dependence of the thermal resistance on the emitter aspect ratio is critical to take into consideration when determining the isolation scheme for devices. 2-D electro-thermal simulations are performed and compared to experimental results. The impact of metallization on the self-heating in the device is examined through simulations.

• 37.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
Device design for a raised extrinsic base SiGe bipolar technology2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 11-okt, p. 1927-1931Article in journal (Refereed)

The impact of emitter, inside spacer, and SIC lateral scaling on the AC and DC performance of a raised extrinsic base SiGe HBT has been investigated using the ISE TCAD simulation package and design of experiments methods. Strong first order effects for all three variables were observed while the interactions of the variables had a weaker effect. It was found that as the emitter size shrinks towards 0.1 mum the impact of changes to inside spacer and SIC width on the current gain increased. The response surface design led to an optimized simulated transistor featuring f(T) and f(MAX) values of 214 and 332 GHz, respectively.

• 38.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
HRXRD analysis of SiGeC layers for BiCMOS applications2004Conference paper (Refereed)

The use of HRXRD for the monitoring of the dopant activation anneal through the detection of carbon outdiffusion has been demonstrated. The advantages of HRXRD over other measurement techniques for in-line epi-growth monitoring are also discussed. HRXRD reciprocal space mapping was used to study the SiGe layer stability as a function of carbon concentration for vertically scaled layers designed for high performance BiCMOS applications. It was found that as the carbon concentration is increased there is a reduction of boron cluster formation, but an increase in defect density is also observed.

• 39.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
NiSi integration in a non-selective base SiGeCHBT process2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 03-jan, p. 245-248Article in journal (Refereed)

A self-aligned nickel silicide (salicide) process is integrated into a non-selective base SiGeC HBT process. The device features a unique, fully silicided base region that grows laterally under the emitter pedestal. This Ni(SiGe) formed in this base region was found to have a resistivity of 23-24 muOmega cm. A difference in the silicide thickness between the boron-doped SiGeC extrinsic base region and the in situ phosphorous-doped emitter region is observed and further analyzed and confirmed with a blanket wafer silicide study. The silicided device exhibited a current gain of 64 and HF device performance of 39 and 32 GHz for f(t) and f(MAX), respectively.

• 40.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT. KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
The effect of C on emitter-base design for a single-polysilicon SiGe: C HBT with an IDP emitter2004In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Vol. 224, no 1-4, p. 330-335Article in journal (Refereed)

A differential epitaxy SiGe:C heterojunction bipolar junction transistor (HBT) design is reported and used to study the effect of carbon on junction formation as well as the effect of lateral design parameters on ac and dc performance. The device exhibits a high current gain (beta) of 1700 and a BVCEO of 1.8 V. The peak cutoff frequency (f(T)) and maximum oscillation frequency (f(MAX)) are 73 and 17 GHz, respectively. The effect of emitter overlap on f(T) was minimal, but it had a strong impact on dc performance. LOCOS opening size strongly impacted both ac and dc performance. In addition, the effect of carbon, base cap thickness, and rapid thermal anneal (RTA) temperature on the emitter-base (E-B) junction formation was studied.

• 41.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
A 500 degrees C 8-b Digital-to-Analog Converter in Silicon Carbide Bipolar Technology2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 9, p. 3445-3450Article in journal (Refereed)

High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 degrees C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 degrees C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 degrees C are 0.79 and 1.01 LSB, respectively, while at 500 degrees C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 degrees C and 500 degrees C, respectively.

• 42.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
A Monolithic, 500 degrees C Operational Amplifier in 4H-SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 7, p. 693-695Article in journal (Refereed)

A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature operation of the amplifier is demonstrated from 25 degrees C to 500 degrees C. The measured closed loop gain is around 40 dB for all temperatures whereas the 3 dB bandwidth increases from 270 kHz at 25 degrees C to 410 kHz at 500 degrees C. The opamp achieves 1.46 V/mu s slew rate and 0.25% total harmonic distortion. This is the first report on high temperature operation of a fully integrated SiC bipolar opamp which demonstrates the feasibility of this technology for high temperature analog integrated circuits.

A Monolithic 500C Operational Amplifier in 4H-SiC Bipolar Technology
• 43.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C2020In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 8, no 1, p. 116-121Article in journal (Refereed)

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.

• 44.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Silicon Carbide BJT Oscillator Design Using S-Parameters2018In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018Conference paper (Refereed)

Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

fulltext
• 45.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Silicon carbide BJT oscillator design using S-parameters2019In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 674-678Conference paper (Refereed)

Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation is further aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, an alternative small-signal, S-parameter based design method can be employed directly without going into complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 °C) was accessed by on-wafer probing and connected by RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

• 46.
KTH, School of Electrical Engineering and Computer Science (EECS).
KTH. KTH. KTH. KTH. KTH. KTH.
An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)

This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

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• 47.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
An Intermediate Frequency Amplifier for High-Temperature Applications (vol 65, pg 1411, 2018)2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 8, p. 3694-3694Article in journal (Refereed)

This correspondence highlights an error in the above-titled paper. The corrected material is presented here.

• 48.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)

This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

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• 49.
KTH, School of Electrical Engineering and Computer Science (EECS).
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)

This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

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• 50.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Uppsala University, Ångström Laboratory. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
A robust spacer gate process for deca-nanometer high-frequency MOSFETs2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 3, p. 434-439Article in journal (Refereed)

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

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