Change search
Refine search result
1 - 32 of 32
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Ekström, Mattias
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hou, Shuoben
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, Vol. 924, p. 389-392Conference paper (Refereed)
    Abstract [en]

    Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

  • 2.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A wafer-scale Ni-salicide contact technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. P197-P200Article in journal (Refereed)
    Abstract [en]

    A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

  • 3.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. 197-200Article in journal (Refereed)
    Abstract [en]

    A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.

  • 4.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

  • 5.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT).
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    500 degrees C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 38, no 10, p. 1429-1432Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for hightemperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (J(C)), lower on-resistance (R-ON), and more uniform current distribution. A maximum current gain (beta) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs aremeasured fromroom temperature to 500 degrees C. An open-base breakdown voltage (V-CEO) of > 50 V is measured for the devices.

  • 6.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Process variation tolerant 4H-SiC power devices utilizing trench structures2013In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 740-742, p. 809-812Article in journal (Refereed)
    Abstract [en]

    Silicon carbide (SiC) is one of the most attractive semiconductors for high voltage applications. The breakdown voltage of SiC-based devices highly depends on the variation of the fabrication process including doping of the epilayers and the etching steps. In this paper, we show a way to diminish this variability by employing novel trench structures. The influence of the process variations in terms of doping concentration and etching has been studied and compared with conventional devices. The breakdown voltage variation (ΔVBr) of 450 V and 2100 V is obtained for the ±20% variation of doping concentration of the devices with and without the trench structures, respectively. For ±20% variation in etching steps, the maximum ΔVBR of 380 V is obtained for the device with trench structures in comparison to 1800 V for the conventional structure without trench structures. These results show that the breakdown voltage variation is significantly reduced by utilizing the proposed structure.

  • 7.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetteling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices2016In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 858, p. 978-981Article in journal (Other (popular science, discussion, etc.))
    Abstract [en]

    High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) are fabricated and optimized in terms of the length and remaining dose of JTEs. It is found that the JTE1 is the most effective one in spreading the electric field. Hence, for a given total termination length, a decremental JTE length from the innermost edge to the outermost mesa edge of the device results in better modification of the electric field. A breakdown voltage of 4.95 kV is measured for the modified device, which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches are fabricated. It is presented that the maximum current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

  • 8.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4366-4372Article in journal (Refereed)
    Abstract [en]

    A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H–SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.

  • 9.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    4.5-kV 20-mΩ. cm2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821, p. 838-841Article in journal (Refereed)
    Abstract [en]

    A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.

  • 10.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 2, p. 168-170Article in journal (Refereed)
    Abstract [en]

    Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.

  • 11.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modification of etched junction termination extension for the high voltage 4H-SiC power devices2016In: Silicon Carbide and Related Materials, Trans Tech Publications, 2016, p. 978-981Conference paper (Refereed)
    Abstract [en]

    High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) were fabricated and optimized in terms of the length (LJTE) and remaining dose (DJTE) of JTEs. It is found that for a given total termination length (Σ LJTEi), a decremental JTE length from the innermost edge to the outermost mesa edge of the device will result in better modification of the electric field. A breakdown voltage (BV) of 4.95 kV is measured for the modified device which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches were fabricated. The maximum current gain of 40 is achieved for a single finger device with the emitter width of 40 μm at IC = 0.25 A (JC = 310 A/cm2) which corresponds to RON = 33 mΩ.cm2. It is presented that the current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

  • 12.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT). KTH University.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT).
    Shakir, Muhammad
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    High Temperature Bipolar Master-Slave Comparator and Frequency Divider in 4H-SiC Technology2017In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 897, p. 681-684Article in journal (Refereed)
    Abstract [en]

    This paper demonstrates a fully integrated master-slave emitter-coupled logic (ECL)comparator and a frequency divider implemented in 4H-SiC bipolar technology. The comparator consists of two latch stages, two level shifters and an output buffer stage. The circuits have been tested up to 500 °C. The single ended output swing of the comparator is -7.73 V at 25 °C and-7.63 V at 500 °C with a -15 V supply voltage. The comparator consumes 585 mW at 25 °C. The frequency divider consisting of two latches shows a relatively constant output voltage swing over the wide temperature range. The output voltage swing is 7.62 V at 25 °C and 7.32 V at 500 °C.

  • 13.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Moeen, Mahdi
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kinetic Modeling of Low Temperature Epitaxy Growth of SiGe Using Disilane and Digermane2012In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 159, no 5, p. H478-H481Article in journal (Refereed)
    Abstract [en]

    Low temperature epitaxy (LTE) in Chemical Vapor Deposition (CVD) refers to 350-650 degrees C interval. This temperature range is critical for this process since the thermal and lattice mismatch (or strain relaxation) issues diminish in advanced BiCMOS processing. The modeling of the epitaxy process is a vital task to increase the understanding the growth process and to design any desired device structure. In this study, an empirical model for Si2H6/Ge2H6-based LTE of SiGe is developed and compared with experimental work. The model can predict the number of free sites on Si surface, growth rate of Si and SiGe, and the Ge content at low temperatures. A good agreement between the model and the experimental data is obtained.

  • 14.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Östling,
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Gated base structure for improved current gain in SiC bipolar technology2017In: 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017, Editions Frontieres , 2017, p. 122-125Conference paper (Refereed)
    Abstract [en]

    Silicon Carbide (SiC) bipolar integrated circuits are a promising technology for extreme environment applications. SiC bipolar technology shows stable operation over a wide range of temperature. However, the current gain of the devices is suffering from high surface recombination, due to poor oxide passivation. In this paper we propose a gated base structure that offers improved current gain control. A polysilicon gate is formed on the passivation oxide on top of the base-link region. We investigate the current gain as a function of gate bias and temperature. A negative gate bias improves the gain at low collector current by more than 30% by suppressing the surface recombination. Measurements are presented at temperatures ranging from 300 K to 550 K and the gain is consistently improved. The proposed structure is also useful as a process monitor for the passivation oxide quality.

  • 15.
    Moeen, Mahdi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammad Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Tehran, Iran.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Improved designs of Si-based quantum wells and Schottky diodes for IR detection2016In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 613, p. 19-23Article in journal (Refereed)
    Abstract [en]

    Novel structures of intrinsic or carbon-doped multi quantum wells (MQWs) and intrinsic or carbon-doped Si Schottky diodes (SD), individually or in combination, have been manufactured to detect the infrared (IR) radiation. The carbon concentration in the structures was 5 × 1020 cm− 3 and the MQWs are located in the active part of the IR detector. A Schottky diode was designed and formed as one of the contacts (based on NiSi(C)/TiW) to MQWs where on the other side the structure had an Ohmic contact. The thermal response of the detectors is expressed in terms of temperature coefficient of resistance (TCR) and the quality of the electrical signal is quantified by the signal-to-noise ratio. The noise measurements provide the K1/f parameter which is obtained from the power spectrum density. An excellent value of TCR = − 6%/K and K1/f = 4.7 × 10− 14 was measured for the detectors which consist of the MQWs in series with the SD. These outstanding electrical results indicate a good opportunity to manufacture low cost Si-based IR detectors in the near future.

  • 16.
    Moeen, Mahdi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Abedin, Ahmad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Enhanced device designs for Si-based infrared detectors2015In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118Article in journal (Other academic)
  • 17.
    Moeen, Mahdi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, M.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of SiGe/Si multi-quantum wells for infrared sensing2013In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 103, no 25, p. 251609-Article in journal (Refereed)
    Abstract [en]

    SiGe epitaxial layers are integrated as an active part in thermal detectors. To improve their performance, deeper understanding of design parameters, such as thickness, well periodicity, quality, and strain amount, of the layers/interfaces is required. Oxygen (2-2500 × 10-9 Torr) was exposed prior or during epitaxy of SiGe/Si multilayers. In this range, samples with 10 nTorr oxygen were processed to investigate layer quality and noise measurements. Temperature coefficient of resistance was also measured to evaluate the thermal response. These results demonstrate sensitivity of SiGe-based devices to size and location of defects in the structure.

  • 18.
    Radamson, Henry
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Moeen, Mahdi
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Abedin, Ahmad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouzb, M
    bSchool of Electrical and Computer Engineering, University of Tehran,Tehran, Iran.
    Sensitivity of Signal-to-Noise Ratio to the Layer Profile and Crystal Quality of SiGe/Si Multilayers2016In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 5, p. 3196-3201Article in journal (Other (popular science, discussion, etc.))
    Abstract [en]

    This study presents signal-to-noise ratio (SNR) measurements of single crystalline dots or layers of SiGe/Si in multilayer structures in terms of Ge content, interfacial and layer quality. All multilayers were processed in form of mesas and the noise behavior of electrical signal was investigated by comparing the power spectral density curves and K1/f values. The SiGe/Si multilayer structures were also characterized by the conventional material analysis tools and the results were compared to the noise measurements. The quality of SiGe/Si interface or SiGe layer was monitored by intentional exposure to oxygen in range of 2–1600 nTorr either during or prior to SiGe growth. The results demonstrated that SNR was sensitive to the interfacial and layer quality, and the Ge content in a multilayer structure. The noise level became very high when the strain fluctuated within SiGe layer and this occurred for SiGe with high Ge content or SiGe dots.

  • 19.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon Carbide Technology for High- and Ultra-High-Voltage Bipolar Junction Transistors and PiN Diodes2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Silicon carbide (SiC) is an attractive material for high-voltage and high-temperature electronic applications owing to the wide bandgap, high critical electric field, and high thermal conductivity. High- and ultra-high-voltage silicon carbide bipolar devices, such as bipolar junction transistors (BJTs) and PiN diodes, have the advantage of a low ON-resistance due to conductivity modulation compared to unipolar devices. However, in order to be fully competitive with unipolar devices, it is important to further improve the off-state and on-state characteristics, such as breakdown voltage, leakage current, common-emitter current gain, switching, current density, and ON-resistance.

    In order to achieve a high breakdown voltage with a low leakage current, an efficient and easy to fabricate junction edge protection or termination is needed. Among different proposed junction edge protections, a mesa design integrated with junction termination extensions (JTEs) is a powerful approach. In this work, implantation-free 4H-SiC BJTs in two classes of voltage, i.e., 6 kV-class and 15 kV-class with an efficient and optimized implantation-free junction termination (O-JTE) and multiple-shallow-trench junction termination extension (ST-JTE) are designed, fabricated and characterized. These terminations result in high termination efficiency of 92% and 93%, respectively.

    The 6 kV-class BJTs shows a maximum current gain of β = 44. A comprehensive study on the geometrical design is done in order to improve the on-state performances. For the first time, new cell geometries (square and hexagon) are presented for the SiC BJTs. The results show a significant improvement of the on-state characteristics because of a better utilization of the base area. At a given current gain, new cell geometries show a 42% higher current density and 21% lower ON-resistance. The results of this study, including an optimized fabrication process, are utilized in the 15 kV-class BJTs where a record high current gain of β = 139 is achieved.

    Ultra-high-voltage PiN diodes in two classes of voltage, i.e., 10+ kV using on-axis 4H-SiC and 15 kV-class off-axis 4H-SiC, are presented. O-JTE is utilized for 15 kV-class PiN diodes, while three steps ion-implantation are used to form the JTE in 10+ kV PiN diodes. Carbon implantation followed by high-temperature annealing is also performed for the 10+ kV PiN diodes in order to enhance the lifetime. Both type diodes depict conductivity modulation in the drift layer. No bipolar degradation is observed in 10+ kV PiN diodes.

  • 20.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ul Hassan, Jawad
    Bergman, Peder
    Zetterling, Carl Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication and Design of 10 kV PiN Diodes Using On-axis 4H-SiC2014In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 778-780, p. 836-840Article in journal (Refereed)
    Abstract [en]

    10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 mu s. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a V-F of 3.3 V at 100 A/cm(2) at 25 degrees C, which was decreased to 3.0 V at 300 degrees C.

  • 21.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, B.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hassan, J. U.
    Bergman, P.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes2015In: Proceedings of the International Symposium on Power Semiconductor Devices and ICs, IEEE conference proceedings, 2015, p. 269-272Conference paper (Refereed)
    Abstract [en]

    Degradation-free ultrahigh-voltage (>10 kV) PiN diodes using on-axis 4H-SiC with low forward voltage drop (VF = 3.3 V at 100 A/cm2) and low differential on-resistance (RON = 3.4 m.cm2) are fabricated, measured, and analyzed by device simulation. The devices show stable on-state characteristics over a broad temperature range up to 300 °C. They show no breakdown up to 10 kV, i.e., the highest blocking capability for 4H-SiC devices using on-axis to date. The minority carrier lifetime (τP) is measured after epitaxial growth by time resolved photoluminescence (TRPL) technique at room temperature. The τP is measured again after device fabrication by open circuit voltage decay (OCVD) up to 500 K.

  • 22.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Area-optimized JTE simulations for 4.5 kV non ion-implanted sic BJT2013In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 740-742, p. 974-977Article in journal (Refereed)
    Abstract [en]

    Non ion-implantation mesa etched 4H-SiC BJT with three-zone JTE of optimized lengths and doses (descending sequences) has been simulated. This design presents an efficient electric field distribution along the device. The device area has been optimized and considerably reduced. As a result of this comprehensive optimization, a high breakdown voltage (>6 kV) and high current gain (β=50) have been achieved; meanwhile the device area with a constant emitter and base contact area (300×300 μm2) will be reduced by about 30%.

  • 23.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Jacobs, Keijo
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 1, p. 63-66Article in journal (Refereed)
    Abstract [en]

    Implantation-free mesa-etched ultra-high-voltage (0.08 mm(2)) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm(2) is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.

  • 24.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance2015In: 2015 IEEE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD), IEEE , 2015, p. 249-252Conference paper (Refereed)
    Abstract [en]

    Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of beta = 44 at a current density of 472 A/cm(2), and a specific on-resistance of R-ON = 18.8 m Omega.cm(2) is obtained for the device. The device shows a negative temperature coefficient of the current gain (beta = 14.5 at 200 degrees C) and a positive temperature coefficient of on-resistance (R-ON = 57.3 m Omega.cm(2) at 200 degrees C).

  • 25.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    15 kV-Class implantation-Free 4H-SiC BJTs with Record High Current Gain2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Other academic)
    Abstract [en]

    Implantation-free mesa-etched ultra-high-voltage 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension (O-JTE) is utilized in order to obtain a high and stable breakdown voltage without ion implantation. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared. The base size effect is investigated in order to improve current gain.

  • 26.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Comprehensive Study on the Geometrical Effects in High Power 4H-SiC BJTs2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 3, p. 882-887Article in journal (Refereed)
    Abstract [en]

    Geometrical effects on the forward characteristics of high-power bipolar junction transistors are studied.An implantation-free area optimized junction termination is implemented in order to have a stable breakdown voltage. The effect of varying the emitter-base geometry, i.e., the emitter width (WE), the base width (WB), emitter contact–emitter edge distance (Wn), and base contact–emitter edge (Wp) on the on-state characteristics is studied in the different emitter cell geometries. The emitter size effect shows the highest influence on the current gain (β). It shows a significant effect on the β (single finger design, about 61%; square cell geometry, about 98%;hexagon cell geometry, about 90%). The base size effect also shows a significant improvement on the β of about 23% at a given WE.

  • 27.
    Salemi, Arash
    et al.
    KTH.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    10+ kV implantation-free 4H-SiC PiN diodes2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Ltd , 2017, p. 423-426Conference paper (Refereed)
    Abstract [en]

    Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.

  • 28.
    Salemi, Arash
    et al.
    KTH.
    Elahipanah, Hossein
    KTH.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN Diodes2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, p. 568-572Conference paper (Refereed)
    Abstract [en]

    Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.

  • 29.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Geometrical effect dependency on the on-state characteristics in 5.6 kV 4H-SiC BJTs2016In: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015, Trans Tech Publications Ltd , 2016, p. 958-961Conference paper (Refereed)
    Abstract [en]

    The influence of varying the emitter-base geometry, i.e., the emitter width (WE), emitter contact-emitter edge distance (Wn), and base contact-emitter edge (Wp) on the on-state characteristics in 5.6 kV implantation free 4H-SiC BJTs is investigated. The BJTs present a clear emitter size effect pointing out that surface recombination has a significant influence on current gain (β). The results show that the influence of varying Wp on the β is higher than Wn. A distance of 3 μm between emitter contact and base contact to the emitter edge (Wn = Wp = 3 μm) is the optimized value to have a BJT with a high β, and low on-resistance (RON) at a given WE.

  • 30.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Investigation of the breakdown voltage in high voltage 4H-SiC BJT with respect to oxide and interface charges2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821-823, p. 834-837Article in journal (Refereed)
    Abstract [en]

    Ion implantation in silicon carbide (SiC) induces defects during the process. Implantation free processing can eliminate these problems. The junction termination extension (JTE) can also be formed without ion implantation in SiC bipolar junction transistor (BJT) using a well-controlled etching into the epitaxial base layer. The fixed charges at the SiC/SiO2 interface modify the effective dose of the JTEs, leakage current, and breakdown voltage. In this paper the influence of fixed charges (positive and negative) and also interface trap density at the SiC/SiO2 interface on the breakdown voltage in 4.5 kV 4H-SiC non-ion implanted BJT have been simulated. SiO2 as a surface passivation layer including interface traps and fixed charges has been considered in the analysis. Simulation result shows that the fixed charges influence the breakdown voltage significantly more than the interface traps. It also shows that the positive fixed charges reduce the breakdown voltage more than the negative fixed charges. The combination of interface traps and fixed charges must be considered when optimizing the breakdown voltage.

  • 31.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 10, p. 1069-1072Article in journal (Refereed)
    Abstract [en]

    Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (R-ON), current density (J(C)), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.

  • 32.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    State of the art Power Switching Devices in SiC and their Applications2016In: 2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), IEEE, 2016, p. 122-123Conference paper (Refereed)
    Abstract [en]

    This paper gives an overview of the current state of the art device technology for SiC discrete devices and applications. The superior switching performance is discusses as well as the energy efficiency of SiC devices. New emerging applications of SiC devices are also discussed focusing on high temperature capability such as integrated digital and analog circuits up to 600 C. Finally, MEMS and Bio applications will be briefly reviewed.

1 - 32 of 32
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf