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  • 1.
    Amin, Yasar
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Shao, Botao
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Design and Analysis of Efficient and Compact Antenna for Paper Based UHF RFID Tags2008In: ISAPE 2008: THE 8TH INTERNATIONAL SYMPOSIUM ON ANTENNAS, PROPAGATION AND EM THEORY, PROCEEDINGS, VOLS 1-3 / [ed] Su D; Yan Z, NEW YORK: IEEE , 2008, p. 62-65Conference paper (Refereed)
    Abstract [en]

    Paper substrate is one of the paramount nominees for Radio Frequency Identification (RFID) tags but at the same time it is extremely prone towards environmental changes. In this paper, antennas for UHF RFID tags on paper based substrate are investigated and analyzed for the first time to evaluate the effect of change in dielectric constant on the antenna parameters and performance. On the basis of analysis a concrete meander line antenna is proposed, designed and evaluated which has tremendous immunity towards variation in dielectric constant.

  • 2.
    Amin, Yasar
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Prokkola, Satu
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Robust Flexible High Performance UHF RFID Tag Antenna2009In: 2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), NEW YORK: IEEE , 2009, p. 235-239Conference paper (Refereed)
    Abstract [en]

    This paper describes a novel Flexo, Screen and Inkjet printed rounded edges bowtie antenna with T-matching stubs on paper, Kapton (HN) and Teonex Q51 substrate. Paper is one of the paramount nominees for Radio Frequency Identification (RFID) tags, for the reason that it is one of the widely and the cheapest available substrates. Kapton (HN) and Teonex Q51 are distinguished for their flexibility and reliability. The antenna exhibits compact size with outstanding read range of 4 meters and complete coverage of UHF RFID band (860-960 MHz). The results show extreme immunity of versatile antenna against harsh environments. These antennas are flexible which give autonomy for their applications.

  • 3.
    Amin, Yasar
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Design of Novel Paper-based Inkjet Printed Rounded Corner Bowtie Antenna for RFID Applications2010In: Sensors & Transducers Journal, ISSN 2306-8515, E-ISSN 1726-5479, Vol. 115, no 4, p. 160-167Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel inkjet printed rounded corner bowtie antenna with T-matching stubs on paper substrate which is the cheapest and widest available substrate. The antenna exhibits compact size with outstanding read range and complete coverage of UHF RFID band (860-960 MHz). The results show extreme immunity of proposed antenna against paper dielectric constant variation.

  • 4.
    Amin, Yasar
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Prokkola, Satu
    Shao, Botao
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Low Cost Paper Based Bowtie Tag Antenna for High Performance UHF RFID Applications2009In: NANOTECH CONFERENCE & EXPO 2009, VOL 1, TECHNICAL PROCEEDINGS - NANOTECHNOLOGY 2009: FABRICATION, PARTICLES, CHARACTERIZATION, MEMS, ELECTRONICS AND PHOTONICS / [ed] Laudon M; Romanowicz B, BOCA RATON: CRC PRESS-TAYLOR & FRANCIS GROUP , 2009, p. 538-541Conference paper (Refereed)
    Abstract [en]

    Radio frequency identification (RFID) antenna's versatility in terms of complete coverage of UHF RFID band (860-960 MHz), while keeping the cost factor low, is an important aspect of today's growing demand for security and tracking of multiple objects in a very short time in addition to tag's readability across the globe. This paper presents a novel inkjet printed rounded corner bowtie antenna with T-matching stubs on paper substrate which is the cheapest and widest available substrate. The antenna exhibits compact size with outstanding read range.

  • 5.
    Amin, Yasar
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Prokkola, Satu
    Shao, Botao
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Inkjet Printed Paper Based Quadrate Bowtie Antennas For UHF RFID Tags2009In: 11TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY, VOLS I-III, PROCEEDINGS, - UBIQUITOUS ICT CONVERGENCE MAKES LIFE BETTER!, TAEJON: ELECTRONICS TELECOMMUNICATIONS RESEARCH INST , 2009, p. 109-112Conference paper (Refereed)
    Abstract [en]

    Paper substrate is one of the paramount nominees for Radio Frequency Identification (RFID) tags, for the reason that it is one of the widely and the cheapest available substrates. In this paper, for the first time quadrate bowtie antennas with round corners [1] are realized and analyzed on paper substrate for UHF RFID tags. These inkjet printed antennas exhibit high performance which give freedom for their applications. Their area is smaller than the general triangle bowtie antenna and have advantages of smaller area, better return loss in high frequency and higher gain in normal direction of antenna plane compared with general triangular bowtie antenna.d

  • 6.
    Amin, Yasar
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Shao, Botao
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Prokkola, Satu
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Design and Characterization of Efficient Flexible UHF RFID Tag Antennas2009In: 2009 3RD EUROPEAN CONFERENCE ON ANTENNAS AND PROPAGATION, NEW YORK: IEEE , 2009, p. 2682-2684Conference paper (Refereed)
    Abstract [en]

    In this paper meander line antennas with end tip loading, designed for UHF RFID tags are presented. These novel antennas are screen printed on Kapton HN for European frequency band (866-868 MHz) and for North American frequency band (902-928 MHz). Asahi ink is used for screen printing of 25 mu m thick antenna traces which remains conductive even after several times sharp bending of these tag antennas. The results show that the antennas exhibit high performance regarding smaller area, high realized gain and better return loss in the frequency band of interest. These antennas are extremely flexible which give autonomy for their applications.

  • 7. Driussi, F.
    et al.
    Esseni, D.
    Selmi, L.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Grasby, T. J.
    Leadley, D. R.
    Mescot, X.
    On the electron mobility enhancement in biaxially strained Si MOSFETs2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 4, p. 498-505Article in journal (Refereed)
    Abstract [en]

    This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.

  • 8.
    Feng, Yi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University, China .
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Huang, Yiping
    Fudan University.
    Development and experimental verification of analytical models for printable interdigital capacitor sensors on paperboard2009In: 2009 IEEE Sensors, IEEE Sensors Council, 2009, p. 1034-1039Conference paper (Refereed)
    Abstract [en]

    Printed interdigital capacitor DWI on paperboard is a promising solution for low-cost sensors in intelligent packaging applications. The currently available analytical models of multi-layered IDCs are targeted to those fabricated by conventional semiconductor process. For this reason, we have adapted two promising models and assessed their accuracies by comparison with experimental data. We modified these models by treating the paper as non-infinite thick substrate and taking the effect of printed metal thickness into account. The models are studied further to reveal the relationship between the response of capacitance change and various geometric parameters which enables a quick way of obtaining the optimum IDC structure design. The modified Gevorgian model fits our experimental data best, and the sensitivity of IDCs is largely affected by its spatial wavelength and the thickness of sensing material layer, while the finger number, length and metallization ratio have minor impact.

  • 9. Ghandi, R.
    et al.
    Kolahdouz, M.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wise, R.
    Wejtmans, Hans
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Effect of strain, substrate surface and growth rate on B-doping in selectively grown SiGe layers2008In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, p. 334-336Article in journal (Refereed)
    Abstract [en]

    In this work, the role of strain and growth rate on boron incorporation in selective epitaxial growth (SEG) of B-doped Si1-xGex (x=0.15-0.25) layers in recessed or unprocessed (elevated) openings for source/drain applications in CMOS has been studied. A focus has been made on the strain distribution and B incorporation in SEG of SiGe layers.

  • 10.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lu, Jun
    Wise, R.
    Wejtmans, H.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    High boron incorporation in selective epitaxial growth of SiGe layers2007In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 18, no 7, p. 747-751Article in journal (Refereed)
    Abstract [en]

    Incorporation of high amount of boron in the range of 1 x 10(20)-1 x 10(21) cm(-3) in selective epitaxial growth (SEG) of Si1-xGex (x = 0.15-0.315) layers for recessed or elevated source/drain junctions in CMOS has been studied. The effect of high boron doping on growth rate, Ge content and appearance of defect in the epi-layers was investigated. In this study, integration issues were oriented towards having high layer quality whereas still high amount of boron is implemented and the selectivity of the epitaxy is preserved.

  • 11.
    Hållstedt, Julius
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Epitaxy and characterization of SiGeC layers grown by reduced pressure chemical vapor deposition2004Licentiate thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Heteroepitaxial SiGeC layers have attracted immenseattention as a material for high frequency devices duringrecent years. The unique properties of integrating carbon inSiGe are the additional freedom for strain and bandgapengineering as well as allowing more aggressive device designdue to the potential for increased thermal budget duringprocessing. This work presents different issues on epitaxialgrowth, defect density, dopant incorporation and electricalproperties of SiGeC epitaxial layers, intended for variousdevice applications.

    Non-selective and selective epitaxial growth of Si1-x-yGexCy(0≤x≤30, ≤y≤0.02) layershave been optimized by using high-resolution x-ray reciprocallattice mapping. The incorporation of carbon into the SiGematrix was shown to be strongly sensitive to the growthparameters. As a consequence, a much smaller epitaxial processwindow compared to SiGe epitaxy was obtained. Differentsolutions to decrease the substrate pattern dependency (loadingeffect) of SiGeC growth have also been proposed. The key pointin these methods is based on reduction of surface migration ofthe adsorbed species on the oxide. In non-selective epitaxy,this was achieved by introducing a thin silicon polycrystallineseed layer on the oxide. The thickness of this seed layer had acrucial role on both the global and local loading effect, andon the epitaxial quality. Meanwhile, in selective epitaxy,polycrystalline stripes introduced around the oxide openingsact as migration barriers and reduce the loading effecteffectively. Chemical mechanical polishing (CMP) was performedto remove the polycrystalline stripes on the oxide.

    Incorporation and electrical properties of boron-doped Si1-x-yGexCylayers (x=0.23 and 0.28 with y=0 and 0.005) with aboron concentration in the range of 3x1018-1x1021atoms/cm3 have also been investigated. In SiGeClayers, the active boron concentration was obtained from thestrain compensation. It was also found that the boron atomshave a tendency to locate at substitutional sites morepreferentially compared to carbon. These findings led to anestimation of the Hall scattering factor of the SiGeC layers,which showed good agreement with theoretical calculations.

    Keywords:Silicon germanium carbon (SiGeC), Epitaxy,Chemical vapor deposition (CVD), Loading effect, Highresolution x-ray diffraction (HRXRD), Hall measurements, Atomicforce microscopy (AFM).

  • 12.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Integration of epitaxial SiGe(C) layers in advanced CMOS devices2007Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices.

    Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained.

    Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe.

    The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer.

    Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer.

    Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm.

    SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices.

    Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage.

  • 13.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Blomqvist, Mats
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Persson, P. O. Å.
    Thin Film Physics Division, Department of Physics, Linköpings Universitet.
    Hultman, L.
    Thin Film Physics Division, Department of Physics, Linköpings Universitet.
    Radamson, Henry
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    The effect of carbon and germanium on phase transformation of nickel on Si1-x-yGexCy epitaxial layers2004In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 95, no 5, p. 2397-Article in journal (Refereed)
    Abstract [en]

    The influence of carbon and germanium on phase transformation and sheet resistance of Ni on epitaxially grown Si1-x-yGexCy (0less than or equal toxless than or equal to0.24 and 0less than or equal toyless than or equal to0.01) layers annealed in a temperature range of 360 to 900degreesC has been investigated. The role of strain relaxation or compensation in the reaction of Ni on Si1-x-yGexCy layers due to Ge or C out-diffusion to the underlying layer during the phase transformation has also been investigated. The formed NiSiGe layers were crystalline, with strong (020)/(013) growth orientation in the direction, but the thermal stability decreased rapidly with increasing Ge amount due to agglomeration. However, this thermal behavior was shifted to higher annealing temperatures when carbon was incorporated in the SiGe layers. A carbon accumulation at the interface of NiSiGeC/SiGeC has been observed even at low-temperature annealing, which is suggested to retard the phase transformation and agglomeration of Ni/SiGeC system.

  • 14.
    Hållstedt, Julius.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs2008In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, p. 117-120Article in journal (Refereed)
    Abstract [en]

    Today MOSFET devices are approaching gate lengths on the order of 10 nm. This sets extreme demands on gate patterning technique. This paper describes a side wall transfer lithography technique to pattern decananomeer MOSFETs or nanowires. A correlated line edge roughness leading to a very low line width roughness was demonstrated for the patterned gates. Moreover, the technology was shown to be robust and reproducible with high yield and uniformity suitable for mass fabrication. Finally, integration of the sidewall transfer lithography was performed in various novel MOSFET devices.

  • 15.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Edholm, Jonas
    Lu, J.
    Uppsala University, Ångström Laboratory.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A robust spacer gate process for deca-nanometer high-frequency MOSFETs2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 3, p. 434-439Article in journal (Refereed)
    Abstract [en]

    This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

  • 16.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Baubinas, R.
    Matukas, J.
    Palenskis, V.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Application of selective epitaxy for formation of ultra shallow SiGe-based junctions2004In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 114-115, no SPEC. ISS, p. 180-183Article in journal (Refereed)
    Abstract [en]

    Selective epitaxial growth (SEG) of B-, P- and As-doped Si1-xGex (0.12 < x < 0.26) layers on patterned substrates, aimed for source/drain ultra shallow junctions was investigated. The SiGe layers were deposited selectively on Si surface that is either unprocessed or previously in situ etched by HCl in the same run in a reduced pressure chemical vapor deposition reactor. In these investigations selectivity mode, pattern dependency (loading effect), defect generation and dopant incorporation in SiGe layers have been discussed. It was demonstrated that the growth rate increased in presence of B in SiGe while it decreased for P- and As-doped layers. The amount of Ge was constant for B-doped samples while it increased for As- and P-doped SiGe layers. The epitaxial quality was dependent on the Ge amount, growth rate and dopant concentration. The selectivity mode of the growth was dependent on B partial pressure, however, no effect was observed for P- or As-doping in SiGe layers. A resistivity value of similar to10(-3) Omega cm was obtained for B- and P-doped SiGe layers with optimized growth parameters.

  • 17.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, R.
    Texas Instruments, Dallas.
    Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors2008In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 103, no 5, p. 054907-Article in journal (Other academic)
    Abstract [en]

    This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1-xGex (x=0.14-0.32) layers. It is shown with a comprehensive experimental study that the local Si coverage of individual chips on patterned wafers is the main parameter for the layer profile in the epitaxial growth. This was explained by the gas depletion of the growth species in the low velocity boundary layer over the wafer. The gas depletion radius around each oxide opening was in the centimeter range which is related to the boundary layer thickness. The results from these experiments were applied to grow Si0.75Ge0.25 layers with B concentration of 4x10(20) cm(-3) selectively for elevated source and drains in fully depleted ultrathin body silicon on insulator p metal oxide semiconductor field effect transistor (p-MOSFET) devices. The epitaxy control was maintained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing a uniform gas depletion over the chips on the wafer.

  • 18.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Oehme, M.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Werner, J.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Lyutovich, K.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Kasper, E.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates2007In: ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference 2008, 2007, p. 319-322Conference paper (Refereed)
    Abstract [en]

    We present a comprehensive study of biaxially strained (up to similar to 3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage for the relaxed SiGe substrates compared to conventional implantation. The source to drain leakage in 80 nm devices was effectively reduced by increment of channel doping and rotation of the channel direction.

  • 19.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Parent, A.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Incorporation of boron in SiGe(C) epitaxial layers grown by reduced pressure chemical vapor deposition2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 03-jan, p. 97-101Article in journal (Refereed)
    Abstract [en]

    In this paper the strain and electrical properties of epitaxial in situ B-doped (10(18)-10(21) cm(-3)) SiGeC layers (23, 28% Ge and 0, 0.5% C) has been investigated. The growth rate was shown to have a significant increase at 3 x 10(-2) mTorr diborane partial pressure. This point coincides with an enhancement in boron incorporation, which was explained by the strain compensation effect of boron in the highly strained SiGeC layers. In these samples, the total Ge and C content was shown to remain constant with increasing diborane partial pressure. The substitutional/active dopant concentration in SiGe layers was obtained by high-resolution X-ray diffraction by measuring the strain compensation effect of boron. The interaction between C and B in SiGe matrix was also investigated. This was compared with the active dopant concentration obtained from Hall measurements in order to achieve a Hall scattering factor of 0.3-0.7 for dopant concentrations between 3 x 10(18) and 5 x 10(21) cm(-3). The resistivity values of these layers were in the range 2 x 10(-2) -4 x 10(-4) Omega cm. Finally, it was shown that boron atoms in SiGeC layers locate preferably at substitutional sites in contrary to carbon atoms at both substitutional and interstitial sites.

  • 20.
    Hållstedt, Julius.
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Parent, Arnaud
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Strain and electrical characterization of boron-doped SiGeC layers grown by chemical vapor deposition2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 31-33Article in journal (Refereed)
    Abstract [en]

    Incorporation, induced strain and electrical properties of boron and carbon in Si1-x-yGexCy epitaxial layers (x = 0.23 and 0.28 with y = 0 and 0.005) grown by chemical vapour deposition (CVD) have been studied. The boron concentration in the epitaxial layers was in the range of 3 x 10(18)-1 x 10(21) cm(-3). The growth rate enhanced weakly by increasing boron partial pressure up to 0.002 mtorr ( corresponding to 2 x 10(19) cm(-3)) where a significant increase in deposition rate was observed. In SiGeC layers, the active boron concentration was obtained from the strain compensation amount. It was also found that the boron atoms have a tendency to locate at substitutional sites more preferentially compared to carbon. The incorporation of boron in SiGeC layers was clearly improved in the range 2 x 10(19)-3 x 10(20) cm(-3). These investigations also enabled an estimation of the Hall scattering factor of the SiGeC layers. A comparison between our results with the previous theoretical calculations showed a good agreement. This created the possibility to evaluate the drift mobility in our samples.

  • 21.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Menon, Cyril
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Methods to reduce the loading effect in selective and non-selective epitaxial growth of sigec layers2004In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 109, no 03-jan, p. 122-126Article in journal (Refereed)
    Abstract [en]

    Various methods to reduce both global and local loading effect during non-selective and selective epitaxial growth of Si1-x-yGexCy (0.09 less than or equal to x less than or equal to 0.28 and 0 less than or equal to y less than or equal to 0.01) layers have been proposed. Evaluation of the proposed solutions for issues such as defect generation and the possibility for integration in device structures have been performed. The key point in these methods is based on reduction of surface diffusion of the adsorbed species on the oxide. In non-selective epitaxy, this was achieved by introducing a thin silicon polycrystalline seed layer on the oxide prior to Si1-x-yGexCy deposition. The thickness of this seed layer had a crucial role on both the global and local loading effect, and also on the epitaxial quality. Higher carbon content (y greater than or equal to 0.006) in Si1-x-yGexCy layers had no noticeable influence on the loading effect, however, the defect density was clearly increased in these layers. In selective epitaxy case, introducing square polycrystalline Si stripes around the oxide openings acting as diffusion barriers have reduced the loading effect effectively. Meanwhile, using Si nitride stripes showed no visible effect on Si1-x-yGexCy layer profile. Further decrease in loading effect can be performed by increasing the HCl partial pressure during epitaxy. Chemical-mechanical polishing (CMP) was performed to remove the polycrystalline stripe on the oxide.

  • 22.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Persson, P. O. Å.
    Department of Physics, Thin Film Physics Division, Linköpings Universitet.
    Hultman, L.
    Department of Physics, Thin Film Physics Division, Linköpings Universitet.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Growth of high quality epitaxial Si1-x-yGexCy layers by using chemical vapor deposition2004In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Applied Surface Science, Vol. 224, no 1-4, p. 46-50Article in journal (Refereed)
    Abstract [en]

    The epitaxial quality of non-selective and selective deposition of Si1-x-yGexCy (0 less than or equal to x less than or equal to 0.30, 0 less than or equal to y less than or equal to 0.02) layers has been optimized by using high-resolution reciprocal lattice mapping (HRRLM). The main goal was to incorporate a high amount of substitutional carbon atoms in Si or Si1-xGex matrix without creating defects. The carbon incorporation behavior was explained by chemical and kinetic effects of the reactant gases during epitaxial process. Although high quality epitaxial Si1-yCy layers can be deposited, lower electron mobility compared to Si layers was observed.

  • 23.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels2006In: ECS Transactions, ISSN 1938-5862, E-ISSN 1938-6737, Vol. 3, no 7, p. 67-72Article in journal (Refereed)
    Abstract [en]

    State of the art bulk and fully depleted SOI Si and SiGe channel pMOSFET devices with gate lengths ranging from 0.1 to 200 μm were fabricated and analyzed in terms of drain current drivability, mobility and noise performance. In general the SOI devices demonstrated superior mobility and significantly reduced I/f noise compared to bulk devices maintaining a well controlled short channel effects due to the ultra thin body.

  • 24.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels2006In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 6, p. 466-468Article in journal (Refereed)
    Abstract [en]

    The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

  • 25. Kolahdouz, M.
    et al.
    Ghandi, R.
    Hållstedt, Julius.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Osling, M.
    Wise, R.
    Wejtmans, Hans
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    The influence of Si coverage in a chip on layer profile of selectively grown Si1-xGex layers using RPCVD technique2008In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, p. 257-258Article in journal (Refereed)
    Abstract [en]

    The influence of chip layout (Si coverage and geometry) on the pattern dependency of selective epitaxy of SiGe layers has been investigated. The variation of Ge content and the growth rate have been investigated from a chip-to-chip (local effect) or wafer-to-wafer. The results are described by transport and diffusion of the reactant molecules over the chips during epitaxy. Our investigations are focused on the origin of pattern dependency of the deposition and also propose methods to control this growth behavior.

  • 26.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Khatibi, Ali
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, Rick
    Riley, Deborah J.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Comprehensive Evaluation and Study of Pattern Dependency Behavior in Selective Epitaxial Growth of B-Doped SiGe Layers2009In: IEEE transactions on nanotechnology, ISSN 1536-125X, E-ISSN 1941-0085, Vol. 8, no 3, p. 291-297Article in journal (Refereed)
    Abstract [en]

    The influence of chip layout and architecture on the pattern dependency of selective epitaxy of B-doped SiGe layers has been studied. The variations of Ge-, B-content, and growth rate have been investigated locally within a wafer and globally from wafer to wafer. The results are described by the gas depletion theory. Methods to control the variation of layer profile are suggested.

  • 27.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, R.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Selective Epitaxial Growth with Full Control of Pattern Dependency Behavior for pMOSFET Structures2008In: SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES / [ed] Harame D; Caymax M; Koester S; Miyazaki S; Rim K; Tillack B; Boquet J; Cressier J; Masini G; Reznicek A; Takagi S, 2008, Vol. 16, no 10, p. 153-158Conference paper (Refereed)
    Abstract [en]

    This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in pMOSPET structures. The pattern dependency behavior of tile growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by gas depletion theory of the growth species in tile stationary boundary layer over tile wafer. The control of SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a water pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.

  • 28.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, R.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Selective Epitaxial Growth with Full Control of Pattern Dependency Behavior for pMOSFET Structures2009In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 156, no 3, p. H169-H171Article in journal (Refereed)
    Abstract [en]

    This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) structures. The pattern dependency behavior of the growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by the gas depletion theory of the growth species in the stationary boundary layer over the water. Control of the SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.

  • 29.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Noise Properties of High-Mobility, 80 nm Gate Length MOSFETs on Supercritical Virtual Substrates2008In: SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES   : MATERIALS, PROCESSING, AND DEVICES / [ed] Harame D; Caymax M; Koester S; Miyazaki S; Rim K; Tillack B; Boquet J; Cressier J; Masini G; Reznicek A; Takagi S, 2008, Vol. 16, no 10, p. 529-537Conference paper (Refereed)
    Abstract [en]

    It was found that for strained Si channel layers of supercritical thickness oil relaxed SiGe virtual substrates, the 1/f noise oil,average is maintained at the same level as in unstrained devices. Short gate length nMOSFETs were analyzed statistically and the noise level variation, across a large number of samples, was similar in strained and unstrained devices. The obtained noise level variation was partly related to gate length fluctuations across the wafer, which was evident from a small V-T fluctuation.

  • 30.
    Radamson, Henry H.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Application of high-resolution x-ray diffraction for detecting defects in SiGe(C) materials2005In: Journal of Physics: Condensed Matter, ISSN 0953-8984, E-ISSN 1361-648X, Vol. 17, no 22, p. S2315-S2322Article in journal (Refereed)
    Abstract [en]

    The application of high-resolution x-ray diffraction for detecting and distinguishing defects in SiGe(C) layers is presented. A depth profile of the defects in SiGe/Si multilayers has been performed by using high-resolution reciprocal lattice mapping at different asymmetric reflections. Transmission electron microscopy was also applied in order to observe defects in the layers and these results were linked with the x-ray analysis. The substitutional C or B concentration in SiGe was measured by the shift of layer peak compared to the intrinsic layers. The thermal stability of the SiGe layers was investigated in order to rank the epitaxial quality of the SiGe below the detection limit of x-ray technique. It has also been demonstrated that x-ray analysis can be used for in-line process monitoring of layers grown in small device openings on patterned substrates. These types of analysis have also been used routinely for the evaluation of processed samples.

  • 31.
    Radamson, Henry H.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Growth and characterization of boron-doped Si1-x-yGe xCy layers grown by reduced pressure chemical vapor deposition2005In: Defects and Diffusion in Semiconductors - an Annual Retrospective VIII, Trans Tech Publications Inc., 2005, p. 39-49Chapter in book (Refereed)
    Abstract [en]

    In this paper, the following issues: epitaxial growth, boron incorporation and electrical properties of Si1-x-yGexCy layers grown by reduced pressure chemical vapor deposition (RPCVD) are presented. Furthermore, diffusion of carbon and boron in silicon-based material is also discussed.

  • 32.
    Radamson, Henry H.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of selective SiGe epitaxy for source/drain application in MOSFETs2006In: Semiconductor Science and Technology, ISSN 0268-1242, E-ISSN 1361-6641, Vol. 22, no 1, p. 123-126Article in journal (Refereed)
    Abstract [en]

    The integration of HCl chemical vapour etching and selective epitaxy by chemical vapour deposition of B-doped SiGe layers for recessed source/drain junction application has been studied. A temperature range of 850-900 degrees C is proposed to be suitable for the etch process in order to obtain a smooth Si surface. This point is crucial for the epitaxial quality of grown SiGe: B layers. The selectivity of the epitaxy was not as good for high B partial pressure. However, Si0.76Ge0.24 layers with a B concentration of 6 x 10(20) cm(-3) were selectively grown. The pattern dependence of the etch and epitaxy process was studied and a calibration of this versus Si coverage of the chip was performed.

  • 33.
    Radamson, Henry H.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Kolahdouz, M.
    Ghandi, R.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Selective epitaxial growth of B-doped SiGe and HCl etch Si for the formation of SiGe: B recessed source and drain (pMOS transistors)2008In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, p. 84-86Article in journal (Refereed)
    Abstract [en]

    HCl chemical vapor etching and selective epitaxial growth of B-doped SiGe layers for recessed source/drain application for pMOSFET structure have been presented. The pattern dependency of the etch and epitaxy process were studied and the data correlated to the Si coverage of the chip.

  • 34.
    Radamson, Henry
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Formation of shallow source/drain junctions in MOSFET structures by using Cl-based processes in reduced pressure CVD reactors2006In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T126, p. 97-100Article in journal (Refereed)
    Abstract [en]

    A novel process to form shallow junctions for source) drain application in CMOS structures is presented. The method consists of two steps; first an HCl-etch followed by SiCl2H2-based selective epitaxy in the same run in a reduced pressure chemical vapour deposition chamber. Optimization of etch and epitaxy processes have been investigated and the active dopant concentration in SiGe layers grown was measured directly in the device openings.

  • 35.
    Radamson, Henry
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Menon, Cyril
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Improvement in epitaxial quality of selectively grown Si1-xGex layers with low pattern sensitivity for CMOS applications2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 03-jan, p. 25-30Article in journal (Refereed)
    Abstract [en]

    The selective growth of Si1-xGex structures (0.09<x<0.29) on patterned substrates aimed for channel layer application in metal oxide semiconductor field effect transistor (MOSFET) structures by using chemical vapor deposition (CVD) has been investigated. By optimizing the growth parameters, the surface roughness of these structures was improved and layers with better epitaxial quality was obtained. Furthermore, two methods are proposed to decrease the pattern-dependency of the epitaxy process. The key point in these methods is based on the reduction of surface diffusion of the adsorbed species on the oxide. This can be obtained by introducing square polycrystalline Si stripes around the oxide openings acting as diffusion barriers. Subsequently, chemical. mechanical polishing was performed to remove the polycrystalline stripe on the oxide. Evaluation of the proposed solution's for issues such as defect generation and the possibility for integration in device structures have also been performed.

  • 36. Rummukainen, M
    et al.
    Slotte, J
    Saarinen, K
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Material Physics, Semiconductor Materials, HMA.
    Hallstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Material Physics, Semiconductor Materials, HMA.
    Kuznetsov, A Y
    Vacancy-impurity pairs in n-type Si1-xGex studied by positron spectroscopy2006In: Physica. B, Condensed matter, ISSN 0921-4526, E-ISSN 1873-2135, Vol. 376, p. 208-211Article in journal (Refereed)
    Abstract [en]

    Positron annihilation spectroscopy was applied to study relaxed P-doped n-type Si1-xGex layers with Ge concentrations up to 30%. As-grown SiGe layers were defect-free and annihilations are superpositions from bulk Si and Ge. Proton irradiation at 2 MeV energy with a 1.6 x 10(15) cm(-2) fluence was used to produce saturated positron trapping in monovacancy related defects. The defects were identified as V-P pairs, the E-center. The distribution of Si and Ge atoms surrounding the E-center is the same as in the host lattice. The vacancy migration process leading to the formation of V-P pairs therefore does not seem to have a preference for either Si or Ge atoms. (c) 2005 Elsevier B.V. All rights reserved.

  • 37. Rummukainen, M
    et al.
    Slotte, J
    Saarinen, K
    Radamson, HH
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Kuznetsov, AY
    Vacancy-impurity pairs in relaxed Si1-xGex layers studied by positron annihilation spectroscopy2006In: Physical Review B. Condensed Matter and Materials Physics, ISSN 1098-0121, E-ISSN 1550-235X, Vol. 73, no 16Article in journal (Refereed)
    Abstract [en]

    Positron annihilation spectroscopy was applied to study relaxed P-doped n-type and undoped Si1-xGex layers with x up to 0.30. The as-grown SiGe layers were found to be defect free and annihilation parameters in a random SiGe alloy could be represented as superpositions of annihilations in bulk Si and Ge. A 2 MeV proton irradiation with a 1.6x10(15) cm(-2) fluence was used to produce saturated positron trapping in monovacancy related defects in the n-type layers. The defects were identified as V-P pairs, the E center. The distribution of Si and Ge atoms surrounding the E center was the same as in the host lattice. The process leading to the formation of V-P pairs therefore does not seem to have a significant preference for either Si or Ge atoms. In undoped Si1-xGex we find that a similar irradiation produces a low concentration of divacancies or larger vacancy defects and found no evidence of monovacancies surrounded by several Ge atoms.

  • 38.
    Seger, Johan
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jarmar, Tobias
    Ericson, Fredric
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Smith, Ulf
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Zhibin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Influence of a Si layer intercalated between Si0.75Ge0.25 and Ni on the behavior of the resulting NiSi1-uGeu film2004In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 96, no 12, p. 7179-7182Article in journal (Refereed)
    Abstract [en]

    The interaction of Ni films with epitaxially grown Si-capped and not capped Si0.75Ge0.25 layers on Si(100) at 500degreesC leads to the formation of NiSi1-uGeu films as a bilayer NiSi on NiSi0.75Ge0.25 with a rather clear compositional boundary. In the absence of a Si cap at the surface, NiSi0.75Ge0.25 is formed on NiSi. Epitaxy of NiSi on NiSi0.75Ge0.25, and vice versa, occurs across the compositional boundary. The crystallographic orientation of the NiSi1-uGeu films is strongly affected by the initial layer thicknesses and the layer sequence. Without a Si cap, the NiSi1-uGeu films show an increased fiber texture with increasing Si0.75Ge0.25 thickness. In the presence of a Si cap, on the other hand, the texture collapses into a random orientation already for thin caps. Rapid diffusion of Ge at 500degreesC results in the presence of some Ge at the NiSi/Si interface for a NiSi0.75Ge0.25/NiSi/Si structure. This diffusion is accompanied by an increased roughness at the NiSi/Si interface, as compared to the quite flat NiSi/Si interface in the absence of Ge. For thin Si caps, severe interface roughening with thick NiSi0.75Ge0.25 grains protruding deeply into the remaining Si0.75Ge0.25 is observed.

  • 39.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Liu, Ran
    Fudan University.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Process-dependence of inkjet printed folded dipole antenna for 2.45 GHZ RFID tags2009In: 2009 3RD EUROPEAN CONFERENCE ON ANTENNAS AND PROPAGATION, VOLS 1-6, NEW YORK: IEEE , 2009, p. 2336-2339Conference paper (Refereed)
    Abstract [en]

    This paper focuses on the process dependence of an inkjet printed folded dipole antenna based on practical parameters in a typical inkjet printing process. We present the effect of width variations and number of overprinting times on the antenna properties such as gain, radiation efficiency and input impedance. Furthermore we investigate the read range degradation of the tag on which the antenna is attached, due to width or thickness variations. In addition, an comparison between an inkjet printed antenna on a regular paper substrate and a copper antenna on Printed Circuit Board (PCB) was made, manifesting the strong competitiveness of the printed silver antenna as a low cost solution.

  • 40.
    Suvar, Erdal
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Haralson, Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    As- or P-doped Si layers grown by RPCVD for emitter application in SiGeCHBTs2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 34-36Article in journal (Refereed)
    Abstract [en]

    A new module for the emitter formation in a bipolar transistor is presented. Arsenic- or phosphorus-doped polycrystalline silicon layer for the emitter formation is deposited in a reduced pressure chemical vapor deposition reactor using silane as the silicon source gas. Characteristics such as the carrier concentration, conductivity, surface morphology, and thermal stability of the polycrystalline-silicon layer as well as the influence this layer has on a SiGeC transistor structure during the drive-in step area studied. The active carrier concentration of the as-grown sample is strongly dependent on the deposition temperature, especially arsenic doped layers which exhibit more than one order of magnitude difference. However, the carrier concentration for the As- or P-doped layer were comparable to that of a standard in-situ doped poly-crystalline layer after a dopant activation at 925 degrees C for 10s.

  • 41.
    von Haartman, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Seger, Johan
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Low-frequency noise in SiGe channel pMOSFETs on ultra-thin body SOI with Ni-silicided source/drain2005In: Noise and Fluctuations, 2005, p. 307-310Conference paper (Refereed)
    Abstract [en]

    Thelow-frequency noise in buried SiGe channel pMOSFETs fabricated on ultra-thinbody silicon-on-insulator (SOI) substrates is investigated. The total thickness ofthe Si/SiGe/Si body structure, which is fully depleted (FD), is20 nm. The low-frequency noise properties are compared with FDSOI pMOSFETs with a 20 nm Si body. The effectof the Ni-silicide used in the Source/Drain were also studied,especially the case of Schottky-Barrier (SB) MOSFETs when the Ni-silicideis formed at the edges of the channel.

  • 42.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shili
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Critical technology issues for deca-nanometer MOSFETs2007In: ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2007, p. 27-30Conference paper (Refereed)
    Abstract [en]

    An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-K gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed.

  • 43.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellstrom, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shili
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Device integration issues towards 10 nm MOSFETs2006In: 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, NEW YORK, NY: IEEE , 2006, p. 25-30Conference paper (Refereed)
    Abstract [en]

    An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high K gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO(2)/Al(2)O(3). Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated, Finally ultra thin body Sol devices with high mobility SiGe channels are demonstrated.

1 - 43 of 43
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