Change search
Refine search result
123 1 - 50 of 117
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, Columbus, OH, United States .
    Asynchronous BFT for low power networks on chip2010In: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, p. 3240-3243Conference paper (Refereed)
    Abstract [en]

    Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdata equals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.

  • 2. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, Columbus, OH, United States .
    Power characteristics of networks on chip2010In: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, p. 3721-3724Conference paper (Refereed)
    Abstract [en]

    Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.

  • 3. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Power efficient networks on chip2009In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 2009, p. 105-108Conference paper (Refereed)
    Abstract [en]

    a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.

  • 4. Abd Elghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, United States .
    High throughput architecture for OCTAGON network on chip2009In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, IEEE , 2009, p. 101-104Conference paper (Refereed)
    Abstract [en]

    High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.

  • 5. Adiseno,
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 9, p. 1162-1168Article in journal (Refereed)
    Abstract [en]

    A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in RF Si-bipolar process with an f(T) of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP3 (+15.5-dBm OIP3) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA dc current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with - 10 to -41-dB S-11 is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 x 0.9 mm(2). The circuit is suitable for area-efficient multiband multistandard low-IF receivers.

  • 6. Adiseno,
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Multiband high-linearity front-end receivers for wireless applications2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, no 1, p. 59-67Article in journal (Refereed)
    Abstract [en]

    In this paper, a modified front-end receiver configuration, which consists of an LNA and mixer suitable for zero-IF or low-IF receivers, is presented. The idea is to achieve a better linearity for receivers by combining circuit and system level solutions. Three circuit topologies, two in bipolar and one in CMOS technology, are presented in this paper with their simulation results. One of the bipolar topologies has been implemented and measurement results are presented. An IIP3 of up to +0.6 dBm of a combined bipolar LNA and mixer is achieved, depending on frequency of interest and with an acceptable noise figure performance at a current consumption of less than 13 mA from 5 V supply voltage in one circuit and 3 V supply voltage in the other one. An IIP3 up to +5 dBm is achieved for the CMOS topology at a lower overall gain and acceptable noise figure (14.4 mA and 3 V). All circuits presented in this paper are wideband circuits, suitable for area-efficient multiband receivers.

  • 7. Aktas, A.
    et al.
    Ismail, Mohammed
    Pad de-embedding in RF CMOS2001In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 17, no 3, p. 8-11Article in journal (Refereed)
    Abstract [en]

    Welcome to The Chip! We remain committed to bringing you material you can use in your work and research. We solicit your contributions and input on what we present here. Material or short articles on chip design tips, modeling and characterization techniques, yield enhancement, packaging, and test are welcome, as well as news on new chips and start-ups, mergers, acquisitions, partnerships in the microchip business, etc. Please continue to e-mail us at ismail@ee.eng.ohio-state.edu or ntan@globespan.net. In this column, we discuss techniques for RF pad layout and de-embedding, a topic of great interest particularly for implementing radio frequency (RF) circuits in mainstream CMOS technology. Happy reading!

  • 8. Alzaher, H. A.
    et al.
    Elwan, H.
    Ismail, Mohammed
    A CMOS fully balanced second-generation current conveyor2003In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 50, no 6, p. 278-287Article in journal (Refereed)
    Abstract [en]

    The design and implementation of a high performance CMOS fully balanced second-generation current conveyor (FBCCII) is presented. The proposed circuit is essential to extend the use of the CCII based circuits to integrated circuits (ICs) applications. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA). A low power class AB circuit realization is implemented in a 1.2-mum CMOS technology and its different characteristics are measured. Design examples of realizing fully balanced variable gain amplifiers (VGAs) and a bandpass filter based on the proposed FBCCII are given. Experimental results of the proposed circuits are included.

  • 9. Alzaher, H. A.
    et al.
    Elwan, H. O.
    Ismail, Mohammed
    A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 1, p. 27-37Article in journal (Refereed)
    Abstract [en]

    A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.

  • 10. Alzaher, H. A.
    et al.
    Elwan, H. O.
    Ismail, Mohammed
    CMOS digitally programmable filter for multi-standard wireless receivers2000In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 36, no 2, p. 133-135Article in journal (Refereed)
    Abstract [en]

    A technique for designing digitally programmable CMOS integrated filters for multi-standard wireless receivers is presented. The technique exhibits the wide frequency range of the transconductance amplifier filters while offering improved linearity. It utilises digitally controlled current followers to provide precise frequency characteristics that can be tuned over a wide range. A digitally tuned lowpass filter is designed for implementing the channel-select filter in the baseband chain of a multi-standard CMOS wireless receiver. Simulation and experimental results obtained from a 1.2 mu m chip show a programmable frequency response covering the IS-54, GSM, IS-95 and WCDMA wireless standards.

  • 11. Alzaher, H. A.
    et al.
    Elwan, H. O.
    Ismail, Mohammed
    CMOS fully differential second-generation current conveyor2000In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 36, no 13, p. 1095-1096Article in journal (Refereed)
    Abstract [en]

    The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 mu m CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented.

  • 12. Alzaher, H. A.
    et al.
    Ismail, Mohammed
    Digitally tuned analogue integrated filters using R-2R ladder2000In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 36, no 15, p. 1278-1280Article in journal (Refereed)
    Abstract [en]

    A new technique for designing digitally tuned frequency selective analogue integrated circuits is proposed. The technique incorporates the R-2R ladder as a circuit element into the circuit design to provide precise frequency characteristics that can be tuned over a wide range. Two filters are described to illustrate the proposed approach. The proposed filters are used to implement the channel-select filter of a multi-standard direct conversion wireless receiver and the bandpass filter of a low IF frequency-hopping receiver.

  • 13. Alzaher, H.
    et al.
    Al-Ghamdi, M.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    CMOS low-power bandpass IF filter for Bluetooth2007In: Iet Circuits Devices & Systems, ISSN 1751-858X, Vol. 1, no 1, p. 7-12Article in journal (Refereed)
    Abstract [en]

    Design of a CMOS 18th-order IF (intermediate frequency) bandpass filter for integrated low-IF Bluetooth receivers is presented. The centre frequency and bandwidth of the filter are 3 and 1 MHz, respectively. The proposed filter is based on unity gain fully differential voltage buffers and provides efficient, low power and a small area design solution. The filter, including its automatic tuning circuit, occupies an area of 0.6 mm(2) in a standard 0.5 mu m-CMOS chip. Experimental results show that the filter satisfies the selectivity and dynamic range requirements of Bluetooth while operating from a total supply current of 0.9 mA.

  • 14. Alzaher, H.
    et al.
    Elwan, H.
    Ismail, Mohammed
    CMOS baseband filter for WCDMA integrated wireless receivers2000In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 36, no 18, p. 1515-1516Article in journal (Refereed)
    Abstract [en]

    A new second-order lowpass filter based on a single CMOS fully differential current conveyor is presented. Developed from the Sallen-Key highpass filter, the proposed filter is AC coupled and provides programmable gain. Moreover, the filter exhibits low noise, high linearity and low power, making it suitable for implementing the baseband filter of a WCDMA direct-conversion wireless receiver. A WCDMA filter having a programmable bandwidth around 2.1 MHz, a variable gain rang of 50dB and a DC notch below 2kHz using passive components below 5kW for resistors and 20pF for capacitors is implemented. Experimental and simulation results obtained from fabricated chips are included.

  • 15. Alzaher, H.
    et al.
    Ismail, Mohammed
    A CMOS fully balanced differential difference amplifier and its applications2001In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 48, no 6, p. 614-620Article in journal (Refereed)
    Abstract [en]

    This brief presents the fully balanced version of the differential difference amplifier (DDA) as an essential building block for implementing fully differential architectures of analog CMOS integrated circuits (ICs). We demonstrate that the fully balanced differential difference amplifier (FBDDA) provides the solution for systematically developing fully differential versions of any single-ended op-amp based circuit. We also show that, unlike the DDA, the FBDDA exhibits a wide input range without demanding complex circuitry. A low-power class AB CMOS realization of the proposed circuit has been designed and fabricated in a 1.2-mum technology. All proposed design techniques and circuits were experimentally verified.

  • 16. Alzaher, H.
    et al.
    Ismail, Mohammed
    A CMOS fully balanced four-terminal floating nullor2002In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 49, no 4, p. 413-424Article in journal (Refereed)
    Abstract [en]

    This paper presents design and implementation of a CMOS fully balanced realization of the four-terminal floating nullor (FTFN). The proposed fully balanced FTFN (FBFTFN) is an essential building block for implementing fully balanced architectures of both voltage and current-mode analog CMOS integrated circuits (ICs). A low-power class AB CMOS realization of the proposed circuit is fabricated in a 1.2-mum technology. The proposed circuit has numerous applications. Several applications including fully balanced amplifiers, filters, and sinusoidal oscillators are presented. All proposed design techniques and circuits are experimentally verified.

  • 17.
    Atallah, Jad G.
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Elnaggar, Mohammed Ismail
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A CMOS frequency synthesizer for multi-standard wireless devices2003In: Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems: Vols 1-3 / [ed] Hamdy, N., NEW YORK: IEEE , 2003, p. 1138-1141Conference paper (Refereed)
    Abstract [en]

    This paper presents a CMOS frequency synthesizer for wireless transceivers that support several communication standards namely GSM, WCDMA, IEEE 802.11b, and Bluetooth. The architecture is based on a multi-stage phase-locked loop where each stage differs from the others in the parameters of its charge pump and loop filter. It is designed using mathematical models and refined through simulation using different software tools depending on the required perspective. The architecture and the components presented pave the way to provide a low cost, fully integrated implementation.

  • 18.
    Atallah, Jad G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elnaggar, Mohammed Ismail
    Ohio State University.
    Future 4G front-ends enabling smooth vertical handovers2006In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, no 1, p. 6-15Article in journal (Refereed)
    Abstract [en]

    An overview is given of the most important effects that handover considerations have on the design of multistandard mobile radio transceivers. Focus is on the multitude of design issues and challenges that should be taken into account in the RF/analog front-end part. Topics discussed include the convergence challenge, wireless transceiver design challenge, wireless standards, handover initiation, interworking between GSM and DECT, idle mode issues, possible issues when mobile terminals miss pages, procedure while in active communication in DECT mode, procedure while in active communication in GSM mode, and GSM/WLAN handover.

  • 19.
    Atallah, Jad G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Michielsen, Wim
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Elnaggar, Mohammed Ismail
    Firstpass Semiconductors AB.
    A frequency planning and generation scheme for multi-standard wireless transceivers2005In: 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005: Gammarth, 11 December 2005 through 14 December 2005, 2005Conference paper (Refereed)
    Abstract [en]

    This work presents a novel frequency planning scheme associated with a reference frequency generation scheme that has the potential of providing low phase noise contribution for several wireless standards including DCS1800, WCDMA II and III, DECT, WLAN a/b/g and Bluetooth. The scheme is particularly useful when implemented in future technologies and can be extended to cover newer wireless standards in newer bands of interest. It uses a single multi-band voltage-controlled oscillator (VCO) with switching inductors and high speed dividers directly generating the quadrature outputs. The VCO itself covers the frequency ranges from 4.8GHz to 6GHz and from 6.8GHz to 8GHz. Its phase noise is -136dBc/Hz at 1MHz offset from a center frequency of 1.85GHz. The design is sent for fabrication using 0.18ÎŒm CMOS.

  • 20.
    Atallah, Jad. G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A direct conversion WiMAX RF receiver front-end in CMOS technology2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 37-40Conference paper (Refereed)
    Abstract [en]

    This paper presents a direct conversion RF receiver front-end supporting the WiMAX standard. The front-end is implemented in 0.18um CMOS technology and designed using the ARCHER software. It shows how the design flow can be accelerated starting from the standard specifications and going down to schematics. All this is accompanied by test benches to extract the relevant metrics. This front-end provides a total gain of 31dB, a noise figure of 3.3dB, an IIP2 of 49.5dBm, and an IIP3 of -13.8dBm.

  • 21. Ben Dhaou, I.
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Current mode, low-power, on-chip signaling in deep-submicron CMOS technology2003In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, no 3, p. 397-406Article in journal (Refereed)
    Abstract [en]

    qThis paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10% Experimental results on a set of benchmark signaling problems implemented in a 0.25-mum 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a twofold reduction in the power and a reduction of 1.4 times the area.

  • 22.
    Dora, Ayadi
    et al.
    University of Sfax, Tunisia .
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Loulou, Mourad
    University of Sfax, Tunisia.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    System level design of radio frequency receiver for IEEE 802.16 standard2008In: 3rd International Design and Test Workshop, 2008, IDT 2008, 2008, p. 82-86Conference paper (Refereed)
    Abstract [en]

    this paper presents a system level design of radio frequency receiver supporting WiMAX mobile standard. Based on direct conversion receiver, the distribution of the total radio system specifications to the individual receiver components is discussed. System level design techniques and theoretical calculation are developed. Simulation results and system simulation level are introduced for noise figure (NF), gain and linearity (third order intercept point, IIP3). Specifications obtained from the received budget can indicate that the noise and the linearity depend on the gain performance of the corresponding circuit blocks. The receiver achieves a total gain of 23dB and an IIP3 of -7.8dBm for low gain mode. It provides up to 68dB gain, 6.5dB noise figure and -16dBm IIP3 for high gain mode.

  • 23.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Ismail, Mohammed
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    On-chip versus off-chip passives analysis in radio and mixed-signal system-on-package design2004In: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), NEW YORK: IEEE , 2004, p. 109-116Conference paper (Refereed)
    Abstract [en]

    Advances of VLSI and packaging technologies enable condensed integration of system level functions in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP, and eliminate constraints between chip and package, a complete solution is needed to co-design and co-optimize chip and package in a total design plan with precise trade-offs of on-chip versus off-chip passives. In this paper, we present a complete and systematic design methodology for RF SoP/SoC. This methodology includes early analysis and design implementation. This early analysis is to estimate the performance and cost of each solution quickly and quantitively. Then, the best solution is found and implemented. For a better presentation, the method and design techniques are demonstrated through the design of a common emitter low noise amplifier (LNA) for 5GHz wireless LAN (local area network). Analytical equations of noise figure and transducer gain for the LNA with lossy package are also developed.

  • 24. Elwan, H.
    et al.
    Alzaher, H.
    Ismail, Mohammed
    A new generation of global wireless compatibility2001In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 17, no 1, p. 7-19Article in journal (Refereed)
  • 25. Elwan, H.
    et al.
    Gao, W.
    Sadkowski, R.
    Ismail, Mohammed
    CMOS low-voltage class-AB operational transconductance amplifier2000In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 36, no 17, p. 1439-1440Article in journal (Refereed)
    Abstract [en]

    The authors present a new low-voltage class-AB opt rational transconductance amplifier (OTA). The proposed OTA achieves a fast non slew-rate limited settling time with low power consumption. The circuit is power efficient when driving large capacitive loads. The OTA circuit is well suited For low-voltage low-power switched capacitor applications. Experimental results of the proposed circuit are included.

  • 26. Elwan, H.
    et al.
    Ismail, Mohammed
    A CMOS digitally programmable class AB OTA circuit2000In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 47, no 12, p. 1551-1556Article in journal (Refereed)
    Abstract [en]

    A new low-voltage CMOS digitally programmable operational transconductance amplifier (OTA) circuit is presented, The circuit utilizes simple class AB voltage buffers to provide a non slew rate limited performance with low standby power consumption. The OTA can be digitally programmed to maintain a constant settling time for different load capacitors without increasing the stand by power consumption. Experimental results from a 1.2-mum chip and comparisons with the regular folded cascode OTA circuit are given. The proposed circuit power consumption is found to be less than one third of a regular folded cascode OTA when driving a load capacitance of 35 pF, For the same power consumption level of 240 muA, the new circuit achieves a slew rate more than 10 V/mus while the traditional folded cascode fails to settle.

  • 27. Elwan, H. O.
    et al.
    Ismail, Mohammed
    Digitally programmable decibel-linear CMOS VGA for low-power mixed-signal applications2000In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 47, no 5, p. 388-398Article in journal (Refereed)
    Abstract [en]

    A new technique for realizing CMOS digitally controlled decibel-linear variable gain amplifier (VGA) circuits is described. CMOS VGA circuits employing the proposed technique are then given. Besides being effective and simple to use from a system point of view, the VGA circuits offer a stable gain characteristic with precise gain control that is achievable without component spreading, The VGA provides a 25 dB gain control range per stage, with 0.55-dB gain steps and a gain error of less than 0.5 dB. It can also be digitally reconfigured to give a 60-dB gain control range with 6-dB gain steps. The VGA circuit provides digital offset trimming, processes voltage or current input signals and operates in a fully differential configuration. Simulation and experimental results are provided.

  • 28. Elwan, H.
    et al.
    Ravindran, A.
    Ismail, Mohammed
    CMOS low power baseband chain for a GSM/DECT multistandard receiver2002In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, no 06-maj, p. 337-347Article in journal (Refereed)
    Abstract [en]

    A CMOS low power baseband chain for an integrated GSM/DECT multistandard receiver is presented. The chain uses a low power class AB digitally controlled filter and variable gain amplifier blocks to provide a low power, DSP controllable design solution. The chain and the building blocks are fabricated using standard N-well CMOS technology. Measurement results indicate that the chain can operate in GSM or DECT mode with a total standby current consumption less than 1.5 mA, while providing a gain control range from -6 dB to 23 dB in 1 dB steps. The chain achieves an input referred noise less than 31 nV/rootHz and an out-of-band IIP3 of more than 30 dBm.

  • 29. Elwan, H.
    et al.
    Soliman, A. M.
    Ismail, Mohammed
    A CMOS Norton amplifier-based digitally controlled VGA for low-power wireless applications2001In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 48, no 3, p. 245-254Article in journal (Refereed)
    Abstract [en]

    A CMOS variable-gain amplifier (VGA) for use in the baseband section of integrated wireless receivers is presented. The VGA circuit is based on a new CMOS realization of the Norton transresistance amplifier. The proposed CMOS realization operates from a 3-V supply voltage with rail-to-rail swing and class AB input and output stages. The standby current of the class AB stages employed can be accurately controlled, leading to a low power consumption, nonslew-rate-limited response. The VGA circuit provides a precise process-independent gain control range of 30 dB with 1-dB gain step. The circuit uses current division techniques to provide an area-efficient B-bit digital offset trimming capability Experimental results from a test chip fabricated through MOSIS are provided.

  • 30. Fayed, A. A.
    et al.
    Ismail, Mohammed
    A high speed, low voltage CMOS offset comparator2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 36, no 3, p. 267-272Article in journal (Refereed)
    Abstract [en]

    A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0-3.6 V and 1.6-2.0 V supplies and -40 to 125 degreesC temperature range on a typical 0.5 mum technology.

  • 31. Fayed, A. A.
    et al.
    Ismail, Mohammed
    A low-voltage, highly linear voltage-controlled transconductor2005In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 52, no 12, p. 831-835Article in journal (Refereed)
    Abstract [en]

    A low-voltage fully differential, voltage-controlled transconductor is described. The proposed transconductor achieves a wide input/control voltage range, with a highly linear transconductance factor and truly fully differential output currents. The transconductor is used to implement a G(m)-C adaptive forward equalizer (FE) for a 125 Mbps wire line transceiver using digital core transistors with channel length of no more than double the feature size in a typical digital CMOS 180-nm process and supply voltage as low as 1.6 V. The adaptive FE enables IEEE 1394b transceivers to operate over UTP-5 cables for up to 100 m in length. The transconductor stage occupies 1945 mu m(2) and consumes an average power of 418 mu w at 125 Mbps and 1.8-V supply.

  • 32. Fayed, A.
    et al.
    Ismail, Mohammed
    A digital calibration algorithm for implementing accurate on-chip resistors2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 47, no 3, p. 259-272Article in journal (Refereed)
    Abstract [en]

    A digital calibration algorithm that provides a systematic method for implementing accurate integrated resistors without compromising linearity or noise performance is described. The technique uses a single external resistor as a reference to implement multiple, different valued integrated resistors without requiring any accurate reference voltage. The algorithm provides a method to calibrate several on-chip resistors without replicating the calibration circuit, and it can achieve an arbitrary accuracy limited only by the external resistor's accuracy and mismatch errors. Terminations for two high speed wire line transceivers are implemented using the algorithm and simulations and measurements results show adequate performance across process, temperature, and supply voltage.

  • 33. Ghany, M. A. A. E.
    et al.
    Reehal, G.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, Columbus, United States .
    Power analysis for Asynchronous CLICH Network-on-Chip2010In: Proceedings - IEEE International SOC Conference, SOCC 2010, IEEE , 2010, p. 499-504Conference paper (Refereed)
    Abstract [en]

    Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICH) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches ( data satisfies a certain condition. The area of Asynchronous CLICH switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the ( data equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the ( data. The total metal resources required to implement Asynchronous design is decreased by 7%.

  • 34.
    Gonzalez, Delia Rodriguez De Liera
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    A programmable baseband chain for a WCDMA/WLAN(802.11b)multi-standard zero-IF receiver2005In: VLSI Circuits and Systems II, Pts 1 and 2 / [ed] Lopez, JF; Fernandez, FV; LopezVillegas, JM; DelaRosa, JM, BELLINGHAM: SPIE-INT SOC OPTICAL ENGINEERING , 2005, Vol. 5837, p. 396-403Conference paper (Refereed)
    Abstract [en]

    As we move towards convergent 4G Wireless encompassing both 3G cellular (WCDMA) for wide area networks and Wireless LAN for "hot-spots", the development of low power, low cost multi-band multi-standard wireless chipset solutions is a must. To this end this paper presents a programmable architecture for an analog baseband chain intended for use in a zero-IF multi-standard WCDMA/WLAN(802.11b) radio receiver. It also addresses the DC offset cancellation in the baseband chain. This is one of the major impairments in zero-IF receivers whose simplicity makes them suitable for single-chip multi-standard designs but where DC offset can reduce the receiver performance if a proper DC offset cancellation scheme is not devised. System level design of the baseband chain is given leading to design specifications of the different blocks in the chain. Extensive simulations carried out in MATLAB/SimuLink at the system level and in Cadence design tools at the circuit level show the performance of the system. The circuits will be fabricated in a 0.18 mu m CMOS process for a 1.8 V power supply.

  • 35.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Behavioral modeling of a programmable UWB/Bluetooth ADC2007In: 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007: Marrakech; 11 December 2007 through 14 December 2007, 2007, p. 1159-1162Conference paper (Other academic)
    Abstract [en]

    This paper presents the system level design of a programmable ADC that can cover the bandwidth-accuracy space of UWB and Bluetooth standards by employing a capacitive interpolation flash ADC and a sigma-delta ADC. The system level performance of the ADC architectures has been evaluated, and circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC can achieve 30 dB SINAD at 528 MSPS in UWB mode, and 86 dB SINAD at 1 MSPS in Bluetooth mode.

  • 36.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Design of a Reconfigurable ADC for UWB/Bluetooth Radios2008In: 2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA: Montreal, QC; 22 June 2008 through 25 June 2008, New York: IEEE , 2008, p. 205-208Conference paper (Refereed)
    Abstract [en]

    This paper presents the circuit implementation of a reconfigurable Analog to Digital Converter (ADC) for UWB and Bluetooth communication standards for mobile terminals. The bandwidth accuracy space is covered through smart configuration of a flexible capacitive interpolation ADC, used as stand-alone in UWB mode and as quantizer of a Sigma Delta ADC in Bluetooth mode. The ADC has been accurately modeled in Matlab/Simulink and then implemented at transistor level in a 180 nm CMOS process in the Cadence environment. The simulation results indicate that the ADC can achieve 30 dB SINAD at 528 MSPS in UWB mode, and 60 dB SINAD at 1 MSPS in Bluetooth mode.

  • 37.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Systematic design of a high-speed capacitive interpolative flash ADC2007Report (Other academic)
  • 38.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Neubauer, Harald
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    Hauer, Johann
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    A flexible algorithmic ADC for wireless sensor nodes2008In: Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008, p. 1213-1216Conference paper (Refereed)
  • 39.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Neubauer, Harald
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    Hauer, Johann
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    A programmable algorithmic ADC for low-power wireless applications2008Report (Other academic)
  • 40. Hella, M. M.
    et al.
    Ismail, Mohammed
    2 GHz controllable power amplifier in standard CMOS process for short-range wireless applications2002In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, no 06-maj, p. 363-368Article in journal (Refereed)
    Abstract [en]

    The authors present the design and implementation of a broadband radiofrequency power amplifier in a standard CMOS technology for short-range wireless applications. The amplifier is implemented in a standard 0.35 mum triple metal CMOS process. The amplifier is capable of delivering a maximum output power of 16.6 dBm at 1.91 GHz, and of 16 dBm at 2 GHz using a 3.3 V supply with an overall measured power added efficiency (PAE) of 33%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. The level of output power can be controlled in 2 dB Steps using a number of parallel semi-cascode stages.

  • 41. Helmy, Ahmed
    et al.
    Ismail, Mohammed
    A design guide for reducing substrate noise coupling in RF applications2006In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, no 5, p. 7-21Article in journal (Refereed)
  • 42. Hwang, C.
    et al.
    Hyogo, A.
    Kim, H. S.
    Ismail, Mohammed
    Sekine, K.
    Low voltage high-speed CMOS square-law composite transistor cell2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 25, no 3, p. 347-349Article in journal (Refereed)
    Abstract [en]

    A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\ +2V(ds,sat) and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3 V supply are given.

  • 43. Jalali-Farahani, Bahar
    et al.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Adaptive noise cancellation techniques in sigma-delta analog-to-digital converters2007In: Ieee Transactions on Circuits and Systems I-Regular Papers, ISSN 1549-8328, Vol. 54, no 9, p. 1891-1899Article in journal (Refereed)
    Abstract [en]

    Adaptive noise cancellation (ANC)) techniques that extract a desired signal from background noise have many applications in different engineering disciplines. In ANC, the corrupted signal is passed through a filter that tends to suppress the noise while leaving the original signal unchanged. This paper demonstrates that the adaptive noise cancellation technique can be embedded in the digital signal postprocessing of a sigma-delta analog-to-digital converter and effectively reduces the quantization noise as well as the thermal noise at the output of the converter. The combination of ANC and the noise-shaping technique enable high-resolution analog-to-digital conversion in wideband applications where noise shaping alone cannot provide enough suppression of quantization noise due to the low oversampling ratio.

  • 44.
    Jonsson, Fredrik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sandén, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Elnaggar, Mohammed Ismail
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A Voltage Controlled Oscillator with Automatic Amplitude Control in SiGe Technology2001In: 19th Norchip: Kista 12-13 November 2001, 2001, p. 28-33Conference paper (Refereed)
  • 45. Larson, F.
    et al.
    Kascak, P.
    Ismail, Mohammed
    A BiCMOS wideband amplifier for the extraction of base spreading resistance with noise measurement techniques2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 24, no 3, p. 187-194Article in journal (Refereed)
    Abstract [en]

    This paper presents a BiCMOS wide band amplifier optimized for maximum sensitivity to noise introduced in the base spreading resistance. It was used to characterize the base spreading resistance of bipolar devices found in Orbit's low-noise, n-well BiCMOS process available through MOSIS. The base spreading resistance is extracted by measuring the output power spectral density of the aforementioned amplifier and isolating the amount caused by thermal noise in the base. The results give insight as to what noise sources are significant in this technology.

  • 46. Li, S. G.
    et al.
    Ismail, Mohammed
    A 7 GHz 1.5-V dual-modulus prescaler in 0.18 mu m copper-CMOS technology2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 1, p. 89-95Article in journal (Refereed)
    Abstract [en]

    A dual-modulus prescaler using True-Single-Phase-Clock (TSPC) logic is implemented in a 0.18 mum copper CMOS technology. With careful design and optimization the prescaler is able to operate at frequency up to 7.14 GHz at 1.5 V supply voltage. The high-speed operation is attributed to the adoption of the TSPC dynamic logic, and the all copper interconnect CMOS process which has much less interconnect parasitics than conventional aluminum technology. The design facilitates the implementation of a fully integrated RF CMOS phase-locked loop for applications in the 5.8 GHz ISM band such as wireless LAN.

  • 47. Li, S. G.
    et al.
    Kipnis, I.
    Ismail, Mohammed
    10-GHz CMOS quadrature LC-VCO for multirate optical applications2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 10, p. 1626-1634Article in journal (Refereed)
    Abstract [en]

    A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-mum CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI(pp) at 10 GHz and a phase poise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.

  • 48. Lindfors, S.
    et al.
    Halonen, K.
    Ismail, Mohammed
    A 2.7-V elliptical MOSFET-only C-gm-OTA filter2000In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 47, no 2, p. 89-95Article in journal (Refereed)
    Abstract [en]

    The g(m) C-operational transconductance amplifier (OTA) technique relaxes transconductor output swing and de-gain requirements; which makes it a suitable candidate for low-voltage circuits. To reduce the power consumption of OTA's, an excess phase-shift compensation with all automatic tuning circuit is used. A floating triode-region transconductor with a novel biasing to compensate the effect of channel-length modulation is presented. The two independent common-mode levels in a g(m) C-OTA integrator are utilized to bias a MOS as a linear capacitor. This enables the realization of the floating-transmission zero capacitors with a pure digital CMOS process. The implementation and the experimental results for a third-order 2.7-V all-MOS elliptical filter with 64-dB dynamic range and 0.1% linearity are presented.

  • 49.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Security and Privacy Issues in a GPS-enabled Mobile Application for Smart Traffic2010In: Proceedings of Smart Mobility Conference, 2010, 2010Conference paper (Refereed)
  • 50.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    MobiTraS: a mobile application for a Smart Traffic System2010In: Proceedings of the 8th IEEE International NEWCAS Conference, IEEE , 2010, p. 365-368Conference paper (Refereed)
    Abstract [en]

    Traffic monitoring systems deployed until now, use data collected mainly through fixed sensors. Advances on the modern mobile devices have made possible the development of S mart Traffic Systems, which use the traffic information g athered by the drivers' mobile devices to provide route guidance. Our work is focused on building a Real-Time Traffic Information System based mobile devices, which are used for both acquiring traffic information data and for providing feedback and guidance to drivers. This paper presents an analysis of the system, its security risks and requirements for dynamic route guidance together with possible solutions. A key component of the system is the mobile application that gathers data in an encrypted way and displays information to the users. The developed JavaME mobile application and its security/privacy features are also described.

123 1 - 50 of 117
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf