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  • 1.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mikulcak, Marcus
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Framework for Characterizing Predictable Platform Templates2014Report (Other academic)
    Abstract [en]

    The design of real-time multiprocessor systems is a very costly and time-consuming process due to the need for extensive verification efforts. Genericcorrect-by-construction system-level design flows, targeting predictable plat-forms, would help to tackle this problem. Unfortunately, because system-level design problems are formulated monolithically, existing methods areeither not powerful enough to perform efficient design space exploration,over-customized to a specific class of platforms, or do not allow to be ex-tended with new heuristics and solving methods, which makes their reusedifficult. We present a formal framework to explicitly capture and character-ize predictable platform templates that can be used to formulate a genericdesign flow for real-time streaming applications in a composable manner. Aproof-of-concept implementation of such a flow is performed and used to mapa JPEG encoder application onto an FPGA-based time-predictable platform.

  • 2. Diallo, P. I.
    et al.
    Attarzadeh-Niaki, Seyed Hosein
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Champeau, J.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    A formal, model-driven design flow for system simulation and multi-core implementation2015In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, IEEE , 2015, p. 254-263Conference paper (Refereed)
    Abstract [en]

    With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.

  • 3.
    Ezzeddine, Hussein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite2015In: NORCHIP 2014 - 32nd NORCHIP Conference: The Nordic Microelectronics Event, 2015Conference paper (Refereed)
    Abstract [en]

    Testing HW IP Blocks in multi-core environments is difficult. This paper presents a case study where a SINE/COSINE implementation using Pipelined Double-precision operations is implemented in one node, and results are sent through the NoC to a target node for inspection. The purpose of the experiments are two-fold, a) to study how debugging in a multi-core environment can be done and b) to examine why the original SINE/COSINE implementation is generating wrong results. During the experiments, several test-methods are applied to validate the implementations until the Floating Point implementation are generating correct values. After eliminating all faults in the operations, the SINE/COSINE function still generates some residual algorithmic errors, coming from the way the function was implemented. However, the experiments show that these errors can be eliminated with the help of some simple trigonometric rales.

  • 4.
    Mand, Nowshad Painda
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Artificial neural network emulation on NOC based multi-core FPGA platform2012In: NORCHIP, 2012, IEEE , 2012, p. 6403122-Conference paper (Refereed)
    Abstract [en]

    With the emergence of Multi-Core platforms, brain emulation in the form of Artificial Neural Nets has been announced as one of the important key research area. However, due to large non-linear growth of inter-neuron connectivity, direct mapping of ANNs to silicon structures is very difficult due to communication bottleneck.

  • 5. Paone, E.
    et al.
    Robino, Fransesco
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Palermo, G.
    Zaccaria, V.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Silvano, C.
    Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints2015In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE conference proceedings, 2015, p. 736-741Conference paper (Refereed)
    Abstract [en]

    When targeting an OpenCL application to platforms with multiple heterogeneous accelerators, task tuning and mapping have to cope with device-specific constraints. To address this problem, we present an innovative design flow for the customization and performance optimization of OpenCL applications on heterogeneous parallel platforms. It consists of two phases: 1) a tuning phase that optimizes each application kernel for a given platform and 2) a task-mapping phase that maximizes the overall application throughput by exploiting concurrency in the application task graph. The tuning phase is suitable for customizing parameterized OpenCL kernels considering device-specific constraints. Then, the mapping phase improves task-level parallelism for multi-device execution accounting for the overhead of memory transfers - overheads implied by multiple OpenCL contexts for different device vendors. Benefits of the proposed design flow have been assessed on a stereo-matching application targeting two commercial heterogeneous platforms.

  • 6.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA2014Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.

  • 7.
    Robino, Francesco
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    From Simulink to NoC-based MPSoC on FPGA2014In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, IEEE , 2014Conference paper (Refereed)
    Abstract [en]

    Network-on-chip (NoC) based multi-processor systems are promising candidates for future embedded system platforms. However, because of their complexity, new high level modeling techniques are needed to design, simulate and synthesize embedded systems targeting NoC-based MPSoC. Simulink is a popular modeling environment suitable to model at system level. However, there is no clear standard to synthesize Simulink models into SW and HW towards a NoC-based MPSoC implementation. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In this paper we present a novel design flow to synthesize Simulink models onto a NoC-based MPSoC running on low-cost FPGAs. Our design flow constrains the MPSoC and the Simulink model to share a common semantics domain. This permits to reduce the need of resource consuming SW components, reducing the memory requirements on the platform. At the same time, performances (throughput) of dataflow applications can increase when the number of processors of the target platform is increased. This is shown through a case study on FPGA.

  • 8.
    Robino, Francesco
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA2013In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, IEEE , 2013, p. 6581536-Conference paper (Refereed)
    Abstract [en]

    Future embedded systems will make use of many hundred, configurable or re-configurable, processing elements communicating through a network on chip (NoC), but there is lack of rapid automated design flows bridging the abstraction gap between the models of such systems and their implementation.

  • 9.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A NoC Generator for the Sea-of-Cores Era2011In: Proceedings of FPGAWorld 2011, 2011Conference paper (Refereed)
  • 10.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A NoC system generator for the Sea-of-Cores era2011In: 8th FPGAworld Conference - Academic Proceedings 2011, 2011, p. 35-40Conference paper (Refereed)
    Abstract [en]

    Multi-core systems are getting bigger. The number of cores is doubling every 18 months, in corollary with the reformulated Moore's law. Soon, the number of cores that can be integrated together in a system will be so large, that it is appropriate to talk about a new SoC design paradigm, the Sea-of-Cores era. This development will not end, even when CMOS cannot be made any smaller. Instead, with the development of Through-Silicon Vias (TSVs), chips will be stacked in 3D, promising continuous scaling for a very long time ahead. As systems grow, programming and debugging of them will become harder. Methods for generating the systems from higher-level specifications will be necessary to manage design complexity. Also, there will be so many processors to be programmed, that the SW also will have to be automatically generated and distributed, much in the same way as a synthesis and place & route tool is doing today for HW. In this paper, we present a NoC generator that can generate an arbitrarily large Multi-core platform from an XML configuration file, targeted for single-chip FPGA platforms. The NoC generator also generates a device driver prototype together with a small test program that can be used as a template for creating larger programs.

1 - 10 of 10
CiteExportLink to result list
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  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
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