Change search
Refine search result
1 - 10 of 10
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Gabry, Frédéric
    et al.
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Li, Nan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Schrammar, Nicolas
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Girnyk, Maksym
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Rasmussen, Lars K.
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Skoglund, Mikael
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    On the Optimization of the Secondary Transmitter's Strategy in Cognitive Radio Channels with Secrecy2014In: IEEE Journal on Selected Areas in Communications, ISSN 0733-8716, E-ISSN 1558-0008, Vol. 32, no 3, p. 451-463Article in journal (Refereed)
    Abstract [en]

    This paper investigates cooperation for secrecy in cognitive radio networks. In particular, we consider a four-node cognitive scenario where the secondary receiver is treated as a potential eavesdropper with respect to the primary transmission. The cognitive transmitter can help the primary transmission, and it should also ensure that the primary message is not leaked to the secondary user. We consider two cognitive scenarios depending on whether the secondary transmitter knows the primary message or not. In the first case, the secondary transmitter is unaware of the primary transmitter's message and acts as a helping interferer to enhance the secrecy of the primary transmission, whereas in the second case, relaying of the primary message is also within its capabilities. First, we find achievable rate regions for these two scenarios in the case of AWGN channels. We then investigate three different optimization problems: the maximization of the primary rate, the maximization of the secondary rate and the minimization of the secondary transmit power. For these optimization problems, we find closed-form expressions in important special cases. Furthermore, we analyze the cooperation between the primary and secondary transmitters from a game-theoretic perspective. We model their interaction as a Stackelberg game, for which we define and find the Stackelberg equilibrium. Finally, we use numerical examples to illustrate the rate regions, the three optimizations, and the impact of the Stackelberg game on the achievable rates and on the transmission strategies of the secondary transmitter.

  • 2.
    Li, Nan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Improvements in High-Coverage and Low-Power LBIST2015Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Testing cost is one of the major contributors to the manufacturing cost of integrated circuits. Logic Built-In Self Test (LBIST) offers test cost reduction in terms of using smaller and cheaper ATE, test data volume reduction due to on-chip test pattern generation, test time reduction due to at-speed test pattern application. However, it is difficult to reach a sufficient test coverage with affordable area overhead using LBIST. Also, excessive power dissipation during test due to the random nature of LBIST patterns causes yield-decreasing problems such as IR-drop and overheating.

    In this dissertation, we present techniques and algorithms addressing these problems.

    In order to increase test coverage of LBIST, we propose to use on-chip circuitry to store and generate the "top-off" deterministic test patterns. First, we study the synthesis of Registers with Non-Linear Update (RNLUs) as on-chip sequence generators. We present algorithms constructing RNLUs which generate completely and incompletely specified sequences. Then, we evaluate the effectiveness of RNLUs generating deterministic test patterns on-chip. Our experimental results show that we are able to achieve higher test coverage with less area overhead compared to test point insertion. Finally, we investigate the possibilities of integrating the presented on-chip deterministic test pattern generator with existing Design-For-Testability (DFT) techniques with a case study.

    The problem of excessive test power dissipation is addressed with a scan partitioning algorithm which reduces capture power for delay-fault LBIST. The traditional S-graph model for scan partitioning does not quantify the dependency between scan cells. We present an algorithm using a novel weighted S-graph model in which the weights are scan cell dependencies determined by signal probability analysis. Our experimental results show that, on average, the presented method reduces average capture power by 50% and peak capture power by 39% with less than 2% drop in the transition fault coverage. By comparing the proposed algorithm to the original scan partitioning, we show that the proposed method is able to achieve higher capture power reduction with less fault coverage drop.

  • 3.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    AIG Rewriting Using 5-Input Cuts2011In: Computer Design (ICCD), 2011 IEEE 29th International Conference on, IEEE conference proceedings, 2011, p. 429-430Conference paper (Refereed)
    Abstract [en]

    Rewriting is a common approach to logic optimization based on local transformations. Most commercially availablelogic synthesis tools include a rewriting engine that may be usedmultiple times on the same netlist during optimization. This paperpresents an And-Inverter graph (AIG) based rewriting algorithmusing 5-input cuts. The best circuits are pre-computed for a subsetof NPN classes of 5-variable functions. Cut enumeration andBoolean matching are used to identify replacement candidates.The presented approach is expected to complement existingrewriting approaches which are usually based on 4-input cuts.The experimental results show that, by adding the new rewritingalgorithm to ABC synthesis tool, we can further reduce the areaof heavily optimized large circuits by 5.57% on average.

  • 4.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An Algorithm for Constructing a Minimal Register with Non-Linear Update Generating a Given Sequence2014In: Proceedings of 2014 IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL), 2014, p. 254-259Conference paper (Refereed)
    Abstract [en]

    Registers with Non-Linear Update (RNLUs) are a generalization of Non-Linear Feedback Shift Registers (NLFSRs) in which both, feedback and feedforward, connections are allowed and no chain connection between the stages is required. An RNLU can be used to generate any given 2p-ary sequence, p ≥ 1. In this paper, a new algorithm for constructing RNLUs is presented. Expected size of RNLUs constructed by the presented algorithm is proved to be asymptotically smaller than the expected size of RNLUs constructed by previous algorithms generating the same sequence. The presented algorithm can potentially be useful for applications such as testing, wireless communications, and cryptography.

  • 5.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Area-efficient high-coverage LBIST2014In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 38, no 5, p. 368-374Article in journal (Refereed)
    Abstract [en]

    Logic Built-In Self Test (LBIST) is a popular technique for applications requiring in-field testing of digital circuits. LBIST incorporates test generation and response-capture on-chip. It requires no interaction with a large, expensive tester. LBIST offers test time reduction due to at-speed test pattern application, makes possible test data re-usability at many levels, and enables test-ready IP. However, the traditional pseudo-random pattern-based LBIST often has a low test coverage. This paper presents a new method for on-chip generation of deterministic test patterns based on registers with non-linear update. Our experimental results on 7 real designs show that the presented approach can achieve a higher stuck-at coverage than the test point insertion with less area overhead. We also show that registers with non-linear update are asymptotically smaller than memories required to store the same test patterns in a compressed form.

  • 6.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    On-Chip Area-Efficient Binary Sequence Storage2013In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2013, p. 325-326Conference paper (Refereed)
    Abstract [en]

    On-chip storage of binary sequences normally require the use ofRead-Only Memories (ROMs). However, ROMs do not exploit ofthe fact that the stored information is accessed sequentially. Thispaper presents an area-efficient sequence storage technique basedon state machines. Experimental results show that the presentedmethod significantly outperforms previous approaches. The resultingstate machines are on average 54% smaller than ROMs storingthe same sequence.

  • 7.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Synthesis of Power- and Area-Efficient Binary Machines for Incompletely Specified Sequences2014In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2014, p. 634-639Conference paper (Refereed)
    Abstract [en]

    Binary Machines (BMs) are a generalization of Linear Feedback Shift Registers (LFSRs) in which a current state is a nonlinear function of the previous state. It is known how to construct a BM generating a given completely specified binary sequence. In this paper, we present an algorithm which can efficiently handle the case of incompletely specified sequences. Our experimental results show that it significantly outperforms the approaches based on all-0 or random fill in both area and power dissipation. On average, it reduces dynamic power dissipation twice compared to all-0 fill approach and 6 times compared to random fill approach. The presented algorithm can potentially be useful for many applications, including Logic Built-In Self Test (LBIST).

  • 8.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Carlsson, Gunnar
    Development Unit Radio, Ericsson AB, Sweden.
    A Scan Partitioning Algorithm for Reducing Capture Power of Delay-Fault LBIST2015In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), 2015, 2015, p. 842-847Conference paper (Refereed)
  • 9.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Carlsson, Gunnar
    Development Unit Radio, Ericsson AB, Sweden.
    Evaluation of Alternative LBIST Flows: A Case Study2014In: Proceedings of 32nd Nordic Microelectronics Conference (NORCHIP'2014), 2014Conference paper (Refereed)
    Abstract [en]

    The cost of manufacturing test has been growing dramatically over the years. The traditional pseudo-random pattern based Logic Built-in Self Test (LBIST) can potentially reduce the test cost by minimizing the need for the automatic test equipment. However, LBIST test coverage can be unaccept-ably low for some designs. Various methods for complementing pseudo-random patterns to increase test coverage exist, but the combined effect of these methods has not been studied. In this paper, we evaluate the effectiveness of alternative LBIST flows by a case study on a real industrial design. Our results can guide the selection of the best LBIST flow for a given set of design constraints such as test coverage, area overhead, and test time.

  • 10.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sharif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Secure Key Storage Using State Machines2013In: 2013 IEEE 43rd International Symposium On Multiple-Valued Logic (ISMVL 2013), IEEE Computer Society, 2013, p. 290-295Conference paper (Refereed)
    Abstract [en]

    In hardware implementations of cryptographic systems, secret keys are commonly stored in an on-chip memory. This makes them prone to physical attacks, since the location of a memory on a chip in usually easy to spot. We propose to encode secret keys using a state machine which can be concealed in the rest of the logic on a chip. We present an heuristic algorithm which constructs a minimal state machine for a given set of secret keys. We show that, by using m-ary encoding, we are able to construct state machines which are smaller than the ones constructed using binary encoding. The presented algorithm is feasible for storing up to 1Mbits of random data.

1 - 10 of 10
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf