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  • 1. Buchholt, K.
    et al.
    Eklund, P.
    Jensen, J.
    Lu, J.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Behan, G.
    Zhang, H.
    Spetz, A. Lloyd
    Hultman, L.
    Growth and characterization of epitaxial Ti3GeC2 thin films on 4H-SiC(0001)2012In: Journal of Crystal Growth, ISSN 0022-0248, E-ISSN 1873-5002, Vol. 343, no 1, p. 133-137Article in journal (Refereed)
    Abstract [en]

    Epitaxial Ti3GeC2 thin films were deposited on 4 degrees off-cut 4H-SiC(0001) using magnetron sputtering from high purity Ti, C, and Ge targets. Scanning electron microscopy and helium ion microscopy show that the Ti3GeC2 films grow by lateral step-flow with {11 (2) over bar0} faceting on the SiC surface. Using elastic recoil detection analysis, atomic force microscopy, and X-Ray diffraction the films were found to be substoichiometric in Ge with the presence of small Ge particles at the surface of the film.

  • 2. Buchholt, Kristina
    et al.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, J.
    Eklund, Per
    Hultman, Lars
    Lloyd Spetz, Anita
    Ohmic contact properties of magnetron sputtered Ti3SiC2 on n- and p-type 4H-silicon carbide2011In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 98, no 4, p. 042108-Article in journal (Refereed)
    Abstract [en]

    Epitaxial Ti3SiC2 (0001) thin film contacts were grown on doped 4H-SiC (0001) using magnetron sputtering in an ultra high vacuum system. The specific contact resistance was investigated using linear transmission line measurements. Rapid thermal annealing at 950 degrees C for 1 min of as-deposited films yielded ohmic contacts to n-type SiC with contact resistances in the order of 10(-4) Omega cm(2). Transmission electron microscopy shows that the interface between Ti3SiC2 and n-type SiC is atomically sharp with evidence of interfacial ordering after annealing. (c) 2011 American Institute of Physics.

  • 3.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Current Gain Degradation in 4H-SiC Power BJTs2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 702-705Article in journal (Refereed)
    Abstract [en]

    SiC airs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.

  • 4.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 10, p. 2664-2670Article in journal (Refereed)
    Abstract [en]

    The influence of the emitter-base geometry on the current gain has been investigated by means of measurements and simulations. Particular attention has been placed on the emitter width and on the distance between the emitter edge and the base contact. When the emitter width is decreased from 40 to 8 mu m, the current gain is reduced by 20%, whereas when the distance between the base contact and the emitter edge is decreased from 5 to 2 mu m, the current gain is reduced by 10%. Simulations have been used to investigate the reasons for the current gain reduction. The reduction of the emitter width induces two mechanisms of current gain reduction: earlier forward biasing of the base-collector junction and higher recombination in the emitter region. Both mechanisms result from the higher current density flowing under the emitter region. Placing the base contact very close to the emitter edge increases the base current by increasing the gradient of the electron concentration toward the base contact. The effect of increasing the base doping in the extrinsic region has been simulated, and the results demonstrate that the current gain can be improved if a high doping concentration in the range of 5 x 10(18) cm(-3) is used.

  • 5.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 3, p. 704-711Article in journal (Refereed)
    Abstract [en]

    Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10(-15) cm(2), and a trap concentration of 2 x 10(12) cm(-2). Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base ( which has a doping concentration of 3 x 10(17) cm(-3)) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.

  • 6.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Temperature Modeling and Characterization of the Current Gain in 4H-SiC Power BJTs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, p. 1061-1064Article in journal (Refereed)
    Abstract [en]

    The current gain of 4H-SiC BJTs has been modeled using interface traps between SIC and SiO2 to describe surface recombination, by a positive temperature dependence of the carrier lifetime in the base region and by bandgap narrowing in the emitter region. The interface traps have been modeled by one single level at 1 eV above the valence band, with capture cross section of 1 x 10(-15) cm(2) and concentration of 2 x 10(12) cm(-2). The temperature behavior of SiC BJTs has been simulated and the results have been compared with measurements. An analysis of the carrier concentration has been performed in order to describe the mechanisms for fall-off of the current gain at high collector current. At room temperature high injection in the base and forward biasing of the base-collector junction occur simultaneously causing an abrupt drop of the current gain. At higher temperatures high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the only acting mechanism for the current gain fall-off at high collector current. This mechanism and the negative temperature dependence of the carrier mobility can also explain the reduction of the knee current for gain fall-off with increasing temperature. Simulations with different emitter widths have been also performed and analyzed to characterize the emitter size effect. Higher current density caused by reducing the emitter width introduces higher carrier recombination in the emitter region, leading to a reduction of the current gain.

  • 7.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 2081-2087Article in journal (Refereed)
    Abstract [en]

    The ON-resistance of silicon carbide bipolar transistors is characterized and simulated. Output characteristics are compared at different base currents and different temperatures in order to validate the physical model parameters. A good agreement is obtained, and the key factors, which limit the improvement of R-ON, are identified. Surface recombination and material quality play an important role in improving device performances, but the device design is also crucial. Based on simulation results, a design that can enhance the conductivity modulation in the lowly doped drift region is proposed. By increasing the base doping in the extrinsic region, it is possible to meet the requirements of having low voltage drop, high current density, and satisfactory forced current gain. According to simulation results, if the doping is 5 x 10(18) cm(-3), it is possible to conduct 200 A/cm(2) at V-CE = 1 V by having a forced current gain of about 8, which represents a large improvement, compared with the simulated value of only one in the standard design.

  • 8.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Investigation of Current Gain Degradation in 4H-SiC Power BJTs2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1131-1134Article in journal (Refereed)
    Abstract [en]

    The current gain degradation of 4H-SiC BJTs with no significant drift of the on-resistance is investigated. Electrical stress on devices with different emitter widths suggests that the device design can influence the degradation behavior. Analysis of the base current extrapolated from the Gummel plot indicates that the reduction of the carrier lifetime in the base region could be the cause for the degradation of the gain. However, analysis of the base current of the base-emitter diode shows that the degradation of the passivation layer could also influence the reduction of the current gain.

  • 9.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors2011Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The superior characteristics of Silicon Carbide as a wide band gap semiconductor have motivated many industrial and non-industrial research groups to consider SiC for the next generations of high power semiconductor devices. The SiC Bipolar Junction Transistor (BJT) is one candidate for high power applications due to its low on-state power loss and fast switching capability. However, to compete with other switching devices such as Field Effect Transistors (FETs) or IGBTs, it is necessary for a power SiC BJT to provide a high current gain to reduce the power required from the drive circuit. In this thesis implantation free 4H-SiC BJTs with linearly graded base layer have been demonstrated with common-emitter current gain of 50 and open-base breakdown voltage of 2700 V. Also an efficient junction termination extension (JTE) with 80% of theoretical parallel-plane breakdown voltage was analyzed by fabrication of high voltage PiN diodes to achieve an optimum dose of remaining JTE charge. Surface passivation of 4H-SiC BJT is an essential factor for efficient power BJTs. Therefore different passivation techniques were compared and showed that around 60% higher maximum current gain can be achieved by a newsurface passivation layer with low interface trap density that consists of PECVD oxide followed by post-deposition oxide anneal in N2O ambient. This surface passivation along with doublezone JTE were used for fabrication of high power BJTs that result in successful demonstration of 2800 V breakdown voltage for small area (0.3 × 0.3 mm) and large area (1.8 × 1.8 mm) BJTs with a maximum dc current gain of 55 and 52, respectively. The small area BJT showed RON = 4mΩcm2, while for the large are BJT RON = 6.8 mΩcm2. Finally, a Darlington transistor with a maximum current gain of 2900 at room temperature and 640 at 200 °C is reported. The high current gain of the Darlington transistor is achieved by optimum design for the ratio of the active area of the driver BJT to the output BJT.

  • 10.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, Romain
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schöner, Adolf
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Han, Jisheng
    Dimitrijev, Sima
    Reshanov, Sergey A.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Surface-passivation effects on the performance of 4H-SiC BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, p. 259-265Article in journal (Refereed)
    Abstract [en]

    In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

  • 11.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 11, p. 1170-1172Article in journal (Refereed)
    Abstract [en]

    Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of similar to 1.2 x 10(13) cm(-2) in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single-and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.

  • 12.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage, Low On-resistance 4H-SiC BJTs with Improved Junction Termination Extension2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 706-709Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC bipolar transistors with two-zone etched-JTE and improved surface passivation are fabricated. This design provides a stable open-base breakdown voltage of 2.8 kV which is about 75% of the parallel plane breakdown voltage. The small area devices shows a maximum dc current gain of 55 at Ic=0.33 A (J(C)=825 A/cm(2)) and V-CESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4 m Omega.cm(2). The large area device shows a maximum dc current gain of 52 at Ic = 9.36 A (J(C)=312 A/cm(2)) and V-CESAT = 1.14 V at Ic = 5 A that corresponds to an ON-resistance of 6.8 m Omega.cm(2). Also these devices demonstrate a negative temperature coefficient of the current gain (beta=26 at 200 degrees C) and positive temperature coefficient of the ON-resistance (R-ON = 10.2 m Omega.cm(2)).

  • 13.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High current-gain implantation-free 4H-SiC Monolithic Darlington Transistor2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 2, p. 188-190Article in journal (Refereed)
    Abstract [en]

    An implantation-free 4H-SiC Darlington transistor with high current gain of 2900 ( JC= \970A/cm2) and VCE) = 6V) at room temperature is reported. The device demonstrates a record maximum current gain of 640 at 200 hC, offering an attractive solution for high-temperature applications. The monolithic Darlington device exhibits an open-base breakdown voltage of 1 kV that is less than the optimum bulk breakdown due to isolation trench between the driver and the output bipolar junction transistor. On the same wafer, a monolithic Darlington pair with a nonisolated base layer was also fabricated. At room temperature, this device shows a maximum current gain of 1000 and an open-base breakdown voltage of 2.8 kV, which is 75% of the parallel-plane breakdown voltage

  • 14.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Shayestehaminzadeh, Seyedmohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of crystal orientation on the current gain in 4H-SiC BJTs2010In: Device Research Conference - Conference Digest, DRC, 2010, p. 131-132Conference paper (Refereed)
    Abstract [en]

    The 4H-SiC bipolar junction transistors (BJT) are considered as efficient high power switching devices due to the ability of obtaining very low specific on-resistance compared to FET based devices. However, one drawback with the present high voltage BJTs is the relatively low current gain. To reduce the power required by the drive circuit, it is important to increase the common-emitter current gain ( #x03B2;). 4H-SiC (0001) Si-face has become a favorable plane for vertical power BJTs with epitaxial layers that shows higher mobility along the c-axis and provides higher current gain. Furthermore, important progress on improving the current gain focused on the quality of surface passivation at the SiC/SiO2 interface has been reported during previous years. Higher quality of passivation can provide less interface traps and thereby minimizes the surface recombination current. Conventionally, vertical 4H-SiC BJTs are fabricated along the [11_00] direction on (0001) Si-face. However due to anisotropic properties of 4H-SiC, different orientations on Si-face can also affect the base current of the BJT through variation of mobility and interface traps density distribution along each direction. In this work, single-finger small area BJTs are fabricated on (0001) Si-face along [12_10], [011_0], [112_0] and [11_00] directions. This design can provide various orientations of BJTs that corresponds to an angular range between 0 to 180 degrees relative to conventional [11_00] direction. The goal was to find a correlation between different crystallographic orientation, mobility and interface traps density distribution through transistor characteristics and finally comparison with simulation. Fig.1 shows a cross section and top view of fabricated BJTs. The n+ emitter epi-layer is 1.35 #x03BC;m nitrogen doped to 6 #x00D7;1018 cm-3 and capped by 200-nm-thick 2 #x00D7;1019 cm-3 layer. The base epi-layer is 650 nm Al-d- - oped with concentration of 4.3 #x00D7;1017 cm-3. The drift n- epilayer is 20 #x03BC;m thick and doped to 6 #x00D7;1015 cm-3. Inductively coupled plasma (ICP) etching with an oxide mask was used to form emitter and base mesas. Fig.2 is a comparison of the maximum current gain with different orientations normalized to the maximum current gain along [11_00] before surface passivation and contact metallization. The results indicate that the maximum current gain is orientation-dependent and has a maximum for BJTs with the emitter edge aligned to the [112_0] direction. The variation effect of planar mobility and interface traps concentration on the current gain is simulated based on the previous work and is illustrated in Fig.3. The simulation shows that interface oxide charges has more influence on the current gain compared to the mobility and higher current gain is attributed to lower oxide interface charges. The orientation dependence of the transistor parameters such as maximum current gain after passivation and the base resistance will be evaluated and compared with simulation.

  • 15.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Shayestehaminzadeh, Seyedmohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Removal of Crystal Orientation Effects on the Current Gain of 4H-SiC BJTs Using Surface Passivation2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 5, p. 596-598Article in journal (Refereed)
    Abstract [en]

    In this letter, the dependence of current gain and base resistance on crystal orientations for single-finger 4H-SiC bipolar junction transistors ( BJTs) is analyzed. Statistical evaluation techniques were also applied to study the effect of surface passivation and mobility on the performance of the devices. It is shown that BJTs with an emitter edge aligned to the [1 (2) under bar 10] direction shows a lower current gain before surface passivation and higher base resistance after contact formation compared with other investigated crystal directions. However, the devices show a similar current gain independent of the crystal orientation after surface passivation.

  • 16.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, R.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schoner, A.
    Han, J.
    Dimitrijev, S.
    Reshanov, S. A.
    Zetterling, Carl -Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Experimental evaluation of different passivation layers on the performance of 3kV 4H-SiC BJTs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, no Part 1-2, p. 661-664Article in journal (Refereed)
    Abstract [en]

    In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 degrees C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.

  • 17.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage (2.8 kV) Implantation-free 4H-SiC BJTs with Long-TermStability of the Current Gain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 8, p. 2665-2669Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC BJTs with high breakdown of 2800 V have been fabricated utilizing acontrolled two-step etched junction termination extension (JTE). The small area devices show a maximum dc current gainof 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4mΩ·cm2. The large area device have a maximum dc current gain of 52 at Ic = 9.36 A (JC=289 A/cm2) and VCESAT = 1.14 Vat Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ·cm2. Also these devices demonstrate a negative temperaturecoefficient of the current gain (β=26 at 200°C) and a positive temperature coefficient of the ON-resistance (RON = 10.2mΩ·cm2 at 200°C). The small area BJT shows no bipolar degradation and low current gain degradation after 150 Hrs stressof the base-emitter diode with current level of 0.2A (JE=500 A/cm2). Also, large area BJT shows a VCE fall time of 18 nsduring turn-on and a VCE rise time of 10 ns during turn-off for 400 V switching characteristics.

  • 18.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lu, Jun
    Wise, R.
    Wejtmans, H.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    High boron incorporation in selective epitaxial growth of SiGe layers2007In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 18, no 7, p. 747-751Article in journal (Refereed)
    Abstract [en]

    Incorporation of high amount of boron in the range of 1 x 10(20)-1 x 10(21) cm(-3) in selective epitaxial growth (SEG) of Si1-xGex (x = 0.15-0.315) layers for recessed or elevated source/drain junctions in CMOS has been studied. The effect of high boron doping on growth rate, Ge content and appearance of defect in the epi-layers was investigated. In this study, integration issues were oriented towards having high layer quality whereas still high amount of boron is implemented and the selectivity of the epitaxy is preserved.

  • 19.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl - Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Implantation-Free Low on-resistance 4H-SiC BJTs with Common-Emitter Current Gain of 50 and High Blocking Capability2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 615-617, p. 833-836Article in journal (Refereed)
    Abstract [en]

    In this study, high voltage blocking (2.7 kV) implantation-free SiC Bipolar Junction Transistors with low on-state resistance (12 m Omega-cm(2)) and high common-emitter current gain of 50 have been fabricated. A graded base doping was implemented to provide a low resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high temperature dopant activation annealing and for avoiding generation of life-time killing defects that reduces the current gain. Also in this process large area transistors showed common-emitter current gain of 38 and open-base breakdown voltage of 2 kV.

  • 20.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of 2700-v 12-m Omega center dot cm(2) non ion-implanted 4H-SiC BJTs with common-emitter current gain of 502008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 10, p. 1135-1137Article in journal (Refereed)
    Abstract [en]

    High-voltage blocking (2.7-kV) implantation-free SiC bipolar junction transistors with low ON-state resistance (12 m Omega . cm(2)) and high common-emitter current gain of 50 have been fabricated. A graded-base doping was implemented to provide a low-resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high-temperature dopant activation annealing and for avoiding generation of lifetime-killing defects that reduce the current gain.

  • 21.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ostling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simultaneous study of nickel based ohmic contacts to Si-face and C-face of n-type silicon carbide2007In: 2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2, NEW YORK: IEEE , 2007, p. 311-311Conference paper (Refereed)
  • 22.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Backside Nickel Based Ohmic Contacts to n-type Silicon Carbide2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 600-603, p. 635-638Article in journal (Refereed)
    Abstract [en]

    This work focuses on Ni ohmic contacts to the C-face (backside) of n-type 4H-SiC substrates. Low-resistive ohmic contacts to the wafer backside are important especially for vertical power devices. Ni contacts were deposited using E-beam evaporation and annealed at different temperatures (700-1050 degrees C) in RTP to obtain optimum conditions for forming low resistive ohmic contacts. Our results indicate that 1 min annealing at temperatures between 950 and 1000 degrees C provides high quality ohmic contacts with a contact resistivity of 2.3x10(-5) Omega cm(2). Also our XRD results show that different Ni silicide phases appear in this annealing temperature range.

  • 23.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, R.
    Texas Instruments, Dallas.
    Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors2008In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 103, no 5, p. 054907-Article in journal (Other academic)
    Abstract [en]

    This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1-xGex (x=0.14-0.32) layers. It is shown with a comprehensive experimental study that the local Si coverage of individual chips on patterned wafers is the main parameter for the layer profile in the epitaxial growth. This was explained by the gas depletion of the growth species in the low velocity boundary layer over the wafer. The gas depletion radius around each oxide opening was in the centimeter range which is related to the boundary layer thickness. The results from these experiments were applied to grow Si0.75Ge0.25 layers with B concentration of 4x10(20) cm(-3) selectively for elevated source and drains in fully depleted ultrathin body silicon on insulator p metal oxide semiconductor field effect transistor (p-MOSFET) devices. The epitaxy control was maintained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing a uniform gas depletion over the chips on the wafer.

  • 24.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Maresca, Luca
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Khatibi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kinetic Model of SiGe Selective Epitaxial Growth Using RPCVD Technique2010In: Sige, Ge, And Related Compounds 4: Materials, Processing, And Devices / [ed] D. Harame, J. Boquet, M. Östling, Y. Yeo, G. Masini, M. Caymax, T. Krishnamohan, B. Tillack, S. Bedell, S. Miyazaki, A. Reznicek, S. Koester, Electrochemical Society, 2010, Vol. 33, p. 581-593Conference paper (Refereed)
    Abstract [en]

    Recently, selective epitaxial growth (SEG) of B-doped SiGe layers has been used in recessed source/drain (S/D) of pMOSFETs. The uniaxial induced strain enhances the carrier mobility in the channel. In this work, a detailed model for SEG of SiGe has been developed to predict the growth rate and Ge content of layers in dichlorosilane(DCS)-based epitaxy using a reduced-pressure CVD reactor. The model considers each gas precursor contributions from the gas-phase and the surface. The gas flow and temperature distribution were simulated in the CVD reactor and the results were exerted as input parameters for Maxwell energy distribution. The diffusion of molecules from the gas boundaries was calculated by Fick's law and Langmuir isotherm theory (in non-equilibrium case) was applied to analyze the surface. The pattern dependency of the selective growth was also modeled through an interaction theory between different subdivisions of the chips. Overall, a good agreement between the kinetic model and the experimental data were obtained.

  • 25.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Maresca, Luca
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Khatibi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kinetic Model of SiGe Selective Epitaxial Growth Using RPCVD Technique2011In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 158, no 4, p. H457-H464Article in journal (Refereed)
    Abstract [en]

    Recently, selective epitaxial growth (SEG) of B-doped SiGe layers has been used in recessed source/drain (S/D) of pMOSFETs. The uniaxial induced strain enhances the carrier mobility in the channel. In this work, a detailed model for SEG of SiGe has been developed to predict the growth rate and Ge content of layers in dichlorosilane(DCS)-based epitaxy using a reduced-pressure CVD reactor. The model considers each gas precursor contributions from the gas-phase and the surface. The gas flow and temperature distribution were simulated in the CVD reactor and the results were exerted as input parameters for Maxwell energy distribution. The diffusion of molecules from the gas boundaries was calculated by Fick's law and Langmuir isotherm theory (in non-equilibrium case) was applied to analyze the surface. The pattern dependency of the selective growth was also modeled through an interaction theory between different subdivisions of the chips. Overall, a good agreement between the kinetic model and the experimental data were obtained.

  • 26.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    B-doped SIGE(C) materials for high performance devices2011In: Boron: Compounds, Production and Application / [ed] Gary L. Perkins, Nova Science Publishers, Inc., 2011, p. 295-326Chapter in book (Refereed)
    Abstract [en]

    B-doping of group IV materials using B2H6 is widely performed in chemical vapor deposition (CVD) technique. The B-doped SiGe layers are grown epitaxially as the base layer in HBTs for increased frequency performance in mixed signal radio frequency (RF) applications. These layers may also apply as a stressor material in source/drain of pMOSFETs for higher carrier mobility in a uniaxially strained channel. Furthermore, contact layers performance in terms of thermal stability and resistivity are improved by adopting highly boron doped (B-doped) layers in various electronic components. However, high diffusion of boron can limit the thermal budget for fabrication of the devices. One way to suppress this problem is integration of carbon in B-doped layers where the carbon diffuses out but boron stays in the SiGe layers. Therefore, growing highly B-doped group IV materials with high thermal stability and layer quality is a challenging issue. This chapter deals with growth kinetics, dopant incorporation, thermal stability, strain compensation, strain relaxation and defect formation of B-doped SiGe layers grown by reduced pressure CVD. The ion implantation and some of its processing issues regarding B-doping will be discussed.

  • 27.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bipolar Integrated OR-NOR Gate in 4H-SiC2011In: Proceedings of International Conference on Silicon Carbibe and Related Materials 2011, 2011Conference paper (Refereed)
  • 28.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Measurements and simulations of lateral PNP transistors in a SiC NPN BJT technology for high temperature integrated circuits2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 758-761Article in journal (Refereed)
    Abstract [en]

    In this work, a 4H-SiC lateral PNP transistor fabricated in a high voltage NPN technology has been simulated and characterized. The possibility of fabricating a lateral PNP with a current gain larger than 1 has been investigated. Device and circuit level solutions have been performed.

  • 29.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 4, p. 1076-1083Article in journal (Refereed)
    Abstract [en]

    Operation up to 300 degrees C of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter-coupled logic is demonstrated. Stable noise margins of about 1 V are reported for a two-input OR-NOR gate operated on - 15 V supply voltage from 27 degrees C up to 300 degrees C. In the same temperature range, an oscillation frequency of about 2 MHz is also reported for a three-stage ring oscillator.

  • 30.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bipolar integrated OR-NOR gate in 4H-SiC2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1257-1260Article in journal (Refereed)
    Abstract [en]

    An integrated bipolar OR-NOR gate based on emitter coupled logic (ECL) is demonstrated in 4H-SiC. Operated from 27 up to 300 °C on -15 V supply voltage the logic gate exhibits stable noise margins (NMs) of about 1 V in the entire temperature range, and high and low output voltage levels that move towards positive voltages when the temperature increases: from -3 up to -2.7 V and from -5.4 up to -5.1 V respectively. In the same temperature range transistor current gain (β) goes from 46 down to 21.

  • 31.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 8, p. 1894-1898Article in journal (Refereed)
    Abstract [en]

    This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 x 1.8 nun (with an active area of 3.24 mm') showed a common emitter current gain 0 of 42, specific on-resistance Rsp ON of 9 mQ - em', and open-base breakdown voltage BVcEO of-1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the p+ regrown layer from the surface of the emitter-base junction. The BJT with p+ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs; with only etched flat-surface JTE.

  • 32.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Allerstam, F.
    Sveinbjörnsson, E. Ö.
    1200 V 4H-SiC BJTs with a Common Emitter Current Gain of 60 and Low On-resistance2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 600-603, p. 1151-1154Article in journal (Refereed)
    Abstract [en]

    This paper reports a 4H-SiC bipolar junction transistor (BJT) with a breakdown voltage (BVCEO) of 1200 V, a maximum current gain (beta) of 60 and the low on-resistance (Rsp-on)of 5.2 m Omega cm(2). The high gain is attributed to an improved surface passivation SiO2 layer which was grown in N2O ambient in a diffusion furnace. The SiC BJTs with passivation oxide grown in N2O ambient show less emitter size dependence than reference SiC BJTs, with conventional SiO2 passivation, due to a reduced surface recombination current. SiC BJT devices with an active area of 1.8 mm x 1.8 mm showed a current gain of 53 in pulsed mode and a forward voltage drop Of V-CE=2V at I-C=15 A (J(C)=460 A/cm(2)).

  • 33.
    Radamson, Henry H.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High strain amount in recessed junctions induced by selectively deposited boron-doped SiGe layers2008In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 154, p. 106-109Article in journal (Refereed)
    Abstract [en]

    This work presents the selective epitaxial growth (SEG) of Si1-xGex (x=0.15-0.315) layers with high amount of boron (1 x 10(20)-1 x 10(21) cm(-3)) in recessed or unprocessed (elevated) openings for source/drain applications in CMOS has been Studied. The influence of the growth rate and strain on boron incorporation has been studied. A focus has been made on the strain distribution and boron incorporation in SEG of SiGe layers.

  • 34.
    Usman, Muhammad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hallen, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effect of 3.0 MeV helium implantation on electrical characteristics of 4H-SiC BJTs2010In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T140, p. 014012-Article in journal (Refereed)
    Abstract [en]

    Degradation of 4H-SiC power bipolar junction transistors (BJTs) under the influence of a high-energy helium ion beam was studied. Epitaxially grown npn BJTs were implanted with 3.0 MeV helium in the fluence range of 10(10)-10(11) cm(-2). The devices were characterized by their current-voltage (I-V) behaviour before and after the implantation, and the results showed a clear degradation of the output characteristics of the devices. Annealing these implanted devices increased the interface traps between passivation oxide and the semiconductor, resulting in an increase of base current in the low-voltage operation range.

  • 35.
    Zetterling, Carl-Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Future high temperature applications for SiC integrated circuits2011Conference paper (Refereed)
  • 36.
    Zetterling, Carl-Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Future high temperature applications for SiC integrated circuits2012In: Physica Status Solidi. C, Current topics in solid state physics, ISSN 1610-1634, E-ISSN 1610-1642, Vol. 9, no 7, p. 1647-1650Article in journal (Refereed)
    Abstract [en]

    The main advantage of SiC is its high critical field for breakdown. This leads to much lower on-resistance for high voltage devices compared to silicon, but at a higher price that has to be offset by system gains. However, it is not straightforward to exploit this advantage, which is clear from the many different device types that are presently being commercialized. There are other advantages of SiC yet to be fully investigated: the possibility of high temperature operating electronics and radiation hard devices. If integrated circuits in SiC are also available, the system advantage is larger. Here temperature ranges higher than that of SOI should be aimed at, and some of these new application areas will be described. An overview of IC research will be ended with a description of our selected technology operated at 300 °C.

  • 37.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zaring, Carina
    Konstantinov, A.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hallen, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SiC bipolar power transistors: Design and technology issues for ultimate performance2010In: 2010 MRS Spring Meeting, 2010, Vol. 1246, p. 175-186Conference paper (Refereed)
    Abstract [en]

    Silicon carbide (SiC) semiconductor devices for high power are becoming more mature and are now commercially available as discrete devices. Schottky diodes have been on the market since a few years but also bipolar junction transistors (BJTs), JFETs and MOSFETs are now reaching the market. The interest is rapidly growing for these devices in high power and high temperature applications. The BJTs have low conduction losses, fast switching capability, operate in normally-off mode, have high radiation hardness, and can handle high power density.

    This paper will review the current state of the art in active switching device performance with special emphasis on BJTs. Device performance has been demonstrated over a wide temperature interval. A very important feature in high power switch applications is the low on-resistance of a device. Better material quality and epi processes suppress the amount of basal plane dislocations to avoid stacking fault formation generated during high current injection. This has long been a concern for bipolar SiC devices but several research reports and long term reliability measurements of pn-junctions show that the bipolar degradation problem can be solved by a fine-tuned epitaxial technique. A discussion on surface passivation control is included. Finally, an example of a power switching module is given also demonstrating the excellent paralleling capability of BJTs.

  • 38.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B.Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SiC Bipolar Devices for High Power and Integrated Drivers2011In: Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2011 IEEE, IEEE conference proceedings, 2011, , p. 4p. 227-234Conference paper (Refereed)
    Abstract [en]

    Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. The first SiC device to reach the market was the unipolar Schottky diode. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now being offered in the voltage range up to 1.2 kV. SiC material quality and epitaxy processes have greatly improved and degradation free 100 mm wafers are readily available, which has removed one obstacle for the introduction of bipolar devices. The SiC wafer roadmap looks very favorable as volume production takes off. Other advantages of SiC are the possibility of high temperature operation (>; 300 °C) and in radiation hard environments, which could offer considerable system advantages. Thanks to the mature SiC process technology, low-power integrated circuits are now also viable. Such circuits could find use in integrated drivers operating at elevated temperatures.

  • 39.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT).
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon carbide bipolar power devices2011In: ECS Transactions, 2011, no 8, p. 189-200Conference paper (Refereed)
    Abstract [en]

    This paper reviews the current state of the art in active switching device performance for SiC BJTs. In addition, some results from simulations are shown with particular attention on temperature and design dependence of the current gain. A design to improve conductivity modulation is also suggested. Finally, performance of a 2.8 kV BJT are illustrated. This device demonstrates high current gain of 52, low on-resistance of 6.8 mΩcm 2, fast switching, and no bipolar degradation.

  • 40.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SiC power devices - present status, applications and future perspective2011In: 2011 IEEE 23RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2011, p. 10-15Conference paper (Refereed)
    Abstract [en]

    Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. Recently Schottky diodes are offered by both USA and Europe based companies. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now available on the commercial market. The interest is rapidly growing for these devices in high power and high temperature applications. The main advantages of wide bandgap semiconductors are their very high critical electric field capability. From a power device perspective the high critical field strength can be used to design switching devices with much lower losses than conventional silicon based devices both for on-state losses and reduced switching losses. This paper reviews the current state of the art in active switching device performance for both SiC and GaN. SiC material quality and epitaxy processes have greatly improved and degradation free 100 mm wafers are readily available. The SiC wafer roadmap looks very favorable as volume production takes off. For GaN materials the main application area is geared towards the lower power rating level up to 1 kV on mostly lateral FET designs. Power module demonstrations are beginning to appear in scientific reports and real applications. A short review is therefore given. Other advantages of SiC is the possibility of high temperature operation (> 300 degrees C) and in radiation hard environments, which could offer considerable system advantages.

1 - 40 of 40
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