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  • 1. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    High throughput architecture for CLICHÉ network on chip2009In: Proceedings - IEEE International SOC Conference, SOCC 2009, 2009, p. 155-158Conference paper (Refereed)
    Abstract [en]

    High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.

  • 2. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. Ohio State University, Columbus, United States .
    High throughput architecture for high performance NoC2009In: ISCAS: 2009 IEEE International Symposium on Circuits and Systems, IEEE , 2009, p. 2241-2244Conference paper (Refereed)
    Abstract [en]

    High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

  • 3. Rashed, M.
    et al.
    Abd El Ghany, M. A.
    Ismail, Mohammed Y Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Power characteristics of Asynchronous Networks-on-Chip2011In: Int. Syst. Chip Conf., 2011, p. 160-165Conference paper (Refereed)
    Abstract [en]

    Power characteristics of different Asynchronous Network on Chip (NoC) architectures are developed. Among different NoC architectures, the Butterfly Fat Tree (BFT) dissipates the minimum power. With increasing the number of IP blocks, the relative power consumption of the interconnects and the associate repeaters of the Asynchronous NoC architecture decreases as compared to the power consumption of the network switches. The power dissipation of the Asynchronous architecture is decreased by up to 57% as compared to the power dissipation of the conventional Synchronous architecture. The BFT is more efficient with increasing the number of IP blocks.

  • 4.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Guest editorial: advanced design techniques for wireless communications2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 179-181Article in journal (Other academic)
  • 5. Wilson, J.
    et al.
    Ismail, Mohammed Y Ahmed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    RFIC design for first-pass silicon success2006In: Radio Des. Nanometer Technol., 2006, p. 287-314Conference paper (Refereed)
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