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  • 1.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Baubinas, R.
    Matukas, J.
    Palenskis, V.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Application of selective epitaxy for formation of ultra shallow SiGe-based junctions2004In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 114-115, no SPEC. ISS, p. 180-183Article in journal (Refereed)
    Abstract [en]

    Selective epitaxial growth (SEG) of B-, P- and As-doped Si1-xGex (0.12 < x < 0.26) layers on patterned substrates, aimed for source/drain ultra shallow junctions was investigated. The SiGe layers were deposited selectively on Si surface that is either unprocessed or previously in situ etched by HCl in the same run in a reduced pressure chemical vapor deposition reactor. In these investigations selectivity mode, pattern dependency (loading effect), defect generation and dopant incorporation in SiGe layers have been discussed. It was demonstrated that the growth rate increased in presence of B in SiGe while it decreased for P- and As-doped layers. The amount of Ge was constant for B-doped samples while it increased for As- and P-doped SiGe layers. The epitaxial quality was dependent on the Ge amount, growth rate and dopant concentration. The selectivity mode of the growth was dependent on B partial pressure, however, no effect was observed for P- or As-doping in SiGe layers. A resistivity value of similar to10(-3) Omega cm was obtained for B- and P-doped SiGe layers with optimized growth parameters.

  • 2.
    Isheden, Christian
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Source and drain engineering in SiGe-based pMOS transistors2005Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO2 and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-4 Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×1020 cm-3. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi0.8Ge0.2/Si0.8Ge0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10-8 Ωcm2 and 1.4x10-7 Ωcm2, respectively.

  • 3.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    MOSFETs with recessed SiGe Source/Drain junctions formed by selective etching and growth2004In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775, Vol. 7, no 4, p. G53-G55Article in journal (Refereed)
    Abstract [en]

    A source/drain extension process that uses HCl etching followed by selective growth of in situ B-doped SiGe is demonstrated. The two key process steps, etching and growth, are integrated by performing them consecutively in the same chemical vapor deposition reactor. The technique has the potential to solve end-of-the-roadmap requirements on junction depth, junction abruptness, and active doping concentration.

  • 4.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Selective Si etching using HCl vapor2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 107-109Article in journal (Refereed)
    Abstract [en]

    Selective Si etching using HCl in a reduced pressure chemical vapor deposition reactor in the temperature range 800-1000 degrees C is investigated. At 900 degrees C, the etch process is anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. This behavior indicates that the etch process is limited by surface reaction, since the etch rate in the directions with higher atomic concentration is lower. When the temperature is decreased to 800 degrees C, etch pits occur. A more isotropic etch is obtained at 1000 degrees C, however at this temperature the masking oxide is attacked and the etch surface is rough. Thus the temperature has to be confined to a narrow window to yield desirable properties under the present process conditions.

  • 5.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Process integration of a new method for formation of shallow junctions in MOSFET structures using recessed and selectively regrown Si1-xGex2004Conference paper (Refereed)
    Abstract [en]

    Process integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The proposed concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. Nitride residues and surface damage originating from RIE are shown to be detrimental for the epitaxial quality.

  • 6.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Recessed and epitaxially regrown SiGe(B) source/drain junctions with Ni salicide contacts2004In: Silicon Front-End Junction Formation-Physics And Technology / [ed] Pichler, P; Claverie, A; Lindsay, R; Orlowski, M; Windl, W, 2004, Vol. 810, p. 49-54Conference paper (Refereed)
    Abstract [en]

    Integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. When integrated in the PMOS process flow, the resulting Si1-xGex layer is very rough. Several possible causes for low quality epitaxy are discussed and improvements are proposed. It is suggested that the dopant type and/or concentration in the silicon substrate can have an effect on the process.

  • 7.
    Isheden, Christian
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    pMOSFETs with recessed and selectively regrown Si1-xGex source/drain junctions2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 1-3, p. 359-362Article in journal (Refereed)
    Abstract [en]

    A new source/drain formation concept based on selective Si etching followed by selective regrowth of in situ B-doped Si(1-x)Ge(x)is presented. Both process steps are performed in the same reactor to preserve the gate oxide. Well-behaved transistors are demonstrated with a negligibly low gate-to-substrate leakage current.

  • 8.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Formation of shallow junctions by HCl-based Si etch followed by selective epitaxy of B-doped Si1-xGex in RPCVD2004In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 151, no 6, p. C365-C368Article in journal (Refereed)
    Abstract [en]

    Formation of shallow source/drain junctions by using HCl-based Si etch followed by selective deposition of in situ heavily B-doped SiGe in a reduced pressure chemical vapor deposition reactor is presented. The etching parameters were optimized to obtain a smooth surface prior to deposition of the SiGe layers. In the epitaxy process, SiGe layers with a resistivity of 5 x 10(-4) Omega cm were obtained by tuning the partial pressure of the B and Ge precursors. A problem with selectivity in the epitaxy step was encountered when combing the etch and growth processes, but a practical solution is presented. Integration issues such as loading effect, pile-up, and defect generation have also been investigated.

  • 9.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Seger, Johan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Formation of Ni mono-germanosilicide on heavily B-doped epitaxial SiGe for ultra-shallow source/drain contacts2003In: Materials Research Society Symposium Proceedings, ISSN 0272-9172, E-ISSN 1946-4274, Vol. 745, p. 117-122Article in journal (Refereed)
    Abstract [en]

    The formation of Ni germanosilicides during solid-state interaction between Ni and heavily B-doped strained epitaxial Si1-xGex films with x=0.18, 0.32 and 0.37 is studied. No NiSi2 is found in these samples even after annealing at 850 degreesC, which can be compared to the formation of NiSi2 at 750 T on Si(I 00). Resistance and diffraction studies for the Si0.82Ge0.18 sample indicate that NiSi0.82Ge0.18 forms and the NiSi0.82Ge0.18/Si0.82Ge0.18 structure is stable from 400 to 700 degreesC. For the NiSi1-uGeu formed in all Si1-xGex samples, where u can be different from x, a strong film texturing is observed. When the Ge fraction is increased from 18 at.% to 32-37 at.%, the morphological stability of the film is degraded and a substantial increase in sheet resistance occurs already at 600 degreesC. The contact resistivity for the NiSi0.8Ge0.2/Si0.8Ge0.2 interface formed at 550 T is determined as 1.2x10(-7) Omegacm(2), which satisfies the ITRS contact resistivity requirement for the 70 nm technology node.

  • 10.
    Persson, Stefan
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Jarmar, Tobias
    Uppsala University, Ångström Laboratory, Materials Science.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lateral growth and three-dimensional effects in contacts between NiSi0.82Ge0.18 and p(+)-Si0.82Ge0.182005In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 489, no 1-2, p. 159-163Article in journal (Refereed)
    Abstract [en]

    Electrical contacts of NiSi0.82Ge0.18 to P+-Si0.82Ge0.18 were fabricated and characterised. Lateral growth of the NiSi0.82Ge0.18 under SiO2 isolation was observed. A three-dimensional model was employed to extract the contact resistivity by considering both the lateral growth and the presence of a recessed NiSi0.82Ge0.18 step into the Si0.82Ge0.18. The contact resistivity extracted was 5.0 x 10(-8) and 1.4 x 10(-7) Omega cm(2) for small contacts of circular geometry and large contacts of square shape, respectively. Possible causes responsible for this 3-fold difference in contact resistivity were discussed. An underestimate of the contact resistivity by 35% was found if a two-dimensional model was used without taking into account the complex interface morphology.

  • 11.
    Radamson, Henry
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Formation of shallow source/drain junctions in MOSFET structures by using Cl-based processes in reduced pressure CVD reactors2006In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T126, p. 97-100Article in journal (Refereed)
    Abstract [en]

    A novel process to form shallow junctions for source) drain application in CMOS structures is presented. The method consists of two steps; first an HCl-etch followed by SiCl2H2-based selective epitaxy in the same run in a reduced pressure chemical vapour deposition chamber. Optimization of etch and epitaxy processes have been investigated and the active dopant concentration in SiGe layers grown was measured directly in the device openings.

  • 12.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Seger, Johan
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Novel integration concepts for sige-based rf-MOSFETs2005In: Proc. Electrochem. Soc., 2005, p. 270-284Conference paper (Refereed)
    Abstract [en]

    An overview of critical integration issues for future generation rf-MOSFETs is presented. The process requirements and implementation of selective epitaxy for the source and drain regions is given. In-situ doping of highly boron doped recessed SiGe S/D is demonstrated. Channel region engineering is discussed and 50 nm strained SiGe pMOSFETs are demonstrated. Implementation of high-κ gate dielectrics is presented and device performance is demonstrated for surface channel MOSFETs with a gate stack based on ALD-formed HfO2/Al 2O3. Low frequency noise properties for those devices are analyzed. Contact metallization issues are critical for ultra scaled devices and here the implementation of NiSi on SiGe(C) regions as well as on ultra thin body SOI MOSFETs are presented. Finally, a spacer pattering technology using optical lithography to fabricate sub-50 nm high-frequency MOSFETs is demonstrated.

1 - 12 of 12
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