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  • 1.
    Lu, Zhonghai
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Thid, Rikard
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Millberg, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Nilsson, Erland
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    NNSE: Nostrum Network-on-Chip Simulation Environment2005In: Proceedings of Swedish System-on-Chip Conference, Stockholm, Sweden, April 2005., 2005Conference paper (Other academic)
    Abstract [en]

    A main challenge for Network-on-Chip (NoC) design isto select a network architecture that suits a particular application.NNSE enables to analyze the performance impactof NoC configuration parameters. It allows one to(1) configure a network with respect to topology, flow controland routing algorithm etc.; (2) configure various regularand application specific traffic patterns; (3) evaluatethe network with the traffic patterns in terms of latency and throughput.

  • 2.
    Millberg, Mikael
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nilsson, Erland
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Thid, Rikard
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip2004In: Design, Automation And Test In Europe Conference And Exhibition, Vols 1 And 2, Proceedings / [ed] Gielen G, Figueras J, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, p. 890-895Conference paper (Refereed)
    Abstract [en]

    In today's emerging Network-on-Chips, there is a need for different traffic classes with different Quality-of-Service guarantees. Within our NoC architecture Nostrum, we have implemented a service of Guaranteed Bandwidth (GB), and latency, in addition to the already existing service of Best-Effort (BE) packet delivery. The guaranteed bandwidth is accessed via Virtual Circuits (VC). The vcs are implemented using a combination of two concepts that we call 'Looped Containers' and 'Temporally Disjoint Networks'. The Looped Containers are used to guarantee access to the network - independently of the current network load without dropping packets; and the TDNS are used in order to achieve several VCs, plus ordinary BE traffic, in the network. The TDNS are a consequence of the deflective routing policy used, and gives rise to an explicit time-division-multiplexing within the network. To prove our concept an HDL implementation has been synthesised and simulated. The cost in terms of additional hardware needed, as well as additional bandwidth is very low - less than 2 percent in both cases! Simulations showed that ordinary BE traffic is practically unaffected by the VCs.

  • 3.
    Millberg, Mikael
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nilsson, Erland
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Thid, Rikard
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kumar, S.
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    The Nostrum Backbone: a Communication Protocol Stack for Networks Chip2004In: 17th International Conference On Vlsi Design, Proceedings - Design Methodologies For The Gigascale Era, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, p. 693-696Conference paper (Refereed)
    Abstract [en]

    We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for describing the individual layers' interfaces and service definitions of the layers in the protocol stack is suggested,and used. The concept includes support for best effort traffic packet delivery as well as support for guaranteed bandwidth traffic, using virtual circuits. Furthermore an application to NoC adapter is defined, as part of the Resource to Network Interface, and is used to communicate between the Nostrum protocol stack and the application. An industrial example has been implemented, simulated, and the results justifies the suggested layered approach.

  • 4.
    Nilsson, Erland
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Experiments of the Proximity Congestion Awareness with the Nostrum Backbone2003In: Proceedings of the Swedish System-on-Chip Conference (SSoCC), April 2003, 2003Conference paper (Refereed)
  • 5.
    Nilsson, Erland
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip2006Licentiate thesis, comprehensive summary (Other scientific)
    Abstract [en]

    During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.

    Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.

    Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce

    the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in

    hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.

    This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways

    can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.

  • 6.
    Nilsson, Erland
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Millberg, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Öberg, Johnny
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Load Distribution with the Proximity Congestion Awareness in a Network on Chip2003In: Design, Automation And Test In Europe Conference And Exhibition, Proceedings , LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2003, p. 1126-1127Conference paper (Refereed)
    Abstract [en]

    In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch. In case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a Proximity Congestion Awareness, PCA, technique, where switches use load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20.

  • 7.
    Nilsson, Erland
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT).
    PANACEA- A case study on the PANACEA NoC- a Nostrum Network on Chip prototype2006Report (Other academic)
  • 8.
    Nilsson, Erland
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Öberg, Johnny
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Reducing Power and Latency in 2-D Mesh NoCs using Globally Pseudochronous Locally Synchronous Clocking2004In:  International Conference On Hardware/Software Codesign And System Synthesis   , New York, USA: ASSOC COMPUTING MACHINERY , 2004, p. 176-181Conference paper (Refereed)
    Abstract [en]

    One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem has been proposed over the years. For Networks-on-Chip (NoC), where computational Resources are organised in a 2-D mesh connected together through Switches in an on-chip interconnection network, another possibility exists: Globally Pseudochronous Locally Synchronous clock distribution.

    In this paper, we present a clocking scheme for NoCs that we call Globally Pseudochronous Locally Synchronous, in which we distribute a clock with a constant phase difference between he switches. As a consequence of the phase difference, some paths along the NoC switch network become faster than the others. We call these paths Data Motorways. By adapting the switching policy in the switches to prefer data to use the motorways, we show that the latency within the network is reduced with up to 40% compared to a synchronous reference case.

    The phase difference between the resources also makes the circuit more tolerant to clock skew. It also distributes the current peaks more evenly across the clock period, which lead to a reduction in peak power, which in turn further reduces the clock skew and the jitter in the clock network.

  • 9.
    Nilsson, Erland
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Trading off Power versus Latency using GPLS Clocking in 2D-Mesh NoCs2005In: Isscs 2005: International Symposium On Signals, Circuits And Systems, Vols 1 And 2, Proceedings , New York, USA: IEEE , 2005, p. 51-54Conference paper (Refereed)
    Abstract [en]

    To handle the design complexity when the number of transistors on-chip reaches one billion, new ways of organizing chips will be needed. One solution to this problem is to organize computational resources in a grid, where all communication between the resources are performed using an interconnection network. These networks are commonly referred to as Networks-on-Chip, or NoCs.

    This paper focus on the trade-off between power and latency while keeping the required interconnection bandwidth constant. The clock frequency can be lowered to reduce the power, with reduced bandwidth as a consequence, which in a synchronous system will increase the latency linearly. In a 2D-Mesh NoC structure, it is possible to choose the regions with different clock phase and arrange them in such ways that the latency from sender to receiver along certain paths is nearly constant, and the total average latency is reduced with 50%. The reduction can then be exploited to trade off latency vs. power; the GPLS solution consumes 50% or the power compared to the fully synchronous solution, at the same latency and constant throughput.

  • 10. Vitkovski, A.
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lauter, Robert
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Haukilahti, Raimo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Nilsson, Erland
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Low-power and error protection coding for network-on-chip traffic2008In: IET Computers and Digital Techniques, ISSN 1751-8601, Vol. 2, no 6, p. 483-492Article in journal (Refereed)
    Abstract [en]

    The power consumption of the network-on-chip communication backbone is explored and the effectiveness of low-power encoding and error protection techniques is analysed. For the switch under the study, a Nostrum defective routing switch, simulations and power analysis suggest that only a minor fraction of the power is dissipated in the logic blocks, whereas the major part is due to the interconnection wires. The authors have investigated a number of low-power and data protection mechanisms and studied their impact on power consumption of the whole network. The bus-invert encoding scheme and a limited set of Hamming data protection codes have been implemented on both data link and at the network layer. However, it turned out that all low-power data encoding schemes have little potential to decrease power consumption due to the significant overhead. On the other hand, error protection mechanisms have a significant potential to decrease power consumption because they allow to operate the network at a lower voltage. The authors' experiments show a 20% decrease of power consumption for a given error rate and for a given performance.

  • 11.
    Vitkovski, Arsenij
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Haukilahti, Raimo
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nilsson, Erland
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Low-power and error coding for network-on-chip traffic2004In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, NEW YORK: IEEE , 2004, p. 20-23Conference paper (Refereed)
    Abstract [en]

    The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus-invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay.

1 - 11 of 11
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