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  • 1. Abdi, Y.
    et al.
    Derakhshandeh, J.
    Hashemi, P.
    Mohajerzadeh, S.
    Karbassian, F.
    Nayeri, F.
    Arzi, E.
    Robertson, M. D.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Light-emitting nano-porous silicon structures fabricated using a plasma hydrogenation technique2005In: Materials Science and Engineering B: Solid-State Materials for Advanced Technology, ISSN 0921-5107, Vol. 124-125, no SUPPL., p. 483-487Article in journal (Refereed)
    Abstract [en]

    The preparation of porous silicon films by DC-plasma hydrogenation and subsequent annealing of amorphous silicon films on silicon and glass substrates is reported for the first time. The effects of varying plasma power and annealing temperatures have been investigated and characterized by scanning-electron microscopy, transmission-electron microscopy, and photoluminescence. A plasma density of about 5.5 W/m2 and hydrogenation-annealing temperatures of about 400 °C was found to be suitable for the formation of nano-crystalline silicon films with grain diameters of the order of 3-10 nm. The intensity and wavelength of the emitted visible light were found to depend on the hydrogenation and annealing conditions, and patterning of the silicon films using standard lithography allowed the creation of light-emitting patterns.

  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Moeen, Mahdi
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Cappetta, Carmine
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Sensitivity of the crystal quality of SiGe layers grown at low temperatures by trisilane and germane2016In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 613, p. 38-42Article in journal (Refereed)
    Abstract [en]

    This work investigates the crystal quality of SiGe layers grown at low temperatures using trisilane, and germane precursors. The crystal quality sensitivity was monitored for hydrogen chloride and/or minor oxygen amount during SiGe epitaxy or at the interface of SiGe/Si layers. The quality of the epi-layerswas examined by quantifying noise parameter, K-1/f obtained from the power spectral density vs. 1/f curves. The results indicate that while it is difficult to detect small defect densities in SiGe layers by physical material characterization, the noise measurement could reveal the effects of oxygen contamination as low as 0.16mPa inside and in the interface of the layers.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Noroozi, Mohammad
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Primetzhofer, Daniel
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry.H
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    GeSnSi CVD Epitaxy using Silane, Germane, Digermane, and Tin tetrachlorideArticle in journal (Refereed)
    Abstract [en]

    In this study, strain relaxed and compressive strained Ge1-x-ySnxSiy (0.015≤x≤0.15 and 0≤y≤0.15) layers were epitaxially grown on Si substrate in a chemical vapor deposition reactor at atmospheric pressure. Digermane (Ge2H6) and germane (GeH4) were used as Ge precursors and tin tetrachloride (SnCl4) was used as Sn precursor. The growth temperature was kept below 400ᵒC to suppress Sn out diffusion. The layers crystal quality and strain were characterized using XRD, high resolution reciprocal lattice mapping and transmission electron microscopy and the surface morphology was investigated by atomic force microscopy (AFM). Furthermore, the low temperature epitaxial growth up to 15% Si atoms incorporation in Ge0.94Sn0.06 was demonstrated by adding silane (SiH4) as Si precursor. Sn contents calculated from high resolution XRD patterns were confirmed by Rutherford backscattering spectroscopy which shows that Sn atoms are mostly positioned in substitutional sites. AFM analysis showed below 1nm surface roughness for both strained and strain relaxed GeSn layers which make the promising materials for photonics and electronics applications.

  • 4.
    Aggerstam, Thomas
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, Electrum Laboratory, ELAB.
    Lourdudoss, Sebastian
    KTH, School of Information and Communication Technology (ICT), Centres, Electrum Laboratory, ELAB.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Centres, Electrum Laboratory, ELAB.
    Sjödin, Mikael
    KTH, School of Information and Communication Technology (ICT), Centres, Electrum Laboratory, ELAB.
    Lorenzini, P.
    CNRS-CHREA.
    Look, D.C.
    Semiconductor Research Center, Wright State University.
    Investigation of the interface properties of MOVPE grown AlGaN/GaN high electron mobility transistor (HEMT) structures on sapphire2006In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 515, no 2, p. 705-707Article in journal (Refereed)
    Abstract [en]

    We have developed a virtual GaN substrate on sapphire based on a two-step growth method. By optimizing the growth scheme for the virtual substrate we have improved crystal quality and reduced interface roughness. Our Al0.22Ga0.78N/GaN HEMT structure grown on the optimized semi-insulating GaN virtual substrate, exhibits Hall mobilities as high as 1720 and 7350 cm(2)/Vs and sheet carrier concentrations of 8.4 x 1012 and 10.0 x 1012 cm(-2) at 300 K and 20 K, respectively The presence of good AlGaN/GaN interface quality and surface morphology is also substantiated by X-Ray reflectivity and Atomic Force Microscopy measurements. A simplified transport model is used to fit the experimental Hall mobility.

  • 5. Akbar, F.
    et al.
    Kolahdouz, M.
    Larimian, Sh.
    Radfar, B.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Graphene synthesis, characterization and its applications in nanophotonics, nanoelectronics, and nanosensing2015In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 26, no 7, p. 4347-4379Article in journal (Refereed)
    Abstract [en]

    In the last decade, as semiconductor industry was approaching the end of the exponential Moore's roadmap for device downscaling, the necessity of finding new candidate materials has forced many research groups to explore many different types of non-conventional materials. Among them, graphene, CNTs and organic conductors are the most successful alternatives. Finding a material with metallic properties combined with field effect characteristics on nanoscale level has been always a dream to continue the ever-shrinking road of the nanoelectronics. Due to its fantastic features such as high mobility, optical transparency, room temperature quantum Hall effect, mechanical stiffness, etc. the atomically thin carbon layer, graphene, has attracted the industry's attention not only in the micro-, nano-, and opto-electronics but also in biotechnology. This paper reviews the basics and previous works on graphene technology and its developments. Compatibility of this material with Si processing technology is its crucial characteristic for mass production. This study also reviews the physical and electrical properties of graphene as a building block for other carbon allotropes. Different growth methods and a wide range of graphene's applications will be discussed and compared. A brief comparison on the performance result of different types of devices has also been presented. Until now, the main focus of research has been on the background physics and its application in electronic devices. But, according to the recent works on its applications in photonics and optoelectronics, where it benefits from the combination of its unique optical and electronic properties, even without a bandgap, this material enables ultrawide-band tunability. Here in this article we review different applications and graphene's advantages and drawbacks will be mentioned to conclude at the end.

  • 6. Andersson, J. Y.
    et al.
    Ericsson, P.
    Radamson, H. H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wissmar, Stanley
    Kolahdouz, Mohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SiGe/Si quantum structures as a thermistor material for low cost IR microbolometer focal plane arrays2011In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 60, no 1, p. 100-104Article in journal (Refereed)
    Abstract [en]

    Uncooled microbolometer thermal infrared detector technology is presently revolutionizing the infrared technology field. Essential improvement of the cost/performance ratio would be achieved by microbolometer arrays with higher sensitivity, since this allows the use of simpler and less costly camera optics, which implies a lower cost of the complete IR camera. The sensitivity of the microbolometers depends critically on the signal-to-noise ratio of the integrated thermistor material, which is set by its temperature coefficient of resistance (TCR) and noise characteristics. In this work we have investigated the use of epitaxial silicon-germanium/silicon (SiGe/Si) quantum well (QW) structures as a thermistor material. Si0.68Ge0.32/Si QW structures typically give a TCR of 3.0%/K and low noise values. A calculation of the noise equivalent temperature NETD of a bolometer gives 25 mK using the following assumptions: f-number = 1, 30 Hz video frame rate for a 640 x 480 array, with a pixel size 25 x 25 mu m. Higher TCR values are foreseen for SiGe/Si quantum dot structures, and the noise is expected to be similar to the QW based structures.

  • 7. Andersson, J. Y.
    et al.
    Hoglund, L.
    Noharet, B.
    Wang, Q.
    Ericsson, P.
    Wissmar, Stanley
    Asplund, C.
    Malm, H.
    Martijn, H.
    Hammar, Mattias
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gustafsson, Oscar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, S.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Holtz, P. O.
    Quantum structure based infrared detector research and development within Acreo's centre of excellence IMAGIC2010In: Infrared physics & technology, ISSN 1350-4495, E-ISSN 1879-0275, Vol. 53, no 4, p. 227-230Article in journal (Refereed)
    Abstract [en]

    Acreo has a long tradition of working with quantum structure based infrared (IR) detectors and arrays. This includes QWIP (quantum well infrared photodetector), QDIP (quantum dot infrared photodetector), and InAs/GaInSb based photon detectors of different structure and composition. It also covers R&D on uncooled microbolometers. The integrated thermistor material of such detectors is advantageously based on quantum structures that are optimised for high temperature coefficient and low noise. Especially the SiGe material system is preferred due to the compatibility with silicon technology. The R&D work on IR detectors is a prominent part of Acreo's centre of excellence "IMAGIC" on imaging detectors and systems for non-visible wavelengths. IMAGIC is a collaboration between Acreo, several industry partners and universities like the Royal Institute of Technology (KTH) and Linkoping University. (C) 2010 Elsevier B.V. All rights reserved.

  • 8.
    Asadollahi, Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zabel, Thomas
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of strained Ge on insulator via room temperature wafer bonding2014In: 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014, IEEE Computer Society, 2014, p. 81-84Conference paper (Refereed)
    Abstract [en]

    This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si 0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).

  • 9.
    Asadollahi, Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zabel, Thomas
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Roupillard, Gabriel
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of relaxed germanium on insulator via room temperature wafer bonding2014In: ECS Transactions: Volume 64, Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, Electrochemical Society, 2014, no 6, p. 533-541Conference paper (Refereed)
    Abstract [en]

    We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

  • 10.
    Azarov, Alexander
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zamani, Atieh
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Vines, L.
    Kuznetsov, A. Yu.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Dopant incorporation in thin strained Si layers implanted with Sb2010In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 518, no 9, p. 2474-2477Article in journal (Refereed)
    Abstract [en]

    The effect of tensile strain on Sb incorporation in Si and its activation during post-implantation annealing has been Studied by a combination of Rutherford backscattering/channeling spectrometry, secondary ion mass spectrometry. X-ray diffraction and 4-point probe measurements Our results show that, for Sb implanted samples a tensile strain has an important role for dopant behavior Particularly, increasing the tensile strain in the Si layer from 0 to 0 8% leads to an enhancement of the fraction of incorporated Sb atoms in substitutional sites already during implantation from similar to 7 to 30% Furthermore, 0 8% strain in antimony doped Si gives similar to 20% reduction in the sheet resistance in comparison to the unstrained sample.

  • 11. Bennett, N. S.
    et al.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Beer, C. S.
    Smith, A. J.
    Gwilliam, R. M.
    Cowern, N. E. B.
    Sealy, B. J.
    Enhanced n-type dopant solubility in tensile-strained Si2008In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, p. 331-333Article in journal (Refereed)
    Abstract [en]

    The creation of highly conductive ultrashallow-doped regions in strained Si is a key requirement for future Si based devices. It is shown that in the presence of tensile strain, Sb becomes a contender to replace As in strain-engineered CMOS devices due to advantages in sheet resistance. While strain reduces resistance for both As and Sb; a result of enhanced electron mobility, the reduction is significantly larger for Sb due to an increase in donor activation. Differential Hall measurements suggest this is a consequence of a strain-induced Sb solubility enhancement following solid-phase epitaxial regrowth, increasing Sb solubility in Si to levels approaching 10(21) cm(-3). Experiments highlight the importance of maintaining substrate strain during thermal annealing to maintain this high Sb activation.

  • 12.
    Bentzen, Andreas
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Menon, Cyril
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Mechanisms of diffusion-enhanced thermal stability of Si/Si1-xGex/Si heterostructures grown by chemical vapor deposition2004In: Journal of Crystal Growth, ISSN 0022-0248, E-ISSN 1873-5002, Vol. 261, no 1, p. 22-29Article in journal (Refereed)
    Abstract [en]

    The thermal stability of doped Si/Si0.8Ge0.2/Si (n-p-n or p-n-p) structures grown by reduced pressure chemical vapor deposition has been studied in correlation with the dopant in- and out-diffusion, using high-resolution X-ray reciprocal lattice mapping and secondary ion mass spectrometry as the main characterization tools. Initially, by doping the strained Si0.8Ge0.2 layer with reasonable amounts of boron, phosphorus, or arsenic, the thermal stability of the structures is shown to be dramatically increased compared to intrinsic layers. Secondly, the results show that when the dopants are present only in the Si buffer and cap layers, intrinsic Si spacer layers are required to obtain a significant enhancement in the thermal stability. These spacers reduce the interfacial dopant concentration and act as barriers for direct injection of precipitates into the SiGe layers. Finally, p-n-p and n-p-n structures were studied showing a very good thermal stability, due to enhanced out-diffusion of dopants from the SiGe layer upon in-diffusion from the adjacent layers. By employing i-Si spacers, the boron out-diffusion in a n-p-n structure was reduced, giving rise to a degradation of the thermal stability of this structure.

  • 13. Christensen, J. S.
    et al.
    Kuznetsov, A. Yu.
    Gunnaes, A. E.
    Svensson, B. G.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Phosphorus diffusion in the presence of threading dislocations in strain relaxed SiGe films2006In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 9, no 4-5, p. 650-654Article in journal (Refereed)
    Abstract [en]

    We have studied phosphorus diffusion in strain relaxed Si1-xGex films (x = 0.1 and 0.2) by secondary ion mass spectrometry (SIMS). The relaxed films were grown with low-pressure chemical vapor deposition (LPCVD) on a Si substrate followed by a graded SiGe layer. Two sets of samples were prepared under different growth conditions, and by transmission electron microscopy (TEM) it was shown that these conditions resulted in one set of samples containing a high density of threading dislocations in the relaxed films, and one set with a low dislocation density. The SIMS profiles of the phosphorus distributions in the samples, after annealing in N-2-ambient in the temperature range of 700-950 degrees C, show that the phosphorus diffusion is significantly faster in the films with the high dislocation density. Furthermore, the data suggests that the fast diffusion is due to a higher mobility of the diffusing complex rather than an increase in the point defect concentration mediating the diffusion, a result which indicates that the threading dislocations may act as channels for the rapid dopant diffusion in SiGe.

  • 14. Christensen, JS
    et al.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kuznetsov, AY
    Svensson, BG
    Diffusion of phosphorus in relaxed Si1-xGex films and strained Si/Si1-xGex heterostructures2003In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 94, no 10, p. 6533-6540Article in journal (Refereed)
    Abstract [en]

    Phosphorus diffusion has been studied in relaxed Si1-xGex samples (x=0.11 and 0.19) and strained Si/Si1-xGex/Si heterostructures (x=0.08, 0.13, and 0.18). The diffusivity of P is found to increase with increasing Ge content, while the influence of compressive strain results in a decrease in diffusivity as compared to that in relaxed material. The effect of strain is found to be equivalent to an apparent activation energy of -13 eV per unit strain, where the negative sign indicates that the P diffusion is mediated by interstitials in Si1-xGex (x<0.20). This conclusion is also supported by an experiment utilizing injection of Si self-interstitials, which results in an enhanced P diffusion in strained Si1-xGex. Further, P is found to segregate into Si across Si/Si1-xGex interfaces and the segregation coefficient increases with increasing Ge concentration.

  • 15. Christensen, JS
    et al.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kuznetsov, AY
    Svensson, BG
    Phosphorus and boron diffusion in silicon under equilibrium conditions2003In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 82, no 14, p. 2254-2256Article in journal (Refereed)
    Abstract [en]

    The intrinsic diffusion of phosphorus and boron in high-purity epitaxial silicon films has been studied. Phosphorus diffusion in a wide temperature range (810 to 1100 degreesC) revealed diffusion coefficients with an Arrhenius behavior exhibiting an activation energy of 2.74+/-0.07 eV and a pre-exponential factor of (8+/-5)x10(-4) cm(2)/s. In the temperature range of 810 to 1050 degreesC, boron was found to diffuse with an activation energy of 3.12+/-0.04 eV and a pre-exponential factor of 0.06+/-0.02 cm(2)/s. These results differ from those of many previous studies, but this deviation may to a large extent be attributed to slow transients before equilibrium concentrations of point defects are established at temperatures below similar to1000 degreesC. Despite a similar diffusion mechanism mediated by Si self-interstitials, P exhibits a lower activation energy than B because of stronger bonding to the Si self-interstitial.

  • 16. Derakhshandeh, J.
    et al.
    Abdi, Y.
    Mohajerzadeh, S.
    Hosseinzadegan, H.
    Soleimani, E. A.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Fabrication of 100 nm gate length MOSFET's using a novel carbon nanotube-based nano-lithography2005In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 124, p. 354-358Article in journal (Refereed)
    Abstract [en]

    PECVD-grown carbon nanotubes on (100)silicon substrates have been studied and exploited for electron emission applications. After the growth of vertical CNT's [Y. Abdi, J. Koohsorkhi, J. Derakhshandeh, S. Mohajerzadeh, H. Hosseinzadegan, M.D. Robertson, C. Benet, EMRS Spring Meeting, Strasbourg, France, May 2005] the grown nanotubes are encapsulated by means of an insulating TiO(2) layer, leading to beam-shape emission of electrons from the cathode towards the opposite anode electrode. The electron emission occurs using an anode-cathode voltage of 100 V with ability of direct writing on a photo-resist-coated substrates. Straight lines with widths between 50 and 200 nm have been successfully drawn. This technique has been applied on P-type (100)silicon substrates for the formation of the gate of N-MOSFET devices. The successful realization of MOSFET devices indicates its usefulness for applications in nano-electronic devices. This device has inversion Cox exceeding 0.7 mu F/cm(2), drive current equal to 3 10 mu A/mu m.

  • 17.
    Di Benedetto, Luigi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Strain balance approach for optimized signal-to-noise ratio in SiGe quantum well bolometers2009In: ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, 2009, p. 101-104Conference paper (Refereed)
    Abstract [en]

    This work presents thermal and electrical characterization of SiGe/Si multi-quantum wells (MQWs) with different layer profiles in complete bolometer structures. The thermal property of the bolometers was studied by measuring thermal coefficient of resistivity (TCR) through I-V curves for five temperatures (25, 40, 55, 80 and 100°C) and for four different pixel areas. The results show a strong dependency of TCR on the Si/SiGe layer thickness and the presence of dopant impurity in the MQW. The noise measurements of MQWs were performed carefully by eliminating all external contributions and the noise spectroscopy provided the noise characteristic parameters. The results demonstrate that the noise depends on the geometric size of the MQW and it increases with decreasing of the pixel area. The investigations show the noise level in the bolometer structures is sensitive to any dopant segregation from the contact layers.

  • 18. Duan, Ningyuan
    et al.
    Luo, Jun
    Wang, Guilei
    Liu, Jinbiao
    Simoen, Eddy
    Mao, Shujuan
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wang, Xiaolei
    Li, Junfeng
    Wang, Wenwu
    Zhao, Chao
    Ye, Tianchun
    Reduction of NiGe/n- and p-Ge Specific Contact Resistivity by Enhanced Dopant Segregation in the Presence of Carbon During Nickel Germanidation2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4546-4549Article in journal (Refereed)
    Abstract [en]

    This brief explores the specific contact resistivity (rho(c)) of NiGe/n- and p-Ge contacts with and without carbon pregermanidation implantation. It is found that in the presence of carbon, not only the thermal stability of NiGe films is improved, but also the rho(c) of the NiGe/n- and p-Ge contacts is reduced remarkably due to enhanced phosphorus (P) and boron (B) dopant segregation (DS) at the NiGe/Ge interface after nickel germanidation. At 500 degrees C germanidation temperature, the.c values are reduced from 1.1 x 10(-4) Omega-cm(2) and 2.9 x 10(-5) Omega-cm(2) for NiGe/n- and p-Ge contacts without carbon to 7.3 x 10(-5) Omega-cm(2) and 1.4 x 10(-5) Omega-cm(2) for their counterparts with carbon, respectively.

  • 19. Ebrahimi, P.
    et al.
    Kolahdouz, M.
    Iraj, M.
    Ganjian, M.
    Aghababa, H.
    Asl-Soleimani, E.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Systematic Optimization of Boron Diffusion for Solar Cell Emitters2017In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 46, no 7, p. 4236-4241Article in journal (Refereed)
    Abstract [en]

    To achieve p-n junctions for n-type solar cells, we have studied BBr3 diffusion in an open tube furnace, varying parameters of the BBr3 diffusion process such as temperature, gas flows, and duration of individual process steps, i.e., predeposition and drive-in. Then, output parameters such as carrier lifetime, sheet resistance, and diffusion profile were measured and statistically analyzed to optimize the emitter characteristics. Statistical analysis (factorial design) was finally employed to systematically explore the effects of the set of input variables on the outputs. The effect of the interactions between inputs was also evaluated for each output, quantified using a two-level factorial method. Temperature and BBr3 flow were found to have the most significant effect on different outputs such as carrier lifetime, junction depth, sheet resistance, and final surface concentration.

  • 20.
    Erdal, Suvar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Haralson, Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    High frequency performance of SiGeCHBTs with selectively & non-selectively grown collector2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 138-141Article in journal (Refereed)
    Abstract [en]

    Two high-frequency heterojunction bipolar transistor (HBT) architectures based on SiGeC have been fabricated and characterized. Different collector designs were applied either by using selective epitaxial growth doped with phosphorous or by non-selective epitaxial growth doped with arsenic. Both designs have a non-selectively deposited SiGeC base doped with boron and a poly-crystalline emitter doped with phosphorous. Both HBT designs exhibit similar electrical characteristics with a peak DC current gain of around 1600 and a BVCEO of 1.8V. The cut-off frequency (f(T)) and maximum frequency of oscillation (f(max)) vary from 40-80 GHz and 15-30 GHz, respectively, depending on lateral design relations. Good high frequency performance for a device with a selectively grown collector is demonstrated for the first time.

  • 21.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Belova, Lyubov M.
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching2012In: Advanced Functional Materials, ISSN 1616-301X, E-ISSN 1616-3028, Vol. 22, no 19, p. 4004-4008Article in journal (Refereed)
    Abstract [en]

    A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro- and nanostructures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The method is demonstrated by fabricating 3D structures made of two and three silicon layers, including suspended beams that are 40 nm thick, 500 nm wide, and 4 μm long, and patterned lines that are 33 nm wide.

  • 22.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Belova, Lyubov M.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, M.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rikers, Y. G. M.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Layer-by-layer 3D printing of Si micro- and nanostructures by Si deposition, ion implantation and selective Si etching2012In: 12th IEEE Conference on Nanotechnology (IEEE-NANO), 2012, IEEE conference proceedings, 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper we report a method for layer-by-layer printing of three-dimensional (3D) silicon (Si) micro- and nanostructures. This fabrication method is based on a sequence of alternating steps of chemical vapor deposition of Si and local implantation of gallium (Ga+) ions by focused ion beam (FIB) writing. The defined 3D structures are formed in a final step by selectively wet etching the non-implanted Si in potassium hydroxide (KOH). We demonstrate the viability of the method by fabricating 2 and 3-layer 3D Si structures, including suspended beams and patterned lines with dimensions on the nm-scale.

  • 23. Ghandi, R.
    et al.
    Kolahdouz, M.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wise, R.
    Wejtmans, Hans
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Effect of strain, substrate surface and growth rate on B-doping in selectively grown SiGe layers2008In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, p. 334-336Article in journal (Refereed)
    Abstract [en]

    In this work, the role of strain and growth rate on boron incorporation in selective epitaxial growth (SEG) of B-doped Si1-xGex (x=0.15-0.25) layers in recessed or unprocessed (elevated) openings for source/drain applications in CMOS has been studied. A focus has been made on the strain distribution and B incorporation in SEG of SiGe layers.

  • 24.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lu, Jun
    Wise, R.
    Wejtmans, H.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    High boron incorporation in selective epitaxial growth of SiGe layers2007In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 18, no 7, p. 747-751Article in journal (Refereed)
    Abstract [en]

    Incorporation of high amount of boron in the range of 1 x 10(20)-1 x 10(21) cm(-3) in selective epitaxial growth (SEG) of Si1-xGex (x = 0.15-0.315) layers for recessed or elevated source/drain junctions in CMOS has been studied. The effect of high boron doping on growth rate, Ge content and appearance of defect in the epi-layers was investigated. In this study, integration issues were oriented towards having high layer quality whereas still high amount of boron is implemented and the selectivity of the epitaxy is preserved.

  • 25. Grahn, J. V.
    et al.
    Fosshaug, H.
    Jargelius, M.
    Jonsson, P.
    Linder, M.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Mohadjeri, B.
    Pejnefors, J.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sanden, M.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Landgren, Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A low-complexity 62-GHz f(T) SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 549-554Article in journal (Refereed)
    Abstract [en]

    A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor deposition at reduced pressure was used for low-temperature SiGe epitaxy. Following SiGe epitaxy, the process temperature budget was kept very low with 900 degrees C for 10 s as the highest temperature step. A very high current gain of almost 2000 and cut off frequency of 62 GHz were achieved for a uniform 12% Ge profile. The breakdown voltage BVCEO and forward Early voltage were equal to 2.9 and 6.5 V, respectively.

  • 26.
    Gylfason, Kristinn B.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Gunnar Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Belova, Lyubov M.
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Process considerations for layer-by-layer 3D patterning of silicon, using ion implantation, silicon deposition, and selective silicon etching2012In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 30, no 6, p. 06FF05-Article in journal (Refereed)
    Abstract [en]

    The authors study suitable process parameters, and the resulting pattern formation, in additive layer-by-layer fabrication of arbitrarily shaped three-dimensional (3D) silicon (Si) micro- and nanostructures. The layer-by-layer fabrication process investigated is based on alternating steps of chemical vapor deposition of Si and local implantation of gallium ions by focused ion beam writing. In a final step, the defined 3D structures are formed by etching the Si in potassium hydroxide, where the ion implantation provides the etching selectivity.

  • 27.
    Hamawandi, Bejan
    et al.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Noroozi, Mohammad
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ergül, Adem
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Zahmatkesh, Katayoun
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Toprak, Muhammet S.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Electrical properties of sub-100 nm SiGe nanowires2016In: Journal of semiconductors, Vol. 37, no 10Article in journal (Refereed)
    Abstract [en]

    In this study, the electrical properties of SiGe nanowires in terms of process and fabrication integrity, measurement reliability, width scaling, and doping levels were investigated. Nanowires were fabricated on SiGe-on oxide (SGOI) wafers with thickness of 52 nm and Ge content of 47%. The first group of SiGe wires was initially formed by using conventional I-line lithography and then their size was longitudinally reduced by cutting with a focused ion beam (FIB) to any desired nanometer range down to 60 nm. The other nanowires group was manufactured directly to a chosen nanometer level by using sidewall transfer lithography (STL). It has been shown that the FIB fabrication process allows manipulation of the line width and doping level of nanowires using Ga atoms. The resistance of wires thinned by FIB was 10 times lower than STL wires which shows the possible dependency of electrical behavior on fabrication method.

  • 28.
    Haralson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sibaja-Hernandez, Arturo
    Xu, Mingwei
    Malm, Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    HRXRD analysis of SiGeC layers for BiCMOS applications2004Conference paper (Refereed)
    Abstract [en]

    The use of HRXRD for the monitoring of the dopant activation anneal through the detection of carbon outdiffusion has been demonstrated. The advantages of HRXRD over other measurement techniques for in-line epi-growth monitoring are also discussed. HRXRD reciprocal space mapping was used to study the SiGe layer stability as a function of carbon concentration for vertically scaled layers designed for high performance BiCMOS applications. It was found that as the carbon concentration is increased there is a reduction of boron cluster formation, but an increase in defect density is also observed.

  • 29.
    Haralson, Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Suvar, E.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    NiSi integration in a non-selective base SiGeCHBT process2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 03-jan, p. 245-248Article in journal (Refereed)
    Abstract [en]

    A self-aligned nickel silicide (salicide) process is integrated into a non-selective base SiGeC HBT process. The device features a unique, fully silicided base region that grows laterally under the emitter pedestal. This Ni(SiGe) formed in this base region was found to have a resistivity of 23-24 muOmega cm. A difference in the silicide thickness between the boron-doped SiGeC extrinsic base region and the in situ phosphorous-doped emitter region is observed and further analyzed and confirmed with a blanket wafer silicide study. The silicided device exhibited a current gain of 64 and HF device performance of 39 and 32 GHz for f(t) and f(MAX), respectively.

  • 30.
    Haralson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    The effect of C on emitter-base design for a single-polysilicon SiGe: C HBT with an IDP emitter2004In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Vol. 224, no 1-4, p. 330-335Article in journal (Refereed)
    Abstract [en]

    A differential epitaxy SiGe:C heterojunction bipolar junction transistor (HBT) design is reported and used to study the effect of carbon on junction formation as well as the effect of lateral design parameters on ac and dc performance. The device exhibits a high current gain (beta) of 1700 and a BVCEO of 1.8 V. The peak cutoff frequency (f(T)) and maximum oscillation frequency (f(MAX)) are 73 and 17 GHz, respectively. The effect of emitter overlap on f(T) was minimal, but it had a strong impact on dc performance. LOCOS opening size strongly impacted both ac and dc performance. In addition, the effect of carbon, base cap thickness, and rapid thermal anneal (RTA) temperature on the emitter-base (E-B) junction formation was studied.

  • 31. Hu, Cheng
    et al.
    Xu, Peng
    Fu, Chaochao
    Zhu, Zhiwei
    Gao, Xindong
    Jamshidi, Asghar
    KTH, School of Information and Communication Technology (ICT).
    Noroozi, Mohammad
    KTH, School of Information and Communication Technology (ICT).
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Dongping
    Zhang, Shi-Li
    Characterization of Ni(Si,Ge) films on epitaxial SiGe(100) formed by microwave annealing2012In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 101, no 9, p. 092101-Article in journal (Refereed)
    Abstract [en]

    Microwave annealing (MWA) is investigated as an alternative technique to rapid thermal processing with halogen lamp heating (RTP) for low-temperature silicide formation on epitaxially grown Si0.81Ge0.19 layers. Phase formation, resistivity mapping, morphology analysis, and composition evaluation indicate that the formation of low-resistivity NiSi1-xGex by means of MWA occurs at temperatures about 100 degrees C lower than by RTP. Under similar annealing conditions, more severe strain relaxation and defect generation are therefore found in the remaining Si0.81Ge0.19 layers treated by MWA. Although silicidation by microwave heating is in essence also due to thermal effects, details in heating mechanisms differ from RTP.

  • 32.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Blomqvist, Mats
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Persson, P. O. Å.
    Thin Film Physics Division, Department of Physics, Linköpings Universitet.
    Hultman, L.
    Thin Film Physics Division, Department of Physics, Linköpings Universitet.
    Radamson, Henry
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    The effect of carbon and germanium on phase transformation of nickel on Si1-x-yGexCy epitaxial layers2004In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 95, no 5, p. 2397-Article in journal (Refereed)
    Abstract [en]

    The influence of carbon and germanium on phase transformation and sheet resistance of Ni on epitaxially grown Si1-x-yGexCy (0less than or equal toxless than or equal to0.24 and 0less than or equal toyless than or equal to0.01) layers annealed in a temperature range of 360 to 900degreesC has been investigated. The role of strain relaxation or compensation in the reaction of Ni on Si1-x-yGexCy layers due to Ge or C out-diffusion to the underlying layer during the phase transformation has also been investigated. The formed NiSiGe layers were crystalline, with strong (020)/(013) growth orientation in the direction, but the thermal stability decreased rapidly with increasing Ge amount due to agglomeration. However, this thermal behavior was shifted to higher annealing temperatures when carbon was incorporated in the SiGe layers. A carbon accumulation at the interface of NiSiGeC/SiGeC has been observed even at low-temperature annealing, which is suggested to retard the phase transformation and agglomeration of Ni/SiGeC system.

  • 33.
    Hållstedt, Julius.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs2008In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, p. 117-120Article in journal (Refereed)
    Abstract [en]

    Today MOSFET devices are approaching gate lengths on the order of 10 nm. This sets extreme demands on gate patterning technique. This paper describes a side wall transfer lithography technique to pattern decananomeer MOSFETs or nanowires. A correlated line edge roughness leading to a very low line width roughness was demonstrated for the patterned gates. Moreover, the technology was shown to be robust and reproducible with high yield and uniformity suitable for mass fabrication. Finally, integration of the sidewall transfer lithography was performed in various novel MOSFET devices.

  • 34.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Edholm, Jonas
    Lu, J.
    Uppsala University, Ångström Laboratory.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A robust spacer gate process for deca-nanometer high-frequency MOSFETs2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 3, p. 434-439Article in journal (Refereed)
    Abstract [en]

    This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

  • 35.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Baubinas, R.
    Matukas, J.
    Palenskis, V.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Application of selective epitaxy for formation of ultra shallow SiGe-based junctions2004In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 114-115, no SPEC. ISS, p. 180-183Article in journal (Refereed)
    Abstract [en]

    Selective epitaxial growth (SEG) of B-, P- and As-doped Si1-xGex (0.12 < x < 0.26) layers on patterned substrates, aimed for source/drain ultra shallow junctions was investigated. The SiGe layers were deposited selectively on Si surface that is either unprocessed or previously in situ etched by HCl in the same run in a reduced pressure chemical vapor deposition reactor. In these investigations selectivity mode, pattern dependency (loading effect), defect generation and dopant incorporation in SiGe layers have been discussed. It was demonstrated that the growth rate increased in presence of B in SiGe while it decreased for P- and As-doped layers. The amount of Ge was constant for B-doped samples while it increased for As- and P-doped SiGe layers. The epitaxial quality was dependent on the Ge amount, growth rate and dopant concentration. The selectivity mode of the growth was dependent on B partial pressure, however, no effect was observed for P- or As-doping in SiGe layers. A resistivity value of similar to10(-3) Omega cm was obtained for B- and P-doped SiGe layers with optimized growth parameters.

  • 36.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, R.
    Texas Instruments, Dallas.
    Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal oxide semiconductor field effect transistors2008In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 103, no 5, p. 054907-Article in journal (Other academic)
    Abstract [en]

    This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1-xGex (x=0.14-0.32) layers. It is shown with a comprehensive experimental study that the local Si coverage of individual chips on patterned wafers is the main parameter for the layer profile in the epitaxial growth. This was explained by the gas depletion of the growth species in the low velocity boundary layer over the wafer. The gas depletion radius around each oxide opening was in the centimeter range which is related to the boundary layer thickness. The results from these experiments were applied to grow Si0.75Ge0.25 layers with B concentration of 4x10(20) cm(-3) selectively for elevated source and drains in fully depleted ultrathin body silicon on insulator p metal oxide semiconductor field effect transistor (p-MOSFET) devices. The epitaxy control was maintained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing a uniform gas depletion over the chips on the wafer.

  • 37.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Parent, A.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Incorporation of boron in SiGe(C) epitaxial layers grown by reduced pressure chemical vapor deposition2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 03-jan, p. 97-101Article in journal (Refereed)
    Abstract [en]

    In this paper the strain and electrical properties of epitaxial in situ B-doped (10(18)-10(21) cm(-3)) SiGeC layers (23, 28% Ge and 0, 0.5% C) has been investigated. The growth rate was shown to have a significant increase at 3 x 10(-2) mTorr diborane partial pressure. This point coincides with an enhancement in boron incorporation, which was explained by the strain compensation effect of boron in the highly strained SiGeC layers. In these samples, the total Ge and C content was shown to remain constant with increasing diborane partial pressure. The substitutional/active dopant concentration in SiGe layers was obtained by high-resolution X-ray diffraction by measuring the strain compensation effect of boron. The interaction between C and B in SiGe matrix was also investigated. This was compared with the active dopant concentration obtained from Hall measurements in order to achieve a Hall scattering factor of 0.3-0.7 for dopant concentrations between 3 x 10(18) and 5 x 10(21) cm(-3). The resistivity values of these layers were in the range 2 x 10(-2) -4 x 10(-4) Omega cm. Finally, it was shown that boron atoms in SiGeC layers locate preferably at substitutional sites in contrary to carbon atoms at both substitutional and interstitial sites.

  • 38.
    Hållstedt, Julius.
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Parent, Arnaud
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Strain and electrical characterization of boron-doped SiGeC layers grown by chemical vapor deposition2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 31-33Article in journal (Refereed)
    Abstract [en]

    Incorporation, induced strain and electrical properties of boron and carbon in Si1-x-yGexCy epitaxial layers (x = 0.23 and 0.28 with y = 0 and 0.005) grown by chemical vapour deposition (CVD) have been studied. The boron concentration in the epitaxial layers was in the range of 3 x 10(18)-1 x 10(21) cm(-3). The growth rate enhanced weakly by increasing boron partial pressure up to 0.002 mtorr ( corresponding to 2 x 10(19) cm(-3)) where a significant increase in deposition rate was observed. In SiGeC layers, the active boron concentration was obtained from the strain compensation amount. It was also found that the boron atoms have a tendency to locate at substitutional sites more preferentially compared to carbon. The incorporation of boron in SiGeC layers was clearly improved in the range 2 x 10(19)-3 x 10(20) cm(-3). These investigations also enabled an estimation of the Hall scattering factor of the SiGeC layers. A comparison between our results with the previous theoretical calculations showed a good agreement. This created the possibility to evaluate the drift mobility in our samples.

  • 39.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Menon, Cyril
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Methods to reduce the loading effect in selective and non-selective epitaxial growth of sigec layers2004In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 109, no 03-jan, p. 122-126Article in journal (Refereed)
    Abstract [en]

    Various methods to reduce both global and local loading effect during non-selective and selective epitaxial growth of Si1-x-yGexCy (0.09 less than or equal to x less than or equal to 0.28 and 0 less than or equal to y less than or equal to 0.01) layers have been proposed. Evaluation of the proposed solutions for issues such as defect generation and the possibility for integration in device structures have been performed. The key point in these methods is based on reduction of surface diffusion of the adsorbed species on the oxide. In non-selective epitaxy, this was achieved by introducing a thin silicon polycrystalline seed layer on the oxide prior to Si1-x-yGexCy deposition. The thickness of this seed layer had a crucial role on both the global and local loading effect, and also on the epitaxial quality. Higher carbon content (y greater than or equal to 0.006) in Si1-x-yGexCy layers had no noticeable influence on the loading effect, however, the defect density was clearly increased in these layers. In selective epitaxy case, introducing square polycrystalline Si stripes around the oxide openings acting as diffusion barriers have reduced the loading effect effectively. Meanwhile, using Si nitride stripes showed no visible effect on Si1-x-yGexCy layer profile. Further decrease in loading effect can be performed by increasing the HCl partial pressure during epitaxy. Chemical-mechanical polishing (CMP) was performed to remove the polycrystalline stripe on the oxide.

  • 40.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Persson, P. O. Å.
    Department of Physics, Thin Film Physics Division, Linköpings Universitet.
    Hultman, L.
    Department of Physics, Thin Film Physics Division, Linköpings Universitet.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Growth of high quality epitaxial Si1-x-yGexCy layers by using chemical vapor deposition2004In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Applied Surface Science, Vol. 224, no 1-4, p. 46-50Article in journal (Refereed)
    Abstract [en]

    The epitaxial quality of non-selective and selective deposition of Si1-x-yGexCy (0 less than or equal to x less than or equal to 0.30, 0 less than or equal to y less than or equal to 0.02) layers has been optimized by using high-resolution reciprocal lattice mapping (HRRLM). The main goal was to incorporate a high amount of substitutional carbon atoms in Si or Si1-xGex matrix without creating defects. The carbon incorporation behavior was explained by chemical and kinetic effects of the reactant gases during epitaxial process. Although high quality epitaxial Si1-yCy layers can be deposited, lower electron mobility compared to Si layers was observed.

  • 41.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels2006In: ECS Transactions, ISSN 1938-5862, E-ISSN 1938-6737, Vol. 3, no 7, p. 67-72Article in journal (Refereed)
    Abstract [en]

    State of the art bulk and fully depleted SOI Si and SiGe channel pMOSFET devices with gate lengths ranging from 0.1 to 200 μm were fabricated and analyzed in terms of drain current drivability, mobility and noise performance. In general the SOI devices demonstrated superior mobility and significantly reduced I/f noise compared to bulk devices maintaining a well controlled short channel effects due to the ultra thin body.

  • 42.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels2006In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 6, p. 466-468Article in journal (Refereed)
    Abstract [en]

    The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

  • 43.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    MOSFETs with recessed SiGe Source/Drain junctions formed by selective etching and growth2004In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775, Vol. 7, no 4, p. G53-G55Article in journal (Refereed)
    Abstract [en]

    A source/drain extension process that uses HCl etching followed by selective growth of in situ B-doped SiGe is demonstrated. The two key process steps, etching and growth, are integrated by performing them consecutively in the same chemical vapor deposition reactor. The technique has the potential to solve end-of-the-roadmap requirements on junction depth, junction abruptness, and active doping concentration.

  • 44.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Selective Si etching using HCl vapor2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 107-109Article in journal (Refereed)
    Abstract [en]

    Selective Si etching using HCl in a reduced pressure chemical vapor deposition reactor in the temperature range 800-1000 degrees C is investigated. At 900 degrees C, the etch process is anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. This behavior indicates that the etch process is limited by surface reaction, since the etch rate in the directions with higher atomic concentration is lower. When the temperature is decreased to 800 degrees C, etch pits occur. A more isotropic etch is obtained at 1000 degrees C, however at this temperature the masking oxide is attacked and the etch surface is rough. Thus the temperature has to be confined to a narrow window to yield desirable properties under the present process conditions.

  • 45.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Process integration of a new method for formation of shallow junctions in MOSFET structures using recessed and selectively regrown Si1-xGex2004Conference paper (Refereed)
    Abstract [en]

    Process integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The proposed concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. Nitride residues and surface damage originating from RIE are shown to be detrimental for the epitaxial quality.

  • 46.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Recessed and epitaxially regrown SiGe(B) source/drain junctions with Ni salicide contacts2004In: Silicon Front-End Junction Formation-Physics And Technology / [ed] Pichler, P; Claverie, A; Lindsay, R; Orlowski, M; Windl, W, 2004, Vol. 810, p. 49-54Conference paper (Refereed)
    Abstract [en]

    Integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. When integrated in the PMOS process flow, the resulting Si1-xGex layer is very rough. Several possible causes for low quality epitaxy are discussed and improvements are proposed. It is suggested that the dopant type and/or concentration in the silicon substrate can have an effect on the process.

  • 47.
    Isheden, Christian
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    pMOSFETs with recessed and selectively regrown Si1-xGex source/drain junctions2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 1-3, p. 359-362Article in journal (Refereed)
    Abstract [en]

    A new source/drain formation concept based on selective Si etching followed by selective regrowth of in situ B-doped Si(1-x)Ge(x)is presented. Both process steps are performed in the same reactor to preserve the gate oxide. Well-behaved transistors are demonstrated with a negligibly low gate-to-substrate leakage current.

  • 48.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Formation of shallow junctions by HCl-based Si etch followed by selective epitaxy of B-doped Si1-xGex in RPCVD2004In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 151, no 6, p. C365-C368Article in journal (Refereed)
    Abstract [en]

    Formation of shallow source/drain junctions by using HCl-based Si etch followed by selective deposition of in situ heavily B-doped SiGe in a reduced pressure chemical vapor deposition reactor is presented. The etching parameters were optimized to obtain a smooth surface prior to deposition of the SiGe layers. In the epitaxy process, SiGe layers with a resistivity of 5 x 10(-4) Omega cm were obtained by tuning the partial pressure of the B and Ge precursors. A problem with selectivity in the epitaxy step was encountered when combing the etch and growth processes, but a practical solution is presented. Integration issues such as loading effect, pile-up, and defect generation have also been investigated.

  • 49.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Seger, Johan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Formation of Ni mono-germanosilicide on heavily B-doped epitaxial SiGe for ultra-shallow source/drain contacts2003In: Materials Research Society Symposium Proceedings, ISSN 0272-9172, E-ISSN 1946-4274, Vol. 745, p. 117-122Article in journal (Refereed)
    Abstract [en]

    The formation of Ni germanosilicides during solid-state interaction between Ni and heavily B-doped strained epitaxial Si1-xGex films with x=0.18, 0.32 and 0.37 is studied. No NiSi2 is found in these samples even after annealing at 850 degreesC, which can be compared to the formation of NiSi2 at 750 T on Si(I 00). Resistance and diffraction studies for the Si0.82Ge0.18 sample indicate that NiSi0.82Ge0.18 forms and the NiSi0.82Ge0.18/Si0.82Ge0.18 structure is stable from 400 to 700 degreesC. For the NiSi1-uGeu formed in all Si1-xGex samples, where u can be different from x, a strong film texturing is observed. When the Ge fraction is increased from 18 at.% to 32-37 at.%, the morphological stability of the film is degraded and a substantial increase in sheet resistance occurs already at 600 degreesC. The contact resistivity for the NiSi0.8Ge0.2/Si0.8Ge0.2 interface formed at 550 T is determined as 1.2x10(-7) Omegacm(2), which satisfies the ITRS contact resistivity requirement for the 70 nm technology node.

  • 50.
    Jamshidi, Asghar
    et al.
    KTH.
    Noroozi, Mohammad
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Moeen, M.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hamawandi, Bejan
    KTH.
    Lu, J.
    Hultman, L.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Growth of GeSnSiC layers for photonic applications2013In: Surface & Coatings Technology, ISSN 0257-8972, E-ISSN 1879-3347, Vol. 230, p. 106-110Article in journal (Refereed)
    Abstract [en]

    This work presents epitaxial growth of intrinsic and doped GeSnSiC layers using Ge2H6, SnCl4, CH3SiH3, B2H6, PH3 and Si2H6 deposited at 290-380 degrees C on strain relaxed Ge buffer layer or Si substrate by using reduced pressure chemical vapor deposition (RPCVD) technique. The GeSnSi layers were compressively strained on Ge buffer layer and strain relaxed on Si substrate. It was demonstrated that the quality of epitaxial layers is dependent on the growth parameters and that the Sn content in epi-layers could be tailored by growth temperature. The Sn segregation caused surface roughness which was decreased by introducing Si and Si-C into Ge layer. The Sn content in GeSn was carefully determined from the mismatch, both parallel and perpendicular, to the growth direction when the Poisson ratio was calculated for a certain Ge-Sn composition. The X-ray results were excellently consistent with Rutherford Backscattered Spectroscopy (RBS). Strain relaxed GeSn layers were also used as virtual substrate to grow tensile-strained Ge layers. The Ge cap layer had low defect density and smooth surface which makes it a viable candidate material for future photonic applications.

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