Change search
Refine search result
1 - 31 of 31
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Gisdakis, Stylianos
    et al.
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Manolopoulos, Vasileios
    KTH.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Papadimitratos, Panagiotis
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Secure and Privacy-Preserving Smartphone based Traffic Information Systems2015In: IEEE transactions on intelligent transportation systems (Print), ISSN 1524-9050, E-ISSN 1558-0016, Vol. 16, no 3Article in journal (Refereed)
    Abstract [en]

    Increasing smartphone penetration, combined with the wide coverage of cellular infrastructures, renders smartphone-based traffic information systems (TISs) an attractive option. The main purpose of such systems is to alleviate traffic congestion that exists in every major city. Nevertheless, to reap the benefits of smartphone-based TISs, we need to ensure their security and privacy and their effectiveness (e.g., accuracy). This is the motivation of this paper: We leverage state-of-the-art cryptographic schemes and readily available telecommunication infrastructure. We present a comprehensive solution for smartphone-based traffic estimation that is proven to be secure and privacy preserving. We provide a full-blown implementation on actual smartphones, along with an extensive assessment of its accuracy and efficiency. Our results confirm that smartphone-based TISs can offer accurate traffic state estimation while being secure and privacy preserving.

  • 2.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Papadimitratos, Panos
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Securing smartphone based ITS2011In: ITST 2011: Proceedings of the 11th International Conference on ITS Telecommunications, 2011, 2011, p. 201-206Conference paper (Refereed)
    Abstract [en]

    GPS-equipped smartphones present several advantages for data acquisition in Intelligent Transportation Systems (ITS), compared to solutions that require a new communication infrastructure. However, there are still significant challenges to meet before deployment. Traffic information and location samples must be collected in a secure manner, to not jeopardize the system operation. Equally important, users must be assured about their privacy, notably the protection of information on their whereabouts. To address this two-fold problem, we propose extending the Generic Bootstrapping Architecture (GBA) with anonymous authentication. Identity and location information are protected and separated, and location samples cannot be linked to each other and to any specific user. Thus, our scheme protects users even in the case of a compromised ITS server. Initial evaluation results indicate the feasibility of our approach with off-the-self mobile platforms.

  • 3.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    MobiTraS: a mobile application for a Smart Traffic System2010In: Proceedings of the 8th IEEE International NEWCAS Conference, IEEE , 2010, p. 365-368Conference paper (Refereed)
    Abstract [en]

    Traffic monitoring systems deployed until now, use data collected mainly through fixed sensors. Advances on the modern mobile devices have made possible the development of S mart Traffic Systems, which use the traffic information g athered by the drivers' mobile devices to provide route guidance. Our work is focused on building a Real-Time Traffic Information System based mobile devices, which are used for both acquiring traffic information data and for providing feedback and guidance to drivers. This paper presents an analysis of the system, its security risks and requirements for dynamic route guidance together with possible solutions. A key component of the system is the mobile application that gathers data in an encrypted way and displays information to the users. The developed JavaME mobile application and its security/privacy features are also described.

  • 4.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Papadimitratos, Panagiotis
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Smartphone-based Traffic Information System for Sustainable Cities2012In: Mobile Computing and Communications Review, ISSN 1559-1662, Vol. 16, no 4, p. 30-31Article in journal (Refereed)
    Abstract [en]

    Traffic Information Systems (TISs) can play a significant role towards creating sustainable cities through improved traffic conditions. The collection of reliable and rich information with low cost is paramount. The use of smartphones carried by individuals for future implementations of TISs present several advantages compared to traditional solutions. This demo integrates our results from previous work addressing challenges on traffic estimation for urban road networks and on security and privacy protection for such TISs.

  • 5.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Papadimitratos, Panos
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Smartphone-based Traffic Information System for Sustainable Cities2012Conference paper (Refereed)
  • 6. Moradi, M.
    et al.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Mirzaee, R. F.
    Physical Unclonable Functions Based on Carbon Nanotube FETs2017In: 2017 IEEE 47th International Symposium on Multiple-Valued Logic ISMVL 2017 : proceedings: 22-24 May 2017, Novi Sad, Serbia, IEEE Computer Society, 2017, p. 124-129, article id 7964978Conference paper (Refereed)
    Abstract [en]

    Physical unclonable functions (PUFs) are new hardware security primitives proposed for protecting resource-constrained devices. This paper presents two PUFs in voltage-and current-modes. The new designs are based on carbon nanotube field effect transistors (CNTFETs). Sensitivity to strong process variation is considered as a demerit of this emerging nanoscale device. However, this deficiency can be the source of constructing unique PUF instances. The proposed circuits are simulated and tested by Synopsys HSPICE using a standard 32nm CNTFET technology. The properties of randomness, uniqueness, reliability, energy efficiency, and area of the implemented CNTFET-based PUFs are evaluated showing very promising results.

  • 7.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An IIP2 Digital Calibration Technique for Passive CMOS Down-Converters2010In: IEEE INT SYMP CIRC SYST PROC, New York: IEEE , 2010, p. 825-828Conference paper (Refereed)
    Abstract [en]

    The IIP2 requirement in fully integrated direct-conversion receivers using FDD duplexing is prohibitively high and demands the use of an external filter in order to attenuate the leakage from the transmitter. This paper presents a digital calibration technique for passive CMOS down-converters that allows a direct conversion receiver achieve the requirements without external filtering. A Least-Mean-Square optimization algorithm is used in order to reduce the low-frequency second-order intermodulation product. The algorithm controls the digital calibration structures at the biasing of the passive mixer and adapts them until the second order intermodulation drops below the noise level. The method is tested by calibrating a 1.2-V 65nm CMOS passive mixer targeting UMTS/LTE applications at several corner conditions including worst case mismatches in the switching pairs.

  • 8.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Advances in Technologies for Implantable Bioelectronics2016In: Wireless Medical Systems and Algorithms: Design and Applications / [ed] Pietro Salvo and Miguel Hernandez-Silveira, CRC Press, 2016, p. 3-20Chapter in book (Refereed)
  • 9.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mobile Phone-based Vehicle Positioning and Tracking and Its Application in Urban Traffic State Estimation2012Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Enabling the positioning and tracking of mobile phones has emerged as a key facility of existing and future generation mobile communication systems. This feature provides opportunities for many value added location-based services and systems. For instance, mobile phones are increasingly employed in traffic infor­mation systems and present several advantages over traditional sensor-based traffic systems. However, there are still plenty of aspects that must be investigated and addressed towards the fully operational deployment. The aim of the research per­formed in this thesis is to examine and propose solutions to two of the problems in the deployment of a mobile phone-based smart traffic information system.

        The first problem investigated is the mobile phone-based vehicle positioning and tracking. The investigation starts with a comprehensive study of mobile positioning with emphasis on existing standardizations. Based on the mobile location methods standardized in UMTS, possible hybrid solutions are proposed. In addition, a tool for simulating one of the UMTS mobile positioning methods (i.e., OTDOA) in vehicular environment is developed. A Kalman filter-based hybrid method, which can track the mobile phones traveling on-board vehicles, is then implemented. This method fuses two of the UMTS standard methods (i.e., OTDOA and A-GPS) loca­tion estimates at the state-vector level. Statistical simulation results demonstrate that the hybrid method can provide better position and velocity estimations than each individual method.

        The second problem addressed is the mobile phone-based urban traffic state estima­tion. A traffic simulation-based framework is proposed to emulate and evalu­ate the operation of urban traffic state estimation with A-GPS mobile phones as probes. Based on the emulated mobile phone probe data, algorithms of location data processing/filtering and average speed estimation are developed and then evaluated by comparing against “ground truth” data from the traffic simulation. Moreover, the estimated average speeds are classified to different traffic condition levels, which are prepared for displaying a traffic map on the mobile phone display. The achieved simulation results demonstrate the effectiveness of the proposed method, which is fundamental for the subsequent development of a mobile phone-based smart traffic information system demonstrator.

  • 10.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters2015Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels.

    The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme.

    A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations.

    A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs. 

  • 11.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Chi, Jiazuo
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Design Considerations for Pipelined Continuous-Time Incremental Sigma-Delta ADCs2015In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE conference proceedings, 2015, p. 1014-1017Conference paper (Refereed)
    Abstract [en]

    This paper addresses design considerations for power-efficient pipelined continuous-time (CT) incremental Sigma-Delta (IΣ∆) ADC architectures. By pipelining identical CT IΣ∆ ADC stages, the proposed architecture provides the design freedom coming from both the pipeline ADC and the IΣ∆ ADC. In searching for a low-power solution given a target resolution, different configurations are examined analytically and simulated using behavioral models. For further power reduction, power-efficient circuits are proposed to implement the active blocks in each configuration. Based on the architecture-level analysis, a configuration that leads to minimum power-area consumption is chosen and implemented as a test-case using the proposed circuit blocks. Post-layout simulations show that the test-case ADC, with 3.2-kHz bandwidth, achieves a peak SNDR of 82.5-dB while dissipating a total power of 18.27-μW. 

  • 12.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    An Ultra-Energy-Efficient Temperature-Stable Physical Unclonable Function in 65nm CMOS2016In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 52, no 10, p. 805-806Article in journal (Refereed)
    Abstract [en]

    Physical unclonable functions (PUFs) are promising hardware security primitives suitable for resource-constrained devices requiring lightweight cryptographic methods. This letter proposes an ultra-low-power and reliable PUF based on a customized dynamic two-stage comparator operating in the sub-threshold region. The proposed PUF is implemented in a standard 65nm CMOS technology and validated through Monte-Carlo simulations. Evaluation results show a worst-case reliability of 98.3% over the commercial temperature range of 0°C to 85°C and 10% fluctuations in supply voltage. In addition, the 128-bit PUF array consumes only 1.33 µW at 1 Mb/s, which corresponds to 10.3 fJ/bit, being the most energy-efficient design to date.

  • 13.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronics.
    MVL-PUFs: multiple-valued logic physical unclonable functions2017In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 45, no 2, p. 292-304Article in journal (Refereed)
    Abstract [en]

    Physical unclonable functions (PUFs) are promising hardware security primitives suitable for protecting resource-constrained devices. In this paper, we propose to use multiple-valued logic (MVL) for implementing hardware-efficient PUF integrated circuits. We show that by extracting device mismatch in either current-mode or voltage-mode MVL comparators, the proposed PUF circuits can generate unique and reliable chip identifiers. In order to stabilize PUF responses, we utilize multiple thresholds of MVL comparators, whose outputs are selected and combined according to the sensed temperature. To reduce power and further enhance reliability, the PUF circuits are biased in the weak-inversion region. Evaluation results show that the proposed MVL-PUFs are unique and reliable over a wide temperature range. In addition, they significantly improve the energy efficiency of the state-of-the-art PUFs.

  • 14.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Reliable low-overhead arbiter-based physical unclonable functions for resource-constrained IoT devices2017In: ACM International Conference Proceeding Series, Association for Computing Machinery (ACM), 2017, p. 1-6, article id 3031837Conference paper (Refereed)
    Abstract [en]

    Physical unclonable functions (PUFs) are promising hardware security primitives suitable for resource-constrained devices requiring lightweight cryptographic methods. However, PUF responses frequently suffer from instability due to varying environmental conditions such as voltage and temperature. In this paper, we introduce circuit-level techniques to enhance the reliability of delay-based PUFs against temperature variation. We propose a voltage controlled current starved (VCCS) delay element that can effectively reduce temperature sensitivity and thus improve the reliability of PUF responses. Built on the VCCS delay element, two test-case arbiter-based PUF architectures are implemented in a standard 65nm CMOS technology and validated through post-layout Monte-Carlo simulation. Evaluation results show that two proposed PUF designs satisfy requirements on randomness, uniqueness, and reliability over a wide temperature range. Moreover, the proposed approach imposes only a marginal overhead leading to one of the most energy-efficient PUFs in the state-of-the-art.

  • 15.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillators2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 686-691, article id 7927077Conference paper (Refereed)
    Abstract [en]

    Physical unclonable functions (PUFs) are promising hardware security primitives suitable for low-cost cryptographic applications. Ring oscillator (RO) PUF is a well-received silicon PUF solution due to its ease of implementation and entropy evaluation. However, the responses of RO-PUFs are susceptible to environmental changes, in particular, to temperature variations. Additionally, a conventional RO-PUF implementation is usually more power-hungry than other PUF alternatives. This paper explores circuit-level techniques to design low-power RO-PUFs with enhanced thermal stability. We introduce a power-efficient approach based on a phase/frequency detector (PFD) to perform pairwise comparisons of ROs. We also propose a temperature compensated bulk-controlled oscillator (BCO) and investigate its feasibility and usage in PFD-based RO-PUFs. Evaluation results demonstrate that the proposed techniques can effectively reduce the thermally induced errors in PUF responses while imposing a low power overhead. The PFD-based BCO-PUF is one of the best among existing RO-PUFs in terms of power efficiency.

  • 16.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronics.
    TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches2017In: Proceedings of The International Symposium on Multiple-Valued Logic, IEEE Computer Society, 2017, p. 130-135, article id 7964979Conference paper (Refereed)
    Abstract [en]

    True random number generators (TRNGs) are important hardware primitives required for many applications including cryptography, communication, and statistical simulation. This paper presents a TRNG with failure detection capability targeting cryptographic applications with a limited power budget. The proposed TRNG extracts entropy from latch comparators, whose metastable states are detected and encoded as an additional alarm bit leading to ternary valued outputs. Furthermore, several such ternary valued latches (TVLs) are employed in an N-modular redundant configuration to address the bias problem caused by unmatched conditions. The statistical properties of the proposed TVL-TRNG are examined by the NIST 800-22 and NIST 800-90B test suits showing resistance against environmental changes and process variations. The proposed TRNG circuit designed in 65 nm CMOS consumes 825.36 nW at 1 Mbps.

  • 17.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garcia, Julian
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Analysis of Exponentially Decaying Pulse Shape DACs in Continuous-Time Sigma-Delta Modulators2012In: Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on, IEEE , 2012, p. 424-427Conference paper (Refereed)
    Abstract [en]

    The performance of continuous-time (CT) sigma-delta (ΣΔ) modulators is severely degraded by the clock jitter induced timing variation in their feedback digital-to-analog converters (DACs). To mitigate this non-ideality, jitter sensitivity reduction techniques that employ exponentially decaying pulse shape DACs have been recently reported. In this paper, exponentially decaying DACs are investigated and generalized expressions are derived. In addition, another exponentially decaying DAC proposed, which can potentially achieve both good jitter immunity and amplitude efficiency. To validate the theoretical results, the proposed DAC, together with other exponentially decaying DACs, are employed in a 3rd order 1-bit CT ΣΔ modulator test case and evaluated through behavioral simulations.

  • 18.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garcia, Julian
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Impact of Feedback DAC Timing Errors in Continuous-Time Incremental Sigma-Delta DACs2014In: SSoCC 2014, 2014Conference paper (Other academic)
  • 19.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Manolopoulos, Vasileios
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hybrid Vehicle Positioning and Tracking Using Mobile Phones2011In: 2011 11th International Conference on ITS Telecommunications, ITST 2011, 2011, p. 315-320Conference paper (Refereed)
    Abstract [en]

    Due to the pervasive deployments of mobile communication technologies, vehicle positioning and tracking by locating the driver's mobile phones has become feasible. However, no single positioning method can provide decent tradeoff between accuracy and coverage. To address this issue, we propose a Kalman filter-based hybrid method which can track the mobile phones traveling on-board vehicles. The proposed method combines coordinates collected by assisted global positioning system (A-GPS) mobile phones and location estimates calculated from observed time difference of arrival (OTDOA) measurements. Numerical results demonstrate the effectiveness of this hybrid scheme in a simulated vehicular scenario.

  • 20.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Manolopoulos, Vasileios
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Real-Time Urban Traffic State Estimation with A-GPS Mobile Phones as Probes2012In: Journal of Transportation Technologies, ISSN 2160-0481, Vol. 2, no 1, p. 22-31Article in journal (Refereed)
    Abstract [en]

    This paper presents a microscopic traffic simulation-based method for urban traffic state estimation using Assisted Global Positioning System (A-GPS) mobile phones. In this approach, real-time location data are collected by A-GPS mobile phones to track vehicles traveling on urban roads. In addition, tracking data obtained from individual mobile probes are aggregated to provide estimations of average road link speeds along rolling time periods. Moreover, the estimated average speeds are classified to different traffic condition levels, which are prepared for displaying a real-time traffic map on mobile phones. Simulation results demonstrate the effectiveness of the proposed method, which are fundamental for the subsequent development of a system demonstrator.

  • 21.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    DAC Waveform Effects in CT Incremental ΣΔ ADCs for Biosensor Applications2013In: 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, IEEE conference proceedings, 2013, p. 6573569-Conference paper (Refereed)
    Abstract [en]

    Incremental sigma-delta (IΣΔ) analog-to-digital converters (ADCs), which are essentially ΣΔ ADCs with periodic resetting, are well suited for low-power low-speed biosensor applications. In recent years, the potential advantage in terms of power dissipation of continuous-time (CT) IΣΔ ADCs have been explored. This paper analyzes the impact of feedback digital-to-analog converters (DACs) on the performance of CT IΣΔ ADCs. Different feedback DAC schemes are firstly analyzed and then evaluated by employing them in a 3rd order single-bit CT IΣΔ ADC. Simulation results are discussed considering the trade-off between the timing error sensitivity and the power consumption, thereby offering a reference for selecting a power efficient feedback DAC scheme.

  • 22.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Two-step continuous-time incremental sigma-delta ADC2013In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 49, no 12, p. 749-750Article in journal (Refereed)
    Abstract [en]

    A two-step continuous-time (CT) incremental sigma-delta (I Sigma Delta) ADC, which enhances the performance of conventional CT I Sigma Delta ADCs, is proposed. By pipelining two second-order CT I Sigma Delta ADCs, the proposed two-step architecture can achieve high resolution without sacrificing the conversion rate. Compared to other alternatives, the two-step CT I Sigma Delta ADC exhibits the freedom of adjusting its accuracy and speed independently while featuring quite relaxed circuit specifications.

  • 23.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    UMTS Mobile Positioning Simulator for Vehicle Location2010In: ICWMMN 2010, PROCEEDINGS, STEVENAGE: INST ENGINEERING TECH-IET , 2010, p. 344-347Conference paper (Refereed)
    Abstract [en]

    In this paper, a tool for simulating UMTS mobile positioning in vehicular environment has been developed The primary function of this simulator is to locate the UMTS mobile in realistic propagation environments. This tool first models the network configuration and radio propagation in a vehicular scenario Based on the system level model, it then simulates the pilot signal transmitted by a base station to a mobile station through the 3GPP WCDMA FDD downlink. The received pilots at mobile station are processed to obtain the time-difference-of-arrival estimates which are used to construct the hyperbolic equations for mobile position calculation The simulator has been implemented in the Matlab and Simulink environment.

  • 24.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vehicle Location using Wireless Wide Area Network2010In: 2010 3rd Joint IFIP Wireless and Mobile Networking Conference (WMNC), 2010Conference paper (Refereed)
    Abstract [en]

    The ability to locate the position of a mobile device has emerged as a key facility of existing and future generation mobile systems. Many value added location based services have been enabled by this feature. Due to the pervasive deployments of mobile communication technologies, vehicle positioning by locating the driver's mobile devices has become feasible. Moreover, it potentially displaces systems that were designed specifically for vehicles. This paper first investigates the standard mobile location methods and exploits this information in intelligent transportation systems, especially in vehicle location. Hybrid solutions are then proposed based on the well-established and standardized location methods.

  • 25.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Device Modelling for 60 GHz Radio Front-ends in 65 nm CMOS2009In: 2009 NORCHIP, 2009Conference paper (Refereed)
    Abstract [en]

    This paper presents an electromagnetic simulation-based modelling solution for active and passive devices which targets 60 GHz front-end integrated circuits. An EM model, using existing transistor compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on EM simulation S-parameter data is also derived. The models are process and layout dependent, which have been verified by the design of a low noise amplifier in a 60 GHz radio front-end.

  • 26.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A 60 GHz receiver front-end in 65 nm CMOS2011In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 67, no 1, p. 61-71Article in journal (Refereed)
    Abstract [en]

    In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of -13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm x 0.44 mm.

  • 27.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Comparative Design Study of Continuous-Time Incremental Sigma-Delta ADC Architectures2016In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 12, p. 2147-2163Article in journal (Refereed)
    Abstract [en]

    This paper presents a comparative design study of continuous-time (CT) incremental sigma-delta (IΣΔ) ADCs, which can expand another dimension of the IΣΔ ADC world that is dominated by discrete-time implementations. Several CT IΣΔ ADC architectures are introduced and analyzed aiming to reduce the modulator’s sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣΔ ADCs are selected to be examined, implemented, and tested. The three ADC prototypes, fabricated in a standard 0.18 μm CMOS technology, demonstrate competitive figure-of-merits in terms of power efficiency compared to the state-of-the-art counterparts.

  • 28.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems2015In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 99, p. 1-10Article in journal (Refereed)
    Abstract [en]

    This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 µm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 µW, which corresponds to a figure-of-merit of 0.85 pJ/conv.

  • 29.
    Tao, Sha
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Yu, Yang
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    FPGA Based True Random Number Generators Using Non-Linear Feedback Ring Oscillators2018In: 2018 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018, IEEE, 2018, p. 213-216Conference paper (Refereed)
    Abstract [en]

    True random number generators (TRNGs) are important hardware primitives required for many applications including cryptography, conmumication, and statistical simulation. This paper presents a non-linear feedback ring oscillator (NI, FRO) based entropy source for implementing high performance TRNGs on FPGAs. The proposed NLFRO structures harvest randomness from noise and unpredictable variation in delay cells and bi-stable elements which are further amplified by non-linear feedback loops. The outputs of NLFROs show chaotic behavior, making them suitable for implementing high entropy, high speed and attack resistance TRNGs. Three NLFRO-TRNGs are implemented and tested on an Altera 60nm FPGA device. Raw entropy and statistical properties of the NLFRO-TRNGs are examined by the NIST 800-22 entropy estimation and NIST 800-90B statistical test suits. Compared to the prior art, experimental NLFRO-TRNGs show higher entropy and lower resource usage while consuming sub-milliwatt at 200 Mbps.

  • 30.
    Yu, Yang
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Näslund, Mats
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Tao, Sha
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. Royal Inst Technol, Sch EECS, S-16440 Stockholm, Sweden..
    On Designing PUF-Based TRNGs with Known Answer Tests2018In: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings / [ed] Nurmi, J Ellervee, P Mihhailov, J Jenihhin, M Tammemae, K, Institute of Electrical and Electronics Engineers (IEEE), 2018, article id 8573489Conference paper (Refereed)
    Abstract [en]

    Random numbers are widely used in cryptographic algorithms and protocols. A faulty true random number generator (TRNG) may open a door into a system in spite of cryptographic protection. It is therefore important to design TRNGs so that they can be tested at different stages of their lifetime to assure their trustworthiness. In this paper, we propose a method for designing physical unclonable function (PUF)-based TRNGs which can be tested in-field by known answer tests. We present a prototype FPGA implementation of the proposed TRNG based on an arbiter PUF which passes all NIST 800-22 statistical tests and has the minimal entropy of 0.918 estimated according to NIST 800-90B recommendations. This is a nontrivial achievement given that arbiter PUFs are notoriously hard to place in a symmetric manner in FPGAs.

  • 31.
    Yu, Yang
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Tao, Sha
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Comparison of CRC and KECCAK Based Message Authentication for Resource-Constrained Devices2018In: 2018 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018, IEEE , 2018, p. 217-220Conference paper (Refereed)
    Abstract [en]

    With the growth of Internet-of-Things (IoT), billions of low-end devices become connected to provide new services appealing to users. The value of the information to which these devices have access via network is increasing, too, making them an attractive target for cyberattacks. Low-end IoT devices typically have very limited computing, storage and energy resources. Therefore, it is not always possible to use conventional cryptographic algorithms for their protection. In this paper, we investigate whether a cryptographically secure Cyclic Redundancy Check (CRC)-based Message Authentication Code (CMAC) and a KEccAK-based Message Authentication Code (KMAC) satisfy limitations of resource-constrained IoT devices. We implement the 128-bits CMAC and the 128-bits KMAC in 65nm CMOS and compare their performance. To our best knowledge, no hardware implementations of CMAC and KMAC have been presented so far. Our evaluation shows that, for 1.2V operating voltage and clock frequencies above 1 MHz, the CMAC128 is at least 32 times more area-efficient and at least 21 times more power-efficient than the KMAC128.

1 - 31 of 31
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf