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  • 1.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Integrated Frequency Synthesis for Convergent Wireless Solutions2008Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Wireless transceivers combining several standards in one unit are of key importance. In order to reach the ultimate goal of maximizing the performance-to-cost ratio of such modules, a careful study of the target application, the architecture, and the frequency planning is strongly required. One of the most challenging tasks is the implementation of the frequency synthesizer. This challenge is compounded by the traditional technical difficulties in designing frequency synthesizers as well as the new requirements that include multi-standard support. As a result, studying the upper levels of the communication system becomes mandatory in order to frame the requirements of the frequency synthesizer and to provide a viable solution from a user’s perspective for an always-best-connected scenario. Additionally, the study of the upper layers opens up new opportunities for innovation at the lower layers, especially at the physical layer where the view is traditionally restricted by some harsh requirements whose source might not be clear at least for the physical-level designer. The first aim of this work is to provide a holistic view of how an optimum user experience can be achieved and how this affects the design of frequency synthesizers for the next generation networks. The work is heavily based on the existing garden of wireless standards although it can also serve for other applications such as real software-defined radios and dynamic spectrum allocation. As a result, this work cuts a vertical path starting from the best user experience vision down to the physical layer where it expands on the design of the frequency synthesizer. It proposes a wireless front-end solution that can make the vision of an always-best-connected scenario a reality. The architecture is based on a wireless detector called Sniffer that searches for an alternative connection while the main connection is running. Not only is the Sniffer solution viable at the physical level, but it also provides a stepping stone for development towards fully-enabled multi-standard transceivers. After this, and inline with the previous vision, some important frequency synthesizer parameters are pointed out and enhancements on the phase-locked architectures are presented. This includes ways to extend the range of the frequency synthesizer and ways to make the synthesizer adaptable depending on the requirements of the wireless standards. This work leads directly to the implementation of a multi-standard frequency synthesizer where the details of the top-down design procedure are presented at several levels of abstraction. In order to round-up the work, and due to the fact that the requirements of the frequency synthesizer stretch thin the capabilities of the technology used, calibration techniques to increase the yield of such a complicated sub-system are presented, an important step towards first-pass success.

  • 2.
    Atallah, Jad G.
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Elnaggar, Mohammed Ismail
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A CMOS frequency synthesizer for multi-standard wireless devices2003In: Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems: Vols 1-3 / [ed] Hamdy, N., NEW YORK: IEEE , 2003, p. 1138-1141Conference paper (Refereed)
    Abstract [en]

    This paper presents a CMOS frequency synthesizer for wireless transceivers that support several communication standards namely GSM, WCDMA, IEEE 802.11b, and Bluetooth. The architecture is based on a multi-stage phase-locked loop where each stage differs from the others in the parameters of its charge pump and loop filter. It is designed using mathematical models and refined through simulation using different software tools depending on the required perspective. The architecture and the components presented pave the way to provide a low cost, fully integrated implementation.

  • 3.
    Atallah, Jad G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elnaggar, Mohammed Ismail
    Ohio State University.
    Future 4G front-ends enabling smooth vertical handovers2006In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, no 1, p. 6-15Article in journal (Refereed)
    Abstract [en]

    An overview is given of the most important effects that handover considerations have on the design of multistandard mobile radio transceivers. Focus is on the multitude of design issues and challenges that should be taken into account in the RF/analog front-end part. Topics discussed include the convergence challenge, wireless transceiver design challenge, wireless standards, handover initiation, interworking between GSM and DECT, idle mode issues, possible issues when mobile terminals miss pages, procedure while in active communication in DECT mode, procedure while in active communication in GSM mode, and GSM/WLAN handover.

  • 4.
    Atallah, Jad G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Michielsen, Wim
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Elnaggar, Mohammed Ismail
    Firstpass Semiconductors AB.
    A frequency planning and generation scheme for multi-standard wireless transceivers2005In: 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005: Gammarth, 11 December 2005 through 14 December 2005, 2005Conference paper (Refereed)
    Abstract [en]

    This work presents a novel frequency planning scheme associated with a reference frequency generation scheme that has the potential of providing low phase noise contribution for several wireless standards including DCS1800, WCDMA II and III, DECT, WLAN a/b/g and Bluetooth. The scheme is particularly useful when implemented in future technologies and can be extended to cover newer wireless standards in newer bands of interest. It uses a single multi-band voltage-controlled oscillator (VCO) with switching inductors and high speed dividers directly generating the quadrature outputs. The VCO itself covers the frequency ranges from 4.8GHz to 6GHz and from 6.8GHz to 8GHz. Its phase noise is -136dBc/Hz at 1MHz offset from a center frequency of 1.85GHz. The design is sent for fabrication using 0.18ÎŒm CMOS.

  • 5.
    Atallah, Jad. G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A direct conversion WiMAX RF receiver front-end in CMOS technology2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 37-40Conference paper (Refereed)
    Abstract [en]

    This paper presents a direct conversion RF receiver front-end supporting the WiMAX standard. The front-end is implemented in 0.18um CMOS technology and designed using the ARCHER software. It shows how the design flow can be accelerated starting from the standard specifications and going down to schematics. All this is accompanied by test benches to extract the relevant metrics. This front-end provides a total gain of 31dB, a noise figure of 3.3dB, an IIP2 of 49.5dBm, and an IIP3 of -13.8dBm.

  • 6. Bahramirad, S.
    et al.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Albrecht, S.
    A low phase noise VCO for multi band wireless transceivers2007In: Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007, IEEE , 2007, p. 148-153Conference paper (Refereed)
    Abstract [en]

    this paper presents a CMOS voltage controlled oscillator for multi standard wireless transceivers. The VCO structure is based on All- PMOS LC oscillators. The frequency range extends from 1.7 GHz to 2.5 GH, and tuning between frequencies is done by means of capacitor banks and varactors.

  • 7. Dixon, A.
    et al.
    Ismail, M.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Digital self-aware charge pump calibration technique for frequency synthesizers2009In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, IEEE , 2009, p. 743-746Conference paper (Refereed)
    Abstract [en]

    As radio design complexity increases and features sizes decrease, more innovative solutions are explored to ensure analog circuit designs meet specifications. Digital calibration is an inexpensive and effective solution. A novel digital calibration technique to improve charge pump current mismatch in frequency synthesizers is presented. This method detect. The charge pump error by measurin. The low pass filter voltage oy the system forced to operate at a fixed phase error. A reference table developed from a mathematical model oy the system use. The measurement result to produce a digital control word. The digital control word acts on a charge pump array to correc. The error. The technique is implemented and tested in Matlab/Simulink for a case study frequency synthesizer. The calibration technique correct. The charge pump current absolute error to within 1.4% oy the nominal value. Additionally. The technique is exceptionally effective for correctin. The charge pump current mismatch to within 1%.

  • 8.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: an automated RF-IC Rx front-end circuit design tool2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 255-270Article in journal (Refereed)
    Abstract [en]

    This paper presents a tool capable of automatically compiling the circuit of a direct-conversion receiver at the schematics level based on system specifications that include the frequency of operation, gain, noise figure, IIP2 and IIP3 linearity. The front-end of a direct-conversion receiver is built using inductive source degeneration (LSD) LNA and double-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that automatically size the transistors, passive components, and find the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout. Case studies involving WiMAX, UMTS, GSM, Bluetooth and WLAN are presented to reveal the capabilities of the tool in reducing the design time.

  • 9.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: An automated RF-IC Rx front-end circuit design tool2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 129-132Conference paper (Refereed)
    Abstract [en]

    This paper presents a tool capable of compiling automatically the schematic circuit design of a direct conversion receiver based on system specifications including frequency of operation, gain, noise figured and 123 linearity. The rx front-end of a direct conversion receiver is built using inductive source degeneration (LSD) LNA and single-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that size automatically the transistors, passive components, and finds the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout.

  • 10.
    Sleiman, Sleiman Bou
    et al.
    Ohio State Univ, Analog VLSI Lab.
    Atallah, Jad G.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Optimal Sigma Delta Modulator Architectures for Fractional-N Frequency Synthesis2010In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 18, no 2, p. 194-200Article in journal (Refereed)
    Abstract [en]

    This paper presents a comparative study of Sigma Delta modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

  • 11.
    Sleiman, Sleiman Bou
    et al.
    Ohio State Univ, Analog VLSI Lab.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Wide-Division-Range High-Speed Fully Programmable Frequency Divider2008In: 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, NEW YORK: IEEE , 2008, p. 17-20Conference paper (Refereed)
    Abstract [en]

    This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mu m - and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.

  • 12.
    Zhao, Zongyang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Vertical handover for 4G multi-standard wireless transceivers2007In: 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS: VOLS 1-4, 2007, p. 1356-1359Conference paper (Refereed)
    Abstract [en]

    Future best-connected wireless solutions will involve a multitude of network standards between which the user can switch in order to optimize a set of benefits such as cost and performance. As a result of this convergence, the hardware design of the mobile device will require knowledge about the restrictions imposed by the upper networking layers. This paper starts by presenting the requirements for the connection initialization in the WLAN, WiMAX and 3G standards as they pertain to the mobile transceiver design. It is assumed that the mobile device is based on the dual front-end transceiver architecture where the primary transceiver handles the current network connection while the secondary transceiver (Sniffer) searches for an alternative connection. The paper also presents the handover procedures between these standards that will provide, among other things, the timing requirements for the circuit design.

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