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  • 1.
    Ekström, Mattias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    SiC CMOS and memory devices for high-temperature integrated circuits2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    High-temperature electronics find use in extreme environments, like data logging in downhole drilling for geothermal energy production, inside of high-temperature turbines, industrial gas sensors and space electronics. The simplest systems use a sensor and a transmitter, but more advance electronic systems would additionally require a microcontroller with memory. Silicon carbide (4H-SiC) integrated circuits target high-temperature electronics, although the current integration level is low due to immature process technology and non-volatile memory has not been demonstrated. SiC CMOS would allow highly dense integrated circuits for microcontrollers and random access memory (RAM). Ferroelectric capacitors could serve as high-temperature non-volatile memory devices.

    In this work, significant efforts have been taken to develop a SiC CMOS process and ferroelectric capacitors. SiC CMOS is challenging and mostly unexplored technology. A recessed channel transistor design was investigated. Several key challenges in the SiC CMOS process was identified, leading to a polyoxide-based field oxide, a deposited gate-dielectric process, reproducible Ni-Al semi-salicide contacts to p-type SiC, and a high-temperature CMP enabled two-level TiW-based metallisation. Self-aligned cobalt silicide contacts were investigated, and was found to produce low-resistance ohmic contactsto n-type SiC. Inverters and ring oscillators that operate at 200 °C were achieved in this recessed channel SiC CMOS process. It was found that steam-treating the gate oxide interface produced both NMOS and PMOS transistors that could be used for circuits. However, the reliability suffered due to poor PMOS performance. Wafer-level statistical measurements of interface trap density was performed on NMOS transistors treated by steam, dry oxygen and nitrided by nitrous oxide. A deposition and etch process for ferroelectric capacitors, using vanadium-doped bismuth titanate as ferroelectric material, was developed. High-temperature operation was demonstrated, and several scalability challenges for the etched process was identified.

    The implication of this thesis is that while operational recessed channel SiC CMOS was demonstrated at high temperature, more promising technologies like ion implanted bulk transistors should be investigated instead, due to the numerous difficulties in optimising both NMOS and PMOS with this recessed channel design. The presented recessed channel process technology can be used to fabricate short channel length NMOS-logic. Ferroelectric capacitors is a good candidate for high-temperature non-volatile memory applications, although more work is needed in the CMOS integration.

  • 2.
    Ekström, Mattias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Ferrario, Andrea
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide2019In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 48, no 4, p. 2509-2516Article in journal (Refereed)
    Abstract [en]

    Previous studies showed that cobalt silicide can form ohmic contacts to p-type 6H-SiC by directly reacting cobalt with 6H-SiC. Similar results can be achieved on 4H-SiC, given the similarities between the different silicon carbide polytypes. However, previous studies using multilayer deposition of silicon/cobalt on 4H-SiC gave ohmic contacts to n-type. In this study, we investigated the cobalt silicide/4H-SiC system to answer two research questions. Can cobalt contacts be self-aligned to contact holes to 4H-SiC? Are the self-aligned contacts ohmic to n-type, p-type, both or neither? Using x-ray diffraction, it was found that a mixture of silicides (Co2Si and CoSi) was reliably formed at 800°C using rapid thermal processing. The cobalt silicide mixture becomes ohmic to epitaxially grown n-type (1×1019cm-3) if annealed at 1000°C, while it shows rectifying properties to epitaxially grown p-type (1×1019cm-3) for all tested anneal temperatures in the range 800–1000°C. The specific contact resistivity (ρC) to n-type was 4.3×10-4 Ω cm2. This work opens the possibility to investigate other self-aligned contacts to silicon carbide.

  • 3.
    Ekström, Mattias
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hou, Shuoben
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, Vol. 924, p. 389-392Conference paper (Refereed)
    Abstract [en]

    Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

  • 4.
    Ekström, Mattias
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Khartsev, Sergiy
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Integration and High-Temperature Characterization of Ferroelectric Vanadium-Doped Bismuth Titanate Thin Films on Silicon Carbide2017In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 46, no 7, p. 4478-4484Article in journal (Refereed)
    Abstract [en]

    4H-SiC electronics can operate at high temperature (HT), e.g., 300A degrees C to 500A degrees C, for extended times. Systems using sensors and amplifiers that operate at HT would benefit from microcontrollers which can also operate at HT. Microcontrollers require nonvolatile memory (NVM) for computer programs. In this work, we demonstrate the possibility of integrating ferroelectric vanadium-doped bismuth titanate (BiTV) thin films on 4H-SiC for HT memory applications, with BiTV ferroelectric capacitors providing memory functionality. Film deposition was achieved by laser ablation on Pt (111)/TiO2/4H-SiC substrates, with magnetron-sputtered Pt used as bottom electrode and thermally evaporated Au as upper contacts. Film characterization by x-ray diffraction analysis revealed predominately (117) orientation. P-E hysteresis loops measured at room temperature showed maximum 2P (r) of 48 mu C/cm(2), large enough for wide read margins. P-E loops were measurable up to 450A degrees C, with losses limiting measurements above 450A degrees C. The phase-transition temperature was determined to be about 660A degrees C from the discontinuity in dielectric permittivity, close to what is achieved for ceramics. These BiTV ferroelectric capacitors demonstrate potential for use in HT NVM applications for SiC digital electronics.

  • 5.
    Ekström, Mattias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators2019In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 5, p. 670-673Article in journal (Refereed)
    Abstract [en]

    Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

  • 6.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A wafer-scale Ni-salicide contact technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. P197-P200Article in journal (Refereed)
    Abstract [en]

    A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

  • 7.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. 197-200Article in journal (Refereed)
    Abstract [en]

    A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.

1 - 7 of 7
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