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  • 1. Abadal, Sergi
    et al.
    Alarcon, Eduard
    Cabellos-Aparicio, Albert
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Nemirovsky, Mario
    Graphene-Enabled Wireless Communication for Massive Multicore Architectures2013In: IEEE Communications Magazine, ISSN 0163-6804, E-ISSN 1558-1896, Vol. 51, no 11, 137-143 p.Article in journal (Refereed)
    Abstract [en]

    Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main bottleneck is foreseen to migrate from computation to communication, efficient and scalable means of inter-core communication are crucial for guaranteeing steady performance improvements in many-core processors. As the number of cores grows, it remains unclear whether initial proposals, such as the Network-on-Chip (NoC) paradigm, will meet the stringent requirements of this scenario. This position paper presents a new research area where massive multicore architectures have wireless communication capabilities at the core level. This goal is feasible by using graphene-based planar antennas, which can radiate signals at the Terahertz band while utilizing lower chip area than its metallic counterparts. To the best of our knowledge, this is the first work that discusses the utilization of graphene-enabled wireless communication for massive multicore processors. Such wireless systems enable broadcasting, multicasting, all-to-all communication, as well as significantly reduce many of the issues present in massively multicore environments, such as data coherency, consistency, synchronization and communication problems. Several open research challenges are pointed out related to implementation, communications and multicore architectures, which pave the way for future research in this multidisciplinary area.

  • 2. Abermann, S.
    et al.
    Efavi, J. K.
    Sjoblom, G.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Olsson, J.
    Bertagnolli, E.
    Processing and evaluation of metal gate/high-kappa/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-kappa dielectric2007In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 84, no 5-8, 1635-1638 p.Article in journal (Refereed)
    Abstract [en]

    We evaluate various metal gate/high-K/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.

  • 3. Abermann, S.
    et al.
    Efavi, J.
    Sjoblom, G.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Olsson, J.
    Bertagnolli, E.
    Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown HfO2 and ZrO2 high-k dielectrics2007In: Microelectronics and reliability, ISSN 0026-2714, E-ISSN 1872-941X, Vol. 47, no 4-5, 536-539 p.Article in journal (Refereed)
    Abstract [en]

    In this work we compare the impacts of nickel (Ni), titanium-nitride (TiN), molybdenum (Mo), and aluminium (Al), gates on MOS capacitors incorporating HfO2- or ZrO2-dielectrics. The primary focus lies on interface trapping, oxide charging, and thermodynamical stability during different annealing steps of these gate stacks. Whereas Ni, Mo, and especially TIN are investigated as most promising candidates for future CMOS devices, Al acted as reference gate material to benchmark the parameters. Post-metallization annealing of both, TiN- and Mo-stacks, resulted in very promising electrical characteristics. However, gate stacks annealed at temperatures of 800 degrees C or 950 degrees C show thermodynamic instability and related undesirable high leakage currents.

  • 4. Abermann, S.
    et al.
    Sjoblom, G.
    Efavi, J.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Olsson, J.
    Bertagnolli, E.
    Comparative study on the impact of TiN and Mo metal gates on MOCVD-grown HfO2 and ZrO2 high-kappa dielectrics for CMOS technology2007In: Physics of Semiconductors, Pts A and B, 2007, 293-294 p.Conference paper (Refereed)
    Abstract [en]

    We compare metal oxide semiconductor capacitors, investigating Titanium-Nitride and Molybdenum as gate materials, as well as metal organic chemical vapor deposited ZrO2 and HfO2 as high-kappa dielectrics, respectively. The impact of different annealing steps on the electrical characteristics of the various gate stacks is a further issue. The positive effect of post metallization annealing in forming gas atmosphere as well as observed mid-gap pinning of TiN and Mo metal gates is presented.

  • 5. Balestra, F.
    et al.
    Parker, E.
    Leadley, D.
    Mantl, S.
    Dubois, E.
    Engstrom, O.
    Clerc, R.
    Cristoloveanu, S.
    Kurz, H.
    Raskin, J. P.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Ionescu, A.
    Moselund, K. E.
    Boucart, K.
    Kasper, E.
    Karmous, A.
    Baus, M.
    Spangenberg, B.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Sangiorgi, E.
    Ghibaudo, G.
    Flandre, D.
    NANOSIL network of excellence-silicon-based nanostructures and nanodevices for long-term nanoelectronics applications2008In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 11, no 5-6, 148-159 p.Article in journal (Refereed)
    Abstract [en]

    NANOSIL Network of Excellence [NANOSIL NoE web site < www.nanosil-noe.eu >], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed-with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades.

  • 6. Baus, M
    et al.
    Ali, M Z
    Winkler, O
    Spangenberg, B
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H
    Monolithic Bidirectional Switch (MBS) - A novel MOS-based power device2005In: PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, 473-476 p.Conference paper (Refereed)
    Abstract [en]

    A novel MOS-based power device, the Monolithic Bidirectional Switch (MBS), is investigated in this work. An analytical model is used to explain basic device operating principles. A self-aligned fabrication process of lateral MBS devices with Schottky contacts and local oxidation of silicon technique (LOCOS) is described. Experimental results are compared with the analytical model to analyze the influence of device parasitics. Bidirectional switching and an on/off-current ratio of more than 100 is demonstrated for MBS devices for the first time.

  • 7. Baus, M.
    et al.
    Echtermeyer, T. J.
    Szafranek, B. N.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Device architectures based on graphene channels2008In: 2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, NEW YORK: IEEE , 2008, 269-272 p.Conference paper (Refereed)
    Abstract [en]

    Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.

  • 8. Baus, M
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Chmielus, S
    Sittig, R
    Spangenberg, B
    Kurz, H
    Fabrication of monolithic bidirectional switch devices2004In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 73-4, 463-467 p.Article in journal (Refereed)
    Abstract [en]

    The fabrication scheme of a novel MOS-based power device, a monolithic bidirectional switch (MBS), is presented. This concept allows the integration of a bidirectional switch with the advantages of low power consumption, small package size, and low fabrication costs. Furthermore, device simulations predict a performance benefit for power applications such as matrix converters. In an MBS, the field effect is used to control carrier concentrations in elevated structures made up of nearly intrinsic silicon. A CMOS-compatible nano-fabrication process for the MBS is proposed, employing local oxidation of silicon for self-aligned contact formation. First electrical results are presented. (C) 2004 Elsevier B.V. All rights reserved.

  • 9. Baus, M.
    et al.
    Szafranek, B. N.
    Chmielus, St.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Hadam, B.
    Spangenberg, B.
    Sittig, R.
    Kurz, H.
    Fabrication of monolithic bidirectional switch (MBS) devices with MOS-controlled emitter structures2006In: PROCEEDINGS OF THE 18TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS, 2006, 181-184 p.Conference paper (Refereed)
    Abstract [en]

    A novel high-voltage power device, the Monolithic Bidirectional Switch (MBS) is investigated in this work. Planar MBS devices have been fabricated by a self-aligned fabrication process using local oxidation of silicon technique and self-aligned sificidation. Results obtained from electrical characterization are compared with numerical simulations. Using highly transparent universal contacts, bidirectional switching with an excellent on/off current ratio is demonstrated. On-current densities of 75 A/cm(2) at V(on) = 3 V have been achieved even in an exploratory device structure. Simulations further demonstrate the high potential of the MBS for future power electronic systems such as the matrix converter.

  • 10. Bell, D. C.
    et al.
    Lemme, Max C.
    Harvard University, Department of Physics.
    Stern, L. A.
    RWilliams, J.
    Marcus, C. M.
    Precision cutting and patterning of graphene with helium ions2009In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 20, no 45, 455301- p.Article in journal (Refereed)
    Abstract [en]

    We report nanoscale patterning of graphene using a helium ion microscope configured for lithography. Helium ion lithography is a direct-write lithography process, comparable to conventional focused ion beam patterning, with no resist or other material contacting the sample surface. In the present application, graphene samples on Si/SiO(2) substrates are cut using helium ions, with computer controlled alignment, patterning, and exposure. Once suitable beam doses are determined, sharp edge profiles and clean etching are obtained, with little evident damage or doping to the sample. This technique provides fast lithography compatible with graphene, with similar to 15 nm feature sizes.

  • 11. Bell, David C.
    et al.
    Lemme, Max C.
    Harvard University, Department of Physics.
    Stern, Lewis A.
    Marcus, Charles M.
    Precision material modification and patterning with He ions2009In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 27, no 6, 2755-2758 p.Article in journal (Refereed)
    Abstract [en]

    The authors report on the use of a helium ion microscope as a potential technique for precise nanopatterning. Combined with an automated pattern generation system, they demonstrate controlled etching and patterning of materials, giving precise command over the geometery of the modified nanostructure. After the determination of suitable doses, sharp edge profiles and clean etching of areas in materials were observed. In this article they present examples of patterning on SiO(2) and graphene, which is particularly relevant. This technique could be an avenue for precise material modification for future graphene based device fabrication. The technique has the potential to revolutionize the way that very thin, one-atomic layer materials are modified in a controlled and predictable way.

  • 12. Benetti, M.
    et al.
    Cannata, D.
    Di Pietrantonio, F.
    Verona, E.
    Di Natale, C.
    D'Amico, A.
    Paletti, S.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Tibuzzi, A.
    Margesin, B.
    Soncini, G.
    Betta, G. F. Dalla
    POLYSILICON MESOSCOPIC WIRES COATED BY Pd AS H(2) SENSORS2009In: PROCEEDINGS OF THE 13TH ITALIAN CONFERENCE ON SENSORS AND MICROSYSTEMS, SINGAPORE: WORLD SCIENTIFIC PUBL CO PTE LTD , 2009, 161-165 p.Conference paper (Refereed)
    Abstract [en]

    In this work a novel monocrystalline silicon nanowires array has been investigated and presented as hydrogen sensor, designed and fabricated by employing high resolution microfabrication techniques and featuring a high surface/volume ratio. The nanowires arrays makes up the channel of a MOS system, palladium-silicon dioxide-silicon. Several devices have been fabricated by using a SOI (Silicon On Insulator) substrate, Source and Drain have been geometrically patterned by optical lithography and Boron p-doped. Electron Beam Litography (EBL) defined the MOS channel made up of a nanowires array of different length and width in different transistors. The pads of Source and Drain have been manufactured with an aluminium film deposition. The Gate has been fabricated with a grown silicon oxide layer (17.4 nm) and Palladium has been used as gate contact. Polarizing and exposing the device to H(2)/N(2) cycles at different concentrations some preliminary measurements have been successfully conducted.

  • 13. Buiu, O.
    et al.
    Hall, S.
    Engstrom, O.
    Raeissi, B.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Hurley, P. K.
    Cherkaoui, K.
    Extracting the relative dielectric constant for "high-k layers" from CV measurements: Errors and error propagation2007In: Microelectronics and reliability, ISSN 0026-2714, E-ISSN 1872-941X, Vol. 47, no 4-5, 678-681 p.Article in journal (Refereed)
    Abstract [en]

    The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., kappa value) from capacitance-voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-rc dielectric and the silicon substrate is a factor that affects - in general - the assessment of the electrical data, as well as the extraction of rc. A methodology which accounts for this transition layer and the errors related to other parameters involved in the k value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO2/SiOx/Si structures produced in different conditions.

  • 14. Czernohorsky, M.
    et al.
    Tetzlaff, D.
    Bugiel, E.
    Dargis, R.
    Osten, H. J.
    Gottlob, H. D. B.
    Schmidt, M.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Stability of crystalline Gd(2)O(3) thin films on silicon during rapid thermal annealing2008In: Semiconductor Science and Technology, ISSN 0268-1242, E-ISSN 1361-6641, Vol. 23, no 3, 035010- p.Article in journal (Refereed)
    Abstract [en]

    We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd(2)O(3) layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack ( silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 degrees C anneal.

  • 15. Del, Sepideh Khandan
    et al.
    Bornemann, Rainer
    Bablich, Andreas
    Schaefer-Eberwein, Heiko
    Li, Jiantong
    Kowald, Torsten
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bolivar, Peter Haring
    Lemme, Max C.
    University of Siegen, Germany.
    Optimizing the optical and electrical properties of graphene ink thin films by laser-annealing2015In: 2D Materials, ISSN 2053-1583, Vol. 2, no 1, 011003Article in journal (Refereed)
    Abstract [en]

    We demonstrate a facile fabrication technique for graphene-based transparent conductive films. Highly flat and uniform graphene films are obtained through the incorporation of an efficient laser annealing technique with one-time drop casting of high-concentration graphene ink. The resulting thin films are uniform and exhibit a transparency of more than 85% at 550 nm and a sheet resistance of about 30 k Omega/square. These values constitute an increase of 45% in transparency, a reduction of surface roughness by a factor of four and a decrease of 70% in sheet resistance compared to un-annealed films.

  • 16. Driussi, F.
    et al.
    Esseni, D.
    Selmi, L.
    Schmidt, M.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Buca, D.
    Mantl, S.
    Luysberg, M.
    Loo, R.
    Nguyen, D.
    Reiche, M.
    Fabrication, characterization and modeling of strained SOI MOSFETs with very large effective mobility2007In: ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, 315-318 p.Conference paper (Refereed)
    Abstract [en]

    Strained Silicon on insulators (sSOI) wafers with a supercritical thickness of 58 nm were produced using thin strain relaxed SiGe buffer layers, wafer bonding, selective etch back and epitaxial overgrowth. Raman spectroscopy revealed an homogeneous strain of 0.63 +/- 0.03% in the strained Si layer. Long channel n-type SOI-MOSFETs showed very large electron mobilities up to 1200 cm(2)/Vs in the strained Si devices. These values are more than two times larger than those of reference SOI n-MOSFETs. Mobility simulations with state of the art scattering models are then used to interpret the experiments.

  • 17. Echtermeyer, T.
    et al.
    Gottlob, H. D. B.
    Wahlbrink, T.
    Mollenhauer, T.
    Schmidt, M.
    Efavi, J. K.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes2007In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 51, no 4, 617-621 p.Article in journal (Refereed)
    Abstract [en]

    Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.

  • 18. Echtermeyer, T. J.
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Bolten, J.
    Baus, M.
    Ramsteiner, M.
    Kurz, H.
    Graphene field-effect devices2007In: The European Physical Journal Special Topics, ISSN 1951-6355, E-ISSN 1951-6401, Vol. 148, no 1, 19-26 p.Article in journal (Refereed)
    Abstract [en]

    In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices ( FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors ( MOSFETs).

  • 19. Echtermeyer, Tim J.
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Baus, Matthias
    Szafranek, Bartholomaeus N.
    Geim, Andre K.
    Kurz, Heinrich
    Nonvolatile switching in graphene field-effect devices2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 8, 952-954 p.Article in journal (Refereed)
    Abstract [en]

    The absence of a band gap in graphene restricts its straightforward application as a channel material in field-effect transistors. In this letter, we report on a new approach to engineer a band gap in graphene field-effect devices (FEDs) by controlled structural modification of the graphene channel itself. The conductance in the FEDs is switched between a conductive "ON-state" and an insulating "OFF-state" with more than six orders of magnitude difference in conductance. Above a critical value of an electric field applied to the FED gate under certain environmental conditions, a chemical modification takes place to form insulating graphene derivatives. The effect can be reversed by electrical fields of opposite polarity or short current pulses to recover the initial state. These reversible switches could potentially be applied to nonvolatile memories and novel neuromorphic processing concepts.

  • 20. Efavi, J K
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T
    Wahlbrink, T
    Bobek, T
    Wang, D
    Gottlob, H D B
    Kurz, H
    Investigation of NiAlN as gate-material for submicron CMOS technology2004In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 76, no 1-4, 354-359 p.Article in journal (Refereed)
    Abstract [en]

    Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.

  • 21. Efavi, J K
    et al.
    Mollenhauer, T
    Wahlbrink, T
    Gottlob, H D B
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H
    Tungsten work function engineering for dual metal gate nano-CMOS2005In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 16, no 7, 433-436 p.Article in journal (Refereed)
    Abstract [en]

    A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.

  • 22. Engstrom, O.
    et al.
    Raeissi, B.
    Hall, S.
    Buiu, O.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Gottlob, H. D. B.
    Hurley, P. K.
    Cherkaoui, K.
    Navigation aids in the search for future high-k dielectrics: Physical and electrical trends2007In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 51, no 4, 622-626 p.Article in journal (Refereed)
    Abstract [en]

    From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.

  • 23.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. KTH Royal Institute of Technology.
    Elgammal, Karim
    KTH, Centres, SeRC - Swedish e-Science Research Centre. KTH, School of Engineering Sciences (SCI), Applied Physics.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Delin, Anna
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering. KTH, Centres, SeRC - Swedish e-Science Research Centre. Department of Physics and Astronomy, Materials Theory Division, Uppsala University, Box 516, SE-75120 Uppsala, Sweden.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. Department of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. KTH Royal Institute of Technology.
    Humidity and CO2 gas sensing properties of double-layer graphene2018In: Carbon, ISSN 0008-6223, E-ISSN 1873-3891, Vol. 127, 576-587 p.Article in journal (Refereed)
    Abstract [en]

    Graphene has interesting gas sensing properties with strong responses of the graphene resistance when exposed to gases. However, the resistance response of double-layer graphene when exposed to humidity and gasses has not yet been characterized and understood. In this paper we study the resistance response of double-layer graphene when exposed to humidity and CO2, respectively. The measured response and recovery times of the graphene resistance to humidity are on the order of several hundred milliseconds. For relative humidity levels of less than ~ 3% RH, the resistance of double-layer graphene is not significantly influenced by the humidity variation. We use such a low humidity atmosphere to investigate the resistance response of double-layer graphene that is exposed to pure CO2 gas, showing a consistent response and recovery behaviour. The resistance of the double-layer graphene decreases linearly with increase of the concentration of pure CO2 gas. Density functional theory simulations indicate that double-layer graphene has a weaker gas response compared to single-layer graphene, which is in agreement with our experimental data. Our investigations contribute to improved understanding of the humidity and CO2 gas sensing properties of double-layer graphene which is important for realizing viable graphene-based gas sensors in the future.

  • 24. Fuchs, A.
    et al.
    Bender, M.
    Plachetka, U.
    Kock, L.
    Wahlbrink, T.
    Gottlob, H. D. B.
    Efavi, J. K.
    Moeller, M.
    Schmidt, M.
    Mollenhauer, T.
    Moormann, C.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Nanowire fin field effect transistors via UV-based nanoimprint lithography2006In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 24, no 6, 2964-2967 p.Article in journal (Refereed)
    Abstract [en]

    A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20 nm (3 sigma). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.

  • 25. Geringer, V.
    et al.
    Liebmann, M.
    Echtermeyer, T.
    Runte, S.
    Schmidt, M.
    Rueckamp, R.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Morgenstern, M.
    Intrinsic and extrinsic corrugation of monolayer graphene deposited on SiO(2)2009In: Physical Review Letters, ISSN 0031-9007, E-ISSN 1079-7114, Vol. 102, no 7, 076102- p.Article in journal (Refereed)
    Abstract [en]

    Using scanning tunneling microscopy in an ultrahigh vacuum and atomic force microscopy, we investigate the corrugation of graphene flakes deposited by exfoliation on a Si/SiO(2) (300 nm) surface. While the corrugation on SiO(2) is long range with a correlation length of about 25 nm, some of the graphene monolayers exhibit an additional corrugation with a preferential wavelength of about 15 nm. A detailed analysis shows that the long-range corrugation of the substrate is also visible on graphene, but with a reduced amplitude, leading to the conclusion that the graphene is partly freely suspended between hills of the substrate. Thus, the intrinsic rippling observed previously on artificially suspended graphene can exist as well, if graphene is deposited on SiO(2).

  • 26. Gomeniuk, Y.
    et al.
    Nazarov, A.
    Vovk, Ya.
    Lu, Yi
    Buiu, O.
    Hall, S.
    Efavi, J. K.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Low-temperature conductance measurements of surface states in HfO2-Si structures with different gate materials2006In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 9, no 6, 980-984 p.Article in journal (Refereed)
    Abstract [en]

    Metal-oxide-semiconductor capacitors based on HfO2 gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator-semiconductor interface. C-V and G-omega measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180-300 K. From the maximum of the plot G/omega vs. ln(omega) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge. The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2 x 10(11) cm(-2)eV(-1) for Al and up to (3.5-5.5) x 10(12)cm(-2)eV(-1) for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8 x 10(-17)cm(2) at 200 K for Al-HfO2-Si structure.

  • 27. Gottlob, H. D. B.
    et al.
    Echtermeyer, T. J.
    Schmidt, M.
    Mollenhauer, T.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Leakage current mechanisms in epitaxial Gd(2)O(3) high-k gate dielectrics2008In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775, Vol. 11, no 3, G12-G14 p.Article in journal (Refereed)
    Abstract [en]

    We report on leakage current mechanisms in epitaxial gadolinium oxide (Gd(2)O(3)) high-k gate dielectrics suitable for low standby power logic applications. The investigated p-type metal-oxide-semi con doctor capacitors are gated with complementary-metal-oxide-semiconductor-compatible fully silicided nickel silicide electrodes. The Gd(2)O(3) thickness is 5.9 nm corresponding to a capacitance equivalent oxide thickness of 1.8 nm. Poole-Frenkel conduction is identified as the main leakage mechanism with the high-frequency permittivity describing the dielectric response on the carriers. A trap level of Phi(T) = 1.2 eV is extracted. The resulting band diagram strongly suggests hole conduction to be dominant over electron conduction.

  • 28. Gottlob, H. D. B.
    et al.
    Echtermeyer, T.
    Mollenhauer, T.
    Efavi, J. K.
    Schmidt, M.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Investigation of high-K gate stacks with epitaxial Gd(2)O(3) and FUSINiSi metal gates down to CET=0.86 nm2006In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 9, no 6, 904-908 p.Article in journal (Refereed)
    Abstract [en]

    Novel gate stacks with epitaxial gadoliniurn oxide (Gd(2)O(3)) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10(-7) A cm(-2) are observed at a capacitance equivalent oxide thickness of CET = 1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd(2)O(3) thickness of 3.1 nm yield current densities down to 0.5 A cm(-2) at V(g) = + 1 V. The extracted dielectric constant for these gate stacks ranges from k = 13 to 14. These results emphasize the potential of NiSi/Gd(2)O(3) gate stacks for future material-based scaling of CMOS technology.

  • 29. Gottlob, H. D. B.
    et al.
    Echtermeyer, T.
    Mollenhauer, T.
    Efavi, J. K.
    Schmidt, M.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Czernohorsky, M.
    Bugiel, E.
    Osten, H. -J
    Fissel, A.
    CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics2006In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 50, no 6, 979-985 p.Article in journal (Refereed)
    Abstract [en]

    Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.

  • 30. Gottlob, H. D. B.
    et al.
    Echtermeyer, T.
    Mollenhauer, T.
    Schmidt, M.
    Efavi, J. K.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Endres, R.
    Stefanov, Y.
    Schwalke, U.
    Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics2006In: ESSDERC 2006: Proceedings of the 36th European Solid-State Device Research Conference, 2006, 150-153 p.Conference paper (Refereed)
    Abstract [en]

    Two process concepts for integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd2O3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.

  • 31. Gottlob, H. D. B.
    et al.
    Echtermeyer, T.
    Schmidt, M.
    Mollenhauer, T.
    Efavi, J. K.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Czernohorsky, M.
    Bugiel, E.
    Fissel, A.
    Osten, H. J.
    Kurz, H.
    0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes2006In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 10, 814-816 p.Article in journal (Refereed)
    Abstract [en]

    In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.

  • 32. Gottlob, H D B
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T
    Wahlbrink, T
    Efavi, J K
    Kurz, H
    Stefanov, Y
    Haberle, K
    Komaragiri, R
    Ruland, T
    Zaunert, F
    Schwalke, U
    Introduction of crystalline high-k gate dielectrics in a CMOS process2005In: Journal of Non-Crystalline Solids, ISSN 0022-3093, E-ISSN 1873-4812, Vol. 351, no 21-23, 1885-1889 p.Article in journal (Refereed)
    Abstract [en]

    In this work we report on methods to introduce crystalline rare-earth (RE) oxides with high (k > 3.9) dielectric constants (high-k) in a CMOS process flow. Key process steps compatible with crystalline praseodymium oxide (Pr2O3) high-k gate dielectric have been developed and evaluated in metal-oxide-semiconductor (MOS) structures and n-MOS transistors fabricated in an adapted conventional bulk process. From capacitance-voltage measurements a dielectric constant of k = 36 has been calculated. Furthermore an alternative process sequence suitable for the introduction of high-k material into silicon on insulator (SOI) MOS-field-effect-transistors (MOSFET) is presented. The feasibility of this process is shown by realization of n- and p-MOSFETs with standard SiO2 gate dielectric as demonstrator. SiO2 gate dielectric can be replaced by crystalline RE-oxides in the next batch fabrication.

  • 33. Gottlob, H. D. B.
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Schmidt, M.
    Echtermeyer, T. J.
    Mollenhauer, T.
    Kurz, H.
    Cherkaoui, K.
    Hurley, P. K.
    Newcomb, S. B.
    Gentle FUSI NiSi metal gate process for high-k dielectric screening2008In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 85, no 10, 2019-2021 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).

  • 34. Gottlob, H D B
    et al.
    Mollenhauer, T
    Wahlbrink, T
    Schmidt, M
    Echtermeyer, T
    Efavi, J K
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H
    Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics2006In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 24, no 2, 710-714 p.Article in journal (Refereed)
    Abstract [en]

    A "gate first" silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10 mu m down to 40 nm on a fully depleted 25 nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100 nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxial high-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.

  • 35. Gottlob, H. D. B.
    et al.
    Schmidt, M.
    Stefani, A.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Mitrovic, I. Z.
    Davey, W. M.
    Hall, S.
    Werner, M.
    Chalker, P. R.
    Cherkaoui, K.
    Hurley, P. K.
    Piscator, J.
    Engström, O.
    Newcomb, S. B.
    Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics2009In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 86, no 7-9, 1642-1645 p.Article in journal (Refereed)
    Abstract [en]

    We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd(2)O(3)) from a silicon oxide (SiO(2)) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).

  • 36. Gottlob, H. D. B.
    et al.
    Stefani, A.
    Schmidt, M.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Mitrovic, I. Z.
    Werner, M.
    Davey, W. M.
    Hall, S.
    Chalker, P. R.
    Cherkaoui, K.
    Hurley, P. K.
    Piscator, J.
    Engström, O.
    Newcomb, S. B.
    Gd silicate: A high-k dielectric compatible with high temperature annealing2009In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 27, no 1, 249-252 p.Article in journal (Refereed)
    Abstract [en]

    The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.

  • 37. Henschel, W
    et al.
    Wahlbrink, T
    Geogriev, Y M
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T
    Vratzov, B
    Fuchs, A
    Kurz, H
    Fabrication of 12 nm electrically variable shallow junction metal-oxide-semiconductor field effect transistors on silicon on insulator substrates2003In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 21, no 6, 2975-2979 p.Article in journal (Refereed)
    Abstract [en]

    Electrically variable shallow junction metal-oxide-semiconductor field effect transistors on silicon on insulator have been fabricated to evaluate the suitability of fabrication processes on a nanoscale. In addition, the limits of scalability have been explored reducing gate lengths down to 12 nm. Specific attention has been paid to the overlay accuracy as required for the fabrication of these double gate structures. The superior quality of hydrogen silsesquioxane (HSQ) as electron beam resist and as mask material is demonstrated. The transistor fabricated exhibits extremely low leakage currents and relatively high on currents. The 8 orders of magnitude difference between the on and off states demonstrates conclusively large potentials for metal-oxide-semiconductor structures with critical dimensions in the 10 nm regime. (C) 2003 American Vacuum Society.

  • 38. Henschel, W
    et al.
    Wahlbrink, T
    Georgiev, Y M
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T
    Vratzov, B
    Fuchs, A
    Kurz, H
    Kittler, M
    Schwierz, F
    Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 5, 739-745 p.Article in journal (Refereed)
    Abstract [en]

    A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This kind of transistor allows testing the limits of scalability at relaxed process requirements. Transistor gate lengths down to 12 run have been structured by electron beam lithography (EBL) and specific etching processes. The coupling of the upper gate to the inner transistor is carefully investigated.

  • 39. Heuser, M
    et al.
    Baus, M
    Hadam, B
    Winkler, O
    Spangenberg, B
    Granzner, R
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H
    Fabrication of wire-MOSFETs on silicon-on-insulator substrate2002In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 61-2, 613-618 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly. (C) 2002 Elsevier Science B.V. All rights reserved.

  • 40. Hurley, P. K.
    et al.
    Cherkaoui, K.
    O'Connor, E.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Gottlob, H. D. B.
    Schmidt, M.
    Hall, S.
    Lu, Y.
    Buiu, O.
    Raeissi, B.
    Piscator, J.
    Engstrom, O.
    Newcomb, S. B.
    Interface defects in HfO2, LaSiOx, and Gd2O3 high-k/metal-gate structures on silicon2008In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 155, no 2, G13-G20 p.Article in journal (Refereed)
    Abstract [en]

    In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.

  • 41.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Department of Electrical Engineering and Computer Science Technology, University of Siegen, Siegen, Germany.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Design exploration of graphene-FET based ring-oscillator circuits: A test-bench for large-signal compact models2015In: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Communications Society, 2015, 2716-2719 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a design-oriented characterization of ring-oscillator (RO) circuits based on complementary-inverters (INVs) implemented with graphene-FET (GFET) devices. A large-signal GFET compact model based on drift-diffusion transport is benchmarked at the circuit level against a second GFET compact model based on virtual source. Transient-based simulations of a 3-cell RO yield performance metrics in terms of operating frequency and voltage dynamic range. Against these metrics, a comprehensive design space exploration covering as input design variables parameters as GFET gate-oxide thickness tOX and channel-length L is presented. Methodologically, the work presents a general-purpose design framework, illustrated for ROs, which establishes a vertical circuit-device co-design environment. Its double-fold outcome is to provide guidelines both to bottom-up dimension and size the circuit, as well as top-down refine GFET device models and in turn GFET technology.

  • 42. Kataria, S.
    et al.
    Wagner, S.
    Ruhkopf, J.
    Gahoi, A.
    Pandey, H.
    Bornemann, R.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    Univ Siegen, Germany.
    Chemical vapor deposited graphene: From synthesis to applications2014In: Physica Status Solidi (a) applications and materials science, ISSN 1862-6300, E-ISSN 1862-6319, Vol. 211, no 11, 2439-2449 p.Article, review/survey (Refereed)
    Abstract [en]

    Graphene is a material with enormous potential for numerous applications. Therefore, significant efforts are dedicated to large-scale graphene production using a chemical vapor deposition (CVD) technique. In addition, research is directed at developing methods to incorporate graphene in established production technologies and process flows. In this paper, we present a brief review of available CVD methods for graphene synthesis. We also discuss scalable methods to transfer graphene onto desired substrates. Finally, we discuss potential applications that would benefit from a fully scaled, semiconductor technology compatible production process.

  • 43. Kuepper, David
    et al.
    Kuepper, Daniel
    Wahlbrink, Thorsten
    Bolten, Jens
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Georgiev, Yordan M.
    Kurz, Heinrich
    Megasonic-assisted development of nanostructures2006In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 24, no 4, 1827-1832 p.Article in journal (Refereed)
    Abstract [en]

    The effect of high frequency (1 MHz) acoustic agitation (megasonic agitation) on development of electron beam exposed poly(methylmethacrylate) (PMMA) nanostructures is investigated. Test patterns consisting of dense holes, isolated lines, and gratings with high aspect ratios have been used. Compared to conventional dip development, the sensitivity of the development process is increased and the homogeneity of nanopatterns is improved considerably. Furthermore, experiments towards ultimate aspect ratios and resolution of PMMA in the range of 2 - 3 ran with megasonically assisted development have been carried out. The physical mechanisms for the observed enhanced development performance which is particularly attractive for nanostructuring are discussed. (c) 2006 American Vacuum Society.

  • 44. Kupper, D
    et al.
    Wahlbrink, T
    Henschel, W
    Bolten, J
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Georgiev, Y M
    Kurz, H
    Impact of supercritical CO(2) drying on roughness of hydrogen silsesquioxane e-beam resist2006In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 24, no 2, 570-574 p.Article in journal (Refereed)
    Abstract [en]

    Surface roughness (SR) and, especially, the closely related line-edge roughness (LER) of nanostructures are important issues in advanced lithography. In this study, the origin of surface roughness in the negative tone electron resist hydrogen silsesquioxane is shown to be associated with polymer aggregate extraction not only during resist development but also during resist drying. In addition, the impact of exposure dose and resist development time on SR is clarified. Possibilities to reduce SR and LER of nanostructures by optimizing resist rinsing and drying are evaluated. A process of supercritical CO(2) resist drying that delivers remarkable reduction of roughness is presented. (c) 2006 American Vacuum Society.

  • 45.
    Lemme, Max C.
    Harvard University, Department of Physics.
    Current Status of Graphene Transistors2009In: Solid State Phenomena, ISSN 1012-0394, E-ISSN 1662-9779, Vol. 156, 499-509 p.Article in journal (Refereed)
    Abstract [en]

    This paper reviews the current status of graphene transistors as potential supplement to silicon CMOS technology. A short overview of graphene manufacturing and metrology methods is followed by an introduction of macroscopic graphene field effect transistors (FETs). The absence of an energy band gap is shown to result in severe shortcomings for logic applications. Possibilities to engineer a band gap in graphene FETs including quantum confinement in graphene Nanoribbons (GNRs) and electrically or substrate induced asymmetry in double and multi layer graphene are discussed. Novel switching mechanisms in graphene transistors are briefly introduced that could lead to future memory devices. Finally, graphene FETs are shown to be of interest for analog radio frequency applications.

  • 46.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Graphene for microelectronics: Can it make a difference?2012In: 2012 Proceedings of the ESSCIRC (ESSCIRC), IEEE , 2012, 25-27 p.Conference paper (Refereed)
    Abstract [en]

    Benchmarking figures for graphene show remarkable properties like ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs [1, 2]. When graphene is integrated and processed, however, defects in the graphene and its dielectric environment dominate device performance [3, 4]. Furthermore, the lack of a band gap limits the applicability of graphene field effect transistors (GFETs) for logic applications. Yet, there are many options for graphene to make a difference in the future of microelectronics, many of which can be attributed to the More than Moore domain defined in the ITRS. These will be discussed in this talk.

  • 47.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Graphene for microelectronics: Can it make a difference?2012In: Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European, IEEE conference proceedings, 2012, 25-27 p.Conference paper (Refereed)
    Abstract [en]

    Benchmarking figures for graphene show remarkable properties like ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs [1, 2]. When graphene is integrated and processed, however, defects in the graphene and its dielectric environment dominate device performance [3, 4]. Furthermore, the lack of a band gap limits the applicability of graphene field effect transistors (GFETs) for logic applications. Yet, there are many options for graphene to make a difference in the future of microelectronics, many of which can be attributed to the More than Moore domain defined in the ITRS. These will be discussed in this talk.

  • 48.
    Lemme, Max C.
    et al.
    Harvard University, Department of Physics.
    Bell, David C.
    Williams, James R.
    Stern, Lewis A.
    Baugher, Britton W. H.
    Jarillo-Herrero, Pablo
    Marcus, Charles M.
    Etching of Graphene Devices with a Helium Ion Beam2009In: ACS Nano, ISSN 1936-0851, E-ISSN 1936-086X, Vol. 3, no 9, 2674-2676 p.Article in journal (Refereed)
    Abstract [en]

    We report on the etching of graphene devices with a helium ion beam, including in situ electrical measurement during lithography. The etching process can be used to nanostructure and electrically isolate different regions In a graphene device, as demonstrated by etching a channel in a suspended graphene device with etched gaps down to about 10 nm. Graphene devices on silicon dioxide (02) substrates etch with lower He ion doses and are found to have a residual conductivity after etching, which we attribute to contamination by hydrocarbons.

  • 49.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Echtermeyer, T. J.
    Baus, M.
    Szafranek, B. N.
    Bolten, J.
    Schmidt, M.
    Wahlbrink, T.
    Kurz, H.
    Mobility in graphene double gate field effect transistors2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 4, 514-518 p.Article in journal (Refereed)
    Abstract [en]

    In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top-down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double-gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra-thin body silicon-on-insulator MOSFETs cannot compete with graphene FET values. (c) 2007 Elsevier Ltd. All rights reserved.

  • 50.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Echtermeyer, Tim J.
    Baus, Matthias
    Kurz, Heinrich
    A graphene field-effect device2007In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 4, 282-284 p.Article in journal (Refereed)
    Abstract [en]

    In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs.

123 1 - 50 of 114
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