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  • 1.
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Core Switching Noise for On-Chip 3D Power Distribution Networks2012Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Reducing the interconnect size with each technology node and increasing speed with each generation increases IR-drop and Ldi/dt noise. In addition to this, the drive for more integration increases the average current requirement for modern ULSI design. Simultaneous switching of core logic blocks and I/O drivers produces large current transients due to power distribution network parasitics at high clock frequency. The current transients are injected into the power distribution planes thereby inducing noise in the supply voltage. The part of the noise that is caused by switching of the internal logic load is core switching noise. The core logic switches at much higher speed than driver speed whereas the package inductance is less than the on-chip inductance in modern BGA packages. The core switching noise is currently gaining more attention for three-dimensional integrated circuits where on-chip inductance is much higher than the board and package inductance due to smaller board, and package. The switching noise of the driver is smaller than the core switching noise due to small driver size and reduced capacitance associated with short on-board wires for three-dimensional integrated circuits. The load increases with the addition of each die. The power distribution TSV pairs to supply each extra die also introduce additional parasitic. The core switching noise may propagate through substrate and consequently through interconnecting TSVs to different dies in heterogeneous integrated system. Core switching noise may lead to decreased device drive capability, increased gate delays, logic errors, and reduced noise margins. The actual behavior of the on-chip load is not well known in the beginning of the design cycle whereas altering the design during later stages is not cost effective. The size of a three-dimensional power distribution network may reach billions of nodes with the addition of dies in a vertical stack. The traditional tools may run out of time and memory during simulation of a three-dimensional power distribution network whereas, the CAD tools for the analysis of 3D power distribution network are in the process of evolution. Compact mathematical models for the estimation of core switching noise are necessary in order to overcome the power integrity challenges associated with the 3D power distribution network design. This thesis presents three different mathematical models to estimate core switching noise for 3D stacked power distribution networks. A time-domain-based mathematical model for the estimation of design parameters of a power distribution TSV pair is also proposed. Design guidelines for the estimation of optimum decoupling capacitance based on flat output impedance are also proposed for each stage of the vertical chain of power distribution TSV pairs. A mathematical model for tradeoff between TSV resistance and amount of decoupling capacitance on each DRAM die is proposed for a 3D-DRAM-Over-Logic system. The models are developed by following a three step approach: 1) design physical model, 2) convert it to equivalent electrical model, and 3) formulate the mathematical model based on the electrical model. The accuracy, speed and memory requirement of the proposed mathematical model is compared with equivalent Ansoft Nexxim models.

  • 2.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system2012In: IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, IEEE conference proceedings, 2012, p. 590-594Conference paper (Refereed)
    Abstract [en]

    The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.

  • 3.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 73, no 1, p. 311-328Article in journal (Refereed)
    Abstract [en]

    In this article we propose an efficient and accurate model to estimate peak-to-peak core switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of dies interconnected through TSVs. The proposed model is accurate with only a 2–3% difference in peak-to-peak core switching noise as compared to the Ansoft Nexxim4.1 equivalent model. The proposed model is 3–4 times faster than Ansoft Nexxim4.1 and uses two times less memory as compared to the Ansoft Nexxim4.1 equivalent model. In this article we also thoroughly establish design guidelines for almost flat output impedance magnitude at each stage of a vertical chain of power distribution TSV pairs to realize a resonance free scenario over a wide operating frequency range. We also establish decoupling capacitance design guidelines based on the optimum output impedance and critically damped supply voltage for the core logic for each stage of a vertical chain of power distribution TSV pairs.

  • 4.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs2010In: 28th Norchip Conference, NORCHIP 2010, 2010, article id 5669473Conference paper (Refereed)
    Abstract [en]

    On-chip power supply noise has become a bottleneck in 3D ICs as scaling of the supply network impedance has not been kept up with increasing device densities and operating currents with each technology node due to limited wire resources. In this paper we proposed an efficient and accurate model to estimate peak-to-peak switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of ICs. The proposed model is quite accurate with only 2-3% difference from Ansoft Nexxim4.1 equivalent model. The proposed model is 3-4 times faster than Nexxim4.1 as well as consumes two times less memory as compared to Nexxim4.1equivalent model. We analyzed peak-to-peak switching noise along a vertical chain of power distribution TSV pairs by varying physical dimensions of TSVs and value of decoupling capacitance. We also thoroughly investigated the peak-to-peak noise sensitivity to TSV effective inductance and decoupling capacitance.

  • 5.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Peak-to-peak Switching Noise and LC Resonance on a Power Distribution TSV Pair2010In: 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 173-176, article id 5642574Conference paper (Refereed)
    Abstract [en]

    How peak-to-peak switching noise as well as the LC resonance term varies by varying different circuit parameters of a power distribution TSV pair (having decoupling capacitance and logic load), within a 3D stack of ICs interconnected through TSVs.

  • 6.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kanth, Rajeev Kumar
    Turku Centre for Computer Science .
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Fast Transient Simulation Algorithm for a 3D Power distribution Bus2010In: Proceedings of IEEE Asia Symposium on Quality Electronic Design, 2010, p. 343-350Conference paper (Refereed)
    Abstract [en]

    Extensive transient simulations for on-chip power delivery networks are required to analyze power delivery fluctuations caused by dynamic IR and Ldi/dt drops. Speed and memory has become a bottleneck for simulation of power distribution networks in modern VLSI design where clock frequency is of the order of GHz. The traditional SPICE based tools are very slow and consume a lot of memory during simulation. The problem is further aggravated for huge networks like power distribution network within a stack of ICs inter-connected through TSVs. This type of 3D power distribution network may contain billions of nodes at a time. In this paper we proposed a faster transient simulation algorithm using visual C++. First we reduce 3D power distribution bus containing n nodes to a two terminal 7 network. Then we solve this two terminal reduced network for voltages and currents. After this, we apply back solving algorithm to the network to solve it for each of the intermediate nodes using visual C++. The proposed algorithm is quite accurate with 1-2% error when compared with Ansoft Nexxim4.1. The proposed algorithm is several times faster than Ansoft Nexxim as well as consumes significantly less memory as compared to Nexxim.

  • 7.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kanth, Rajeev Kumar
    Turku Centre for Computer Science .
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Power distribution TSVs induced core switching noise2011In: Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE, IEEE conference proceedings, 2011Conference paper (Refereed)
    Abstract [en]

    Size of on-chip interconnects as well as the supply voltage is reducing with each technology node whereas the operating speed is increasing in modern VLSI design. Today, the package inductance and resistance has been reduced to such an extent that core switching noise caused by on-chip inductance and on-chip resistance is gaining importance as compared to I/O drivers switching noise. Both on-chip inductance and skin effect are prime players at frequencies of the order of GHz. The problem is further aggravated when chips are interconnected through TSVs to form a 3D integrated stack in order to achieve low form factor and high integration density. In this paper we analysed peak core switching noise in a 3D stack of integrated chips interconnected through power distribution TSV pairs, through our comprehensive mathematical model which has been proved to be quite accurate as compared to SPICE. We analysed the effect of number of chips in a 3D stack, rise time, decoupling capacitance, and skin effect on power distribution TSVs induced core switching noise in this paper.

  • 8.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Switching Noise in 3D Power Distribution Networks: an Overview2012In: VLSI  design / [ed] Esteban Tlelo-Cuautle, Sheldon Tan, Intech , 2012, p. 209-224Chapter in book (Refereed)
  • 9.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Peak-to-Peak Ground Noise on a Power Distribution TSV Pair as a Function of Rise Time in 3-D Stack of Dies Interconnected Through TSVs2011In: IEEE Transactions on Components Packaging and Manufacturing Technology, ISSN 2156-3950, Vol. 1, no 2, p. 196-207Article in journal (Refereed)
    Abstract [en]

    Supply grids of integrated chips are interconnected through through-silicon vias (TSVs) in modern design techniques to form a 3-D stack in vertical direction. The load on each chip is supplied through (power/ground) TSV pairs. Accurate estimation of power/ground noise on each TSV pair of a 3-D power distribution network is necessary for a robust power supply design. The worst case noise obtained with fast switching characteristics may not be significantly accurate. The behavior of power/ground noise as a function of rise time for an inductive power distribution TSV pair with decoupling capacitance, is investigated in this paper. An equivalent rise time corresponding to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. In addition noise sensitivity to decoupling capacitance and TSV inductance is evaluated as a function of rise time. We also discuss noise accumulation as a result of worst case damping factor in this paper.

  • 10.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Weerasekera, Roshan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Weldezion, Awet Yemane
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Power Integrity Optimization of 3D Chips Stacked Through TSVs2009In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, NEW YORK: IEEE , 2009, p. 105-108Conference paper (Refereed)
    Abstract [en]

    On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.

  • 11.
    Ansari, Muhammad Adeel
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Diode based charge pump design using 0.35μm technology2010In: 28th Norchip Conference, NORCHIP 2010, IEEE , 2010, p. 5669437-Conference paper (Refereed)
    Abstract [en]

    A high voltage charge pump design is being presented in this paper. The design is based on Dickson charge pump, constructed with diodes by using AMS 0.35μm technology. The innovation is made in Dickson charge pump i.e. charge control PMOS transistor is used in each stage of charge pump. PMOS transistor is used in series with charging capacitor which reduces the power consumption during the clock transition by controlling the time constant of each stage. The resistance between drain to source of PMOS transistor increases the time constant during the charging of the capacitor placed in each stage of charge pump. The output voltage of about 5.693V is achieved by the six stages of Dickson charge pump at no-load which reduces to 5.537V with the six stages of proposed charge pump but the power during the input clock transition is reduced from 340.5μw (consumed by Dickson charge pump) to 28.85 μW (consumed by the proposed modified charge pump). Some other results are also discussed in this paper, which are achieved on different load resistances.

  • 12.
    Ansari, Muhammad Adeel
    et al.
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Signell, Svante R.
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    Single clock charge pump designed in 0.35μm technology2011In: Proceedings of the 18th International Conference - Mixed Design of Integrated Circuits and Systems, MIXDES 2011, 2011, p. 552-556Conference paper (Refereed)
    Abstract [en]

    An on-chip novel design of a single clock charge pump for high voltage applications is being presented in this paper. The proposed charge pump is designed using AMS 0.35μm technology. Three stages of the proposed charge pump are being used for the results verification and comparing them with the six stages of Dickson charge pump designed with diode connected PMOS. The proposed charge pump gives an output voltage of 5.34V at no-load. The proposed charge pump gives maximum efficiencies of 89% on 1MHz frequency and 87.4% on 5MHz frequency using 1Mohm load resistance. The efficiency and the output voltage including voltage gain per stage of the proposed charge pump are higher than the Dickson charge pump measured under similar conditions mediating that the performance of proposed charge pump is better than the Dickson charge pump.

  • 13. Kanth, R. K.
    et al.
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liljeberg, P.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Analysis, design and development of novel, low profile 2.487 GHz microstrip antenna2010In: 2010 14th International Symposium on Antenna Technology and Applied Electromagnetics and the American Electromagnetics Conference, ANTEM/AMEREM 2010, 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    International Telecommunication Union Radio Communication Sector ( ITU-R) has assigned 1.176 GHz and 2.487 GHz respectively in L and S band to Regional Navigational Satellite System (RNSS) for satellite navigation purpose. In this paper attempt has been made to design a novel, low profile compact microstrip antenna which achieves required specification such as gain of -4dBi up to ±50° and bandwidth of 30 MHz. The design of S band antenna was carried out using Ansoft Designer software, was fabricated and the required performance of antenna was measured in terms of its return loss, VSWR and gain radiation pattern. The return loss of the developed antenna was measured with the vector network analyzer and its gain radiation pattern in anechoic chamber and the performance of its measurements were compared with the analyzed results.

  • 14. Kanth, R. K.
    et al.
    Liljeberg, P.
    Tenhunen, H.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shakya, S.
    Zheng, Li Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Autonomous use of fractal structure in low cost, multiband and compact navigational antenna2010In: Proc. Mediterranean Microwave Symp. (MMS), 2010, p. 135-138Conference paper (Refereed)
    Abstract [en]

    Different fractal structures and their relevance in navigational antennas have been studied. Based on multiband characteristics and performance of sierpinski gasket fractal structures, a dual band, low profile antenna is devised in this paper. Classical fractal structures have been generated with extensive use of MATL AB, dimensions of the parasitic layers are determined viaseveral optimizations in Math CAD and finally design analysis is carried out using Ansoft Designer. The performance of this antenna is theoretically measured in terms of its return loss, gain radiation pattern and axial ratio. The multi layered physical antenna has been fabricated using glass epoxy substrate material contributing acceptable bandwidth in bothbands. The measured performance of the fabricated antenna has been analyzed and evaluated with the theoretical outcomes.

  • 15. Kanth, R. K.
    et al.
    Liljeberg, P.
    Tenhunen, H.
    Wan, Qiansu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, H.
    Insight into the requirements of self-aware, adaptive and reliable embedded sub-systems of satellite spacecraft2011In: PECCS - Proc. Int. Conf. Pervasive Embedded Comput. Commun. Syst., 2011, p. 603-608Conference paper (Refereed)
    Abstract [en]

    This position paper gives an insight for self-aware and adaptivity requirements of the sub-systems embedded in a satellite spacecraft. The most significant and considerable issues of self-aware and adaptive systems that are necessary in present and future on-board satellite spacecraft are illustrated in this paper. An attempt has been made to discuss several embedded sub-systems and space environment scenarios of the spacecraft. As a case study, an adaptive sierpinski based dual band antenna has been devised. The adaptive nature of this antenna provides a foundation of longer and more reliable mission life of a spacecraft. Through this paper it will be shown that adaptive, reconfigurable and reliability issues are the most prominent and potential area of research for outer space communication technology.

1 - 15 of 15
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  • ieee
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