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  • 1.
    Al Khatib, Iyad
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Performance Analysis of Application-Specific Multicore Systems on Chip2008Doctoral thesis, monograph (Other scientific)
    Abstract [en]

    The last two decades have witnessed the birth of revolutionary technologies in data communications including wireless technologies, System on Chip (SoC), Multi Processor SoC (MPSoC), Network on Chip (NoC), and more. At the same time we have witnessed that performance does not always keep pace with expectations in many services like multimediaservices and biomedical applications. Moreover, the IT market has suffered from some crashes. Hence, this triggered us to think of making use of available technologies and developing new ones so that the performance level is suitable for given applications and services. In the medical field, from a statistical viewpoint, the biggest diseases in number of deaths are heart diseases, namely Cardiovascular Disease (CVD) and Stroke. The application with the largest market for CVD is the electrocardiogram (ECG/EKG) analysis. According to the World Health Organization (WHO) report in 2003, 29.2% of global deaths are due to CVD and Stroke, half of which could be prevented if there was proper monitoring. We found in the new advance in microelectronics, NoC, SoC, and MPSoC, a chance of a solution for such a big problem. We look at the communication technologies, wireless networks, and MPSoC and realize that many projects can be founded, and they may affect people's lives positively, as for example, curing people more rapidly, as well as homecare of such large scale diseases. These projects have a medical impact as well as economic and social impacts. The intention is to use performance analysis of interconnected microelectronic systems and combine it with MPSoC and NoC technologies in order to evolve to new systems on chip that may make a difference. Technically, we aim at rendering more computations in less time, on a chip with smaller volume, and with less expense. The performance demand and the vision of having a market success, i.e. contributing to lower healthcare costs, pose many challenges on the hardware/software co-design to meet these goals. This calls upon the development of new integrated circuits featuring increased energy efficiency while providing higher computation capabilities, i.e. better performance. The biomedical application of ECG analysis is an ideal target for an application-specific SoC implementation. However, new 12-lead ECG analyses algorithms are needed to meet the aforementioned goals. In this thesis, we present two novel algorithms for ECG analysis, namely the Autocorrelation-Function (ACF) based algorithm and the Fast Fourier Transform (FFT) based algorithm. In this respect, we explore the design space by analyzing different hardware and software architectures. As a result, we realize a design with twelve processors that can compute 3.5 million arithmetic computations and respect the real time hard deadline for our biomedical application (3.5-4seconds), and that can deploy the ACF-based and FFT-based algorithms. Then, we investigate the configuration space looking for the most effective solution, performance and energy-wise. Consequently, we present three interconnect architectures (Single Bus, Full Crossbar, and Partial Crossbar) and compare them with existing solutions. The sampling frequencies of 2.2 KHz and 4 KHz, with 12 DSPs, are found to be the critical points for our Shared-Bus design and Crossbar architecture, respectively. We also show how our performance analysis methods can be applied to such a field of SoC design and with a specific purpose application in order to converge to a solution that is acceptable from a performance viewpoint, meets the real-time demands, and can be implemented with the present technologies while at the same time paving the way for easier and faster development. In order to connect our MPSoC solution to communication networks to transmit the medical results to a healthcare center, we come up with new protocols that will allow the integration of multiple networks on chips in a communication network. Finally, we present a methodology for HW/SW Codesign for application-specific systems (with focus on biomedical applications) that require a large number of computations since this will foster the convergence to solutions that are acceptable from a performance point of view.

  • 2.
    Al Khatib, Iyad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Bertozzi, Davide
    Poletti, Francesco
    Benini, Luca
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Bechara, Mohamed
    Khalifeh, Hasan
    Hajjar, Mazen
    Nabiev, Rustam
    Jonsson, Sven
    Hardware/Software architecture for real-time ECG monitoring and analysis leveraging MPSoC technology2007In: Transactions on High-Performance Embedded Architectures and Compilers I / [ed] tenstrom, P; OBoyle, M; Bodin, F; Cintra, M; McKee, SA, 2007, Vol. 4050, p. 239-258Conference paper (Refereed)
    Abstract [en]

    The interest in high performance chip architectures for biomedical applications is gaining a lot of research and market interest. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine. However, ECG analysis still faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and it is centered on the parallelization of the ECG computation kernel. Our Hardware- Software (HW/SW) Multi-Processor System-on-Chip (MPSoQ design improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final HW/SW architecture is the focus of this paper. We explore the design space by considering a number of hardware and software architectural variants, and deploy industrial components to build up the system.

  • 3.
    Al Khatib, Iyad
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. iITC, Sweden .
    Ismail, M.
    WNoC: A microelectronic system architecture suitable for biomedical wireless sensor networks2005Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-cost microelectronic system architecture suitable for single chip CMOS integration. The system architecture consists of a large set of on-chip processing-cores, sensors, and four multi-standard wireless border cores that are interconnected to form an ultra-fast microelectronic network of distributed-computing systems. Our main application areas are: biomedical emergency monitoring systems and healthcare. The hardware platform is based on Network-on-Chip (NoC) design and RF circuitry for wireless connectivity. We focus on the design of this Wireless Network-on-Chip (WNoC). WNoC faces several challenges. A main issue of concern from the application point of view is to have the design support the convergence to a decision within acceptable periods of time, because time is critical in many medical healthcare applications. We define a mechanism to enable many WNoCs to interact together over the wireless media. A key result is a design and protocol for internal and external WNoC communications between the main and backup wireless cores. We run simulations on a biomedical monitoring system for emergency situations, and our results show that the time to converge to a medical warning is in the range of milliseconds, which is acceptable for the related medical scenarios.

  • 4.
    Al Khatib, Iyad
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Nabiev, Rustam
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    ECG-BIONET: A global biomedical network for human heart monitoring and analysis: Performance needs of an electrocardiogram Telemedicine platform for medical aid at the point-of-need2006In: 25TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS: VOLS 1-7, PROCEEDINGS IEEE INFOCOM 2006, New York: IEEE , 2006, p. 3282-3283Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a Tele-medicine application platform as a medical aid for patients suffering from Heart malfunction. We focus on heart diseases since they remain by far the major cause of death in the globe. Our solution utilizes the Satellite communication protocol DVB-RCS (Digital Video Broadcast- Return Channel Satellite), Wi-Fi, and the Network-on-Chip (NoC) technology. We utilize the 12-lead ECG biomedical technique to detect heart disorders via the biomedical NoC, which transmits the medical alarm and results via the biomedical network, ECG-BIONET. We do not investigate the DVB-RCS standard or Wi-Fi technology, but rather we try to utilize this technology, and we look at it from a performance point of view for our application by investigating three parameters, namely: delay, packet loss, and reliability. We follow a top down approach by looking at the needs of the application from a performance guarantee for our specific-purpose network.

  • 5.
    Al-Khatib, Iyad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Bertozzi, Davide
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Benini, Luca
    Performance Analysis and Design Space Exploration for High-End Biomedical Applications: Challenges and Solutions2007In: Proceedings of the International Conference on Hardware - Software Codesign and System Synthesis, 2007, p. 217-226Conference paper (Refereed)
    Abstract [en]

    High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.

  • 6.
    Al-Khatib, Iyad
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Poletti, Francesco
    Bertozzi, Davide
    Benini, Luca
    Bechara, Mohamed
    Khalifeh, Hasan
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Nabiev, Rustam
    A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis: Architectural Design Space Exploration2006In: DAC '06: Proceedings of the 43rd annual Design Automation Conference, 2006, p. 125-130Conference paper (Refereed)
    Abstract [en]

    In this paper we focus on MPSoC architectures for human heart ECGreal-time monitoring and analysis. This is a very relevant bio-medicalapplication, with a huge potential market, hence it is an ideal targetfor an application-specific SoC implementation. We investigate asymmetric multi-processor architecture based on STMicroelectronicsVLIW DSPs that process in real-time 12-lead ECG signals. Thisarchitecture improves upon state-of-the-art SoC designs for ECGanalysis in its ability to analyze the full 12 leads in real-time, evenwith high sampling frequencies, and ability to detect heartmalfunction. We explore the design space by considering a number ofhardware and software architectural options.

  • 7.
    Baudette, Maxime
    et al.
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Vanfretti, Luigi
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Del Rosario, Gerard
    IREC.
    Ruiz Alvarez, Albert
    IREC.
    Dominguez Garcia, Jose Luis
    IREC.
    Al-Khatib, Iyad
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Shoaib Almas, Muhammad
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Gjerde, Jan Ove
    Statnett SF.
    Validating a real-time PMU-based application for monitoring of sub-synchronous wind farm oscillations2014In: 2014 IEEE PES Innovative Smart Grid Technologies Conference, 2014, p. 1-5Conference paper (Refereed)
    Abstract [en]

    This paper presents validation experiments performed on a Phasor Measurement Unit (PMU) based fast oscillation detection application. The monitoring application focuses on the detection of sub-synchronous oscillations, utilizing real-time measurements from PMUs. The application was first tested through Hardware-In-the-Loop (HIL) simulation. Validation experiments were carried out with a different set-up by utilizing a micro grid laboratory. This second experimental set-up as well as the results of the validation experiments are presented in this paper.

  • 8.
    Cairo, Ignasi
    et al.
    IREC.
    Del Rosario, Gerard
    IREC.
    Dominguez, J.L.
    IREC.
    Vanfretti, Luigi
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Al-Khatib, Iyad
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Baudette, Maxime
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Almas, M. Shoaib
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Equipos para medidas precisas de fase en tension corriente para redes inteligentes2013In: Automatica e Instrumentación, ISSN 0213-3113, no 451, p. 87-90Article in journal (Other (popular science, discussion, etc.))
  • 9.
    Chenine, Moustafa
    et al.
    KTH, School of Electrical Engineering (EES), Industrial Information and Control Systems.
    Al Khatib, Iyad
    Ivanovski, Jordan
    Maden, Volkan
    Nordström, Lars
    KTH, School of Electrical Engineering (EES), Industrial Information and Control Systems.
    PMU traffic shaping in IP-based wide area communication2010In: 2010 5th International Conference on Critical Infrastructure, CRIS 2010 - Proceedings, IEEE conference proceedings, 2010, p. 1-6Conference paper (Refereed)
    Abstract [en]

    Phasor based Wide Area Monitoring and Control (WAMC) Systems are becoming a reality with increased research, development and deployments. Many potential control applications based on these systems are being proposed and researched. Such applications are either local applications using data from one or a few Phasor Measurement Units (PMUs) or centralized utilizing data from several PMUs. An aspect of these systems, which is less well researched, is the WAMC system dependence on high performance communication. This paper presents results of research on the use of Internet Protocol (IP) networks for both PMU and Remote Terminal Unit (RTU)/Intelligent Electronic Devices (IED) data for monitoring purposes. The paper examines performance aspects of the IP network Infrastructures when utilized by both: continuous PMU data streams and critical IED/RTU data. A set of simulation models characterizing a network of a Nordic Transmission System Operator were built to perform the analysis. The paper considers Quality of Service (QoS) strategies and the resulting delays and data loss that would be experienced.

  • 10.
    Khatib, Iyad Al
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ayani, Rassul
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Maguire Jr., Gerald Q.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Wireless LAN Access Points Uplink and Downlink Delays: Packet Service-Time Comparison2002In: Proceedings of 16th Nordic Teletraffic Seminar, 2002, 2002, p. 253-264Conference paper (Refereed)
    Abstract [en]

    Wireless LAN access points are very important connecting nodes transferring traffic between two media in opposite directions. Hence the performance of the wireless LAN access point should be looked upon from two different reference points: uplink (from WLAN to Ethernet) and Downlink (from Ethernet to WLAN). This paper builds on our previous modeling of the wireless access point as a single server, FIFO, queuing system to analyze the service times in both directions. The previous analysis showed that the average service time is a function of payload. Measurements have revealed that the uplink service time is much smaller than the downlink service time for the same payload. In this paper, we investigate the absolute value of the difference between the uplink and downlink service-times. We refer to the absolute value of the difference in time between uplink and downlink as the UDC, or the"Uplink-Downlink Contrast". Results show that as the packet size increases, the UDC either decreases or increases monotonically depending on the brand of the access point. For a decreasing UDC, the absolute value of the difference between the uplink and downlinkservice-times decreases, hence the UDC is convergent. Similarly, the UDC is divergent if it increases with increasing packet size. These results can be used to select a WLAN accesspoint given the size of packets transmitted by an application or multiple applications over a Local Area Network.

  • 11.
    Khatib, Iyad Al
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Bertozzi, Davide
    Poletti, Francesco
    Benini, Luca
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Bechara, Mohamed
    Khalifeh, Hasan
    Hajjar, Mazen
    Nabiev, Rustam
    Jonsson, Sven
    MPSoC ECG biochip: A multiprocessor system-on-chip for real-time human heart monitoring and analysis2006In: Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06, 2006, p. 21-28Conference paper (Refereed)
    Abstract [en]

    The interest in high performance chip architectures for biomedical applications is on the rise. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine, which faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and is centered on the parallelization of the ECG computation kernel. It improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final hardware/software architecture, modeling, and simulation is the focus of this paper. Our system model is based on industrial components. The architectural template we employ is scalable and flexible.

  • 12.
    Khatib, Iyad Al
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Kayal, Bassam
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Nabiev, Rustam
    Jonsson, Sven
    Wireless Network-on-Chips as Autonomous Systems: A Novel Solution for Biomedical Healthcare and Space Exploration Sensor-Networks2005In: Proceedings of the Infocom 2005 Conference - Student Workshop, 2005Conference paper (Refereed)
  • 13.
    Khatib, Iyad Al
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Maguire Jr., Gerald Q.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ayani, Rassul
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Forsgren, Daniel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    MobiCom poster: wireless LAN access points as queuing systems: performance analysis and service time2003In: ACM SIGMOBILE Mobile Computing and Communications Review, ISSN 1559-1662, Vol. 7, no 1, p. 28-30Article in journal (Refereed)
    Abstract [en]

    Since the approval of the IEEE 802.11b by the IEEE in 1999, the demand for WLAN equipment and networks has been growing quickly. We present a queuing model of wireless LAN (WLAN) access points (APs) for IEEE 802.11b. We use experimentation to obtain the characteristic parameters of our analytic model. The model can be used to compare the performance of different WLAN APs as well as the QoS of different applications in the presence of an AP. We focus on the delay introduced by an AP. The major observations are that the delay to serve a packet going from the WLAN medium to the wired medium (on the uplink) is less than the delay to serve a packet, with identical payload, but travelling from the wired medium to the WLAN medium (on the downlink). A key result is an analytic solution showing that the average service time of a packet is a strictly increasing function of payload.

  • 14.
    Khatib, Iyad Al
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Maguire Jr., Gerald Q.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ayani, Rassul
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Forsgren, Daniel
    Wireless LAN Access Points as a Queuing System2002In: Proceedings of The Communications and Computer Networks 2002 Conference (CCN 2002), 2002, p. 463-468Conference paper (Refereed)
    Abstract [en]

    This paper presents a research study of wireless LAN access points for IEEE 802.11b, where we seek to model the access point as a queuing system. The model can be used to compare performance metrics of different wireless LAN access points and to investigate the QoS of specific applications in the presence of a wireless LAN access point. In this paper, we focus on two parameters: the delay introduced by a wireless LAN access point and the average service time required to serve a packet passing through an access point. A major result is an analytic solution for the average service time of a packet in relationship to payload.

  • 15.
    Khatib, Iyad Al
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Maguire Jr., Gerald Q.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ayani, Rassul
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Forsgren, Daniel
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wireless LAN Access Points as a Queuing System, Performance Analysis and Service Time2002In: The Eighth ACM International Conference on Mobile Computingand Networking (ACM MOBICOM 2002 Conference), Association for Computing Machinery (ACM), 2002Conference paper (Refereed)
  • 16.
    Khatib, Iyad Al
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Poletti, Francesco
    Bertozzi, Davide
    Benini, Luca
    Bechara, Mohamed
    Khalifeh, Hasan
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Nabiev, Rustam
    A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration2008In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 13, no 2, p. 31-Article in journal (Refereed)
    Abstract [en]

    In this article we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart electrocardiogram (ECG) real time analysis as a hardware/software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is a relevant biomedical application with good potential market, since heart diseases are responsible for the largest number of yearly deaths. Hence, it is a good target for an application-specific system-on-chip (SoC) and HW/SW codesign. We investigate a symmetric multiprocessor architecture based on STMicroelectronics VLIW DSPs that process in real time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real time, even with high sampling frequencies, and its ability to detect heart malfunction for the whole ECG signal interval. We explore the design space by considering a number of hardware and software architectural options. Comparing our design with present-day solutions from an SoC and application point-of-view shows that our platform can be used in real time and without failures.

  • 17. Laverty, D. M.
    et al.
    Vanfretti, Luigi
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Al Khatib, Iyad
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Applegreen, Viktor K.
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Best, R. J.
    Morrow, D. J.
    The OpenPMU Project: Challenges and perspectives2013In: 2013 IEEE Power and Energy Society General Meeting (PES), IEEE , 2013Conference paper (Refereed)
    Abstract [en]

    The OpenPMU project is a platform for the development of Synchrophasor measurement technology, Phasor Measurement Units (PMU), in an open source manner. The project has now been operating for a number of years and has seen increased adoption at Universities and interest from electrical utilities. The OpenPMU device has recently been tested against the IEEE C37.118 standard and shown to operate within the specification. This paper discusses the OpenPMU project from the perspective of the past two years of experience and evaluates successes and opportunities for improvements in both the OpenPMU device and the philosophy of the design.

  • 18. Laverty, David M.
    et al.
    Best, Robert J.
    Brogan, Paul
    Al Khatib, Iyad
    KTH.
    Vanfretti, Luigi
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Morrow, D. John
    The OpenPMU Platform for Open-Source Phasor Measurements2013In: IEEE Transactions on Instrumentation and Measurement, ISSN 0018-9456, E-ISSN 1557-9662, Vol. 62, no 4, p. 701-709Article in journal (Refereed)
    Abstract [en]

    OpenPMU is an open platform for the development of phasor measurement unit (PMU) technology. A need has been identified for an open-source alternative to commercial PMU devices tailored to the needs of the university researcher and for enabling the development of new synchrophasor instruments from this foundation. OpenPMU achieves this through open-source hardware design specifications and software source code, allowing duplicates of the OpenPMU to be fabricated under open-source licenses. This paper presents the OpenPMU device based on the Labview development environment. The device is performance tested according to the IEEE C37.118.1 standard. Compatibility with the IEEE C37.118.2 messaging format is achieved through middleware which is readily adaptable to other PMU projects or applications. Improvements have been made to the original design to increase its flexibility. A new modularized architecture for the OpenPMU is presented using an open messaging format which the authors propose is adopted as a platform for PMU research.

  • 19.
    Vanfretti, Luigi
    et al.
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Baudette, Maxime
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Al-Khatib, Iyad
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Almas, Muhammad Shoaib
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Gjerde, Jan Ove
    Testing and Validation of a Fast Real-Time Oscillation Detection PMU-Based Application for Wind-Farm Monitoring2013In: 2013 First International Black Sea Conference on Communications and Networking (BlackSeaCom), IEEE conference proceedings, 2013, p. 216-221Conference paper (Refereed)
    Abstract [en]

    This article provides an overview of a monitoring application, its testing and validation process. The application was developed for the detection of sub-synchronous oscillations in power systems, utilizing real-time measurements from phasor measurement units (PMUs). It uses two algorithms simultaneously to both detect the frequency at which the oscillatory event occurs and the level of energy in the oscillations. The application has been developed and tested in the framework of SmarTS Lab, an environment capable of hardware-in-the-loop (HIL) simulation. The necessary components of the real-time chain of data acquisition are presented in this paper, as well as testing and validation results, to demonstrate the accuracy of the monitoring tool and the feasibility of fast prototyping for real-time PMU measurements based applications using the SmarTS Lab environment.

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