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  • 1.
    Jafri, Syed M. A. H.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
    Tajammul, Adeel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Paul, Kolin
    Indian Institute of Technology.
    Ellervee, Peeter
    Plosila, Juha
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
    Morphable Compression Architecture for Efficient Configuration in CGRAs2014In: 2014 17th Euromicro Conference on Digital System Design (DSD), 2014, p. 42-49Conference paper (Refereed)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads (up to 50% area of the overall platform). As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties (i.e. compression ratio and decoding time), and is therefore best suited for a particular class of applications (and situation). However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to enjoy a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Thereby, our solution offers minimal memory while meeting the required configuration deadlines. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (from configware replication to 52%) and configuration cycles (from 33 nsec to 1.5 secs) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

  • 2.
    Jafri, Syed M.A.H.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
    Tajammul, Adeel
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Paul, Kolin
    Ellervee, Peeter
    Plosila, Juha
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Customizable Compression Architecture for Efficient Configuration in CGRAs2011In: Proceedings: 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, 2011, p. 31-31Conference paper (Refereed)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads. As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties, and is therefore best suited for a particular class of applications. However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform.

  • 3.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. Turku Centre for Computer Science, Finland; University of Turku, Finland.
    Gia, T.N.
    University of Turku, Finland.
    Dytckov, Sergei
    University of Turku, Finland.
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Plosila, Juha
    Turku Centre for Computer Science, Finland; University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
    NeuroCGRA: A CGRA with support for neural networks2014In: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014, IEEE , 2014, p. 506-511Conference paper (Refereed)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) are becoming an increasingly popular implementation platform. In real world applications, the CGRAs are required to simultaneously host processing (e.g. Audio/video acquisition) and estimation (e.g. audio/video/image recognition) tasks. For estimation problems, neural networks, promise a higher efficiency than conventional processing. However, most of the existing CGRAs provide no support for neural networks. To realize realize both neural networks and conventional processing on the same platform, this paper presents NeuroCGRA. NeuroCGRA allows the processing elements and the network to dynamically morph into either conventional CGRA or a neural network, depending on the hosted application. We have chosen the DRRA as a vehicle to study the feasibility and overheads of our approach. Synthesis results reveal that the proposed enhancements incur negligible overheads (4.4% area and 9.1% power) compared to the original DRRA cell.

  • 4.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Paul, Kolin
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Plosila, Juha
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures2011In: Proc. IEEE Int Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW) Symp, 2011, p. 290-293Conference paper (Refereed)
    Abstract [en]

    This paper considers the possibility of speeding up the configuration by reducing the size of configware in coarsegrained reconfigurable architectures (CGRAs). Our goal was to reduce the number of cycles and increase the configuration bandwidth. The proposed technique relies on multicasting and bitstream compression. The multicasting reduces the cycles by configuring the components performing identical functions simultaneously, in a single cycle, while the bitstream compression increases the configuration bandwidth. We have chosen the dynamically reconfigurable resource array (DRRA) architecture as a vehicle to study the efficiency of this approach. In our proposed method, the configuration bitstream is compressed offline and stored in a memory. If reconfiguration is required, the compressed bitstream is decompressed using an online decompresser and sent to DRRA. Simulation results using practical applications showed upto 78% and 22% decrease in configuration cycles for completely parallel and completely serial implementations, respectively. Synthesis results have confirmed nigligible overhead in terms of area (1.2 %) and timing.

  • 5.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Leon, Guillermo Serrano
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Abbas, N.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Paul, Kolin
    Indian Institute of Technology.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    TransPar: Transformation based dynamic Parallelism for low power CGRAs2014In: Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014, 2014Conference paper (Refereed)
    Abstract [en]

    Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer runtime parallelism to reduce energy consumption (by lowering voltage/frequency). To implement the runtime parallelism, CGRAs commonly store multiple compile-time generated implementations of an application (with different degree of parallelism) and select the optimal version at runtime. However, the compile-time binding incurs excessive configuration memory overheads and/or is unable to parallelize an application even when sufficient resources are available. As a solution to this problem, we propose Transformation based dynamic Parallelism (TransPar). TransPar stores only a single implementation and applies a series for transformations to generate the bitstream for the parallel version. In addition, it also allows to displace and/or rotate an application to parallelize in resource constrained scenarios. By storing only a single implementation, TransPar offers significant reductions in configuration memory requirements (up to 73% for the tested applications), compared to state of the art compaction techniques. Simulation and synthesis results, using real applications, reveal that the additional flexibility allows up to 33% energy reduction compared to static memory based parallelism techniques. Gate level analysis reveals that TransPar incurs negligible silicon (0.2% of the platform) and timing (6 additional cycles per application) penalty.

  • 6.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Leon, Guillermo Serrano
    Iqbal, J.
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Paul, Kolin
    Indian Institute of Technology.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs2014In: Proceedings - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014, 2014, p. 233-241Conference paper (Refereed)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Compile-time mapping decisions are neither optimal nor desirable to efficiently support the diverse and unpredictable application requirements. As a solution to this problem, recently proposed architectures offer run-time remapping. The run-time remappers displace or expand (parallelize/serialize) an application to optimize different parameters (such as platform utilization). However, the existing remappers support application displacement or expansion in either horizontal or vertical direction. Moreover, most of the works only address dynamic remapping in packet-switched networks and therefore are not applicable to the CGRAs that exploit circuitswitching for low-power and high predictability. To enhance the optimality of the run-time remappers, this paper presents a design framework called Run-time Rotatable-expandable Partitions (RuRot). RuRot provides architectural support to dynamically remap or expand (i.e. parallelize) the hosted applications in CGRAs with circuit-switched interconnects. Compared to state of the art, the proposed design supports application rotation (in clockwise and anticlockwise directions) and displacement (in horizontal and vertical directions), at run-time. Simulation results using a few applications reveal that the additional flexibility enhances the device utilization, significantly (on average 50 % for the tested applications). Synthesis results confirm that the proposed remapper has negligible silicon (0.2 % of the platform) and timing (2 cycles per application) overheads.

  • 7.
    Kelati, Amleset
    et al.
    University of Turku (UTU), Turku, Finland.
    Plosila, Juha
    University of Turku (UTU), Turku, Finland.
    Tenhunen, Hannu
    University of Turku (UTU), Turku, Finland.
    Smart Meter Load Profiling for e-Health Monitoring System2019In: 2019 IEEE 7th International Conference on Smart Energy Grid Engineering (SEGE), Oshawa, ON, Canada: IEEE, 2019, , p. 6Conference paper (Refereed)
    Abstract [en]

    A structural health-monitoring system needed to come out from the problem associated due to the rapidly growing population of elderly and the health care demand. The paper discussed the consumer's electricity usage data, from the smart meter, how to support the healthcare sector by load profiling the normal or abnormal energy consumption. For this work, the measured dataset is taken from 12 households and collected by the smart meter with an interval of an hour for one month. The dataset is grouped according to the features pattern, reduced by matrix-based analysis and classified with K-Means algorithm data mining clustering method. We showed how the clustering result of the Sum Square Error (SSE) has connection trend to indicate normal or abnormal behavior of electricity usage and leads to determine the assumption of the consumer's health status.

  • 8.
    Kelati, Amleset
    et al.
    University of Turku (UTU), Turku, Finland.
    Plosila, Juha
    University of Turku (UTU), Turku, Finland.
    Tenhunen, Hannu
    University of Turku (UTU), Turku, Finland.
    et al.,
    Smart Meter Load Profiling for e-Health Monitoring System2019In: 2019 IEEE 7th International Conference on Smart Energy Grid Engineering (SEGE), Oshawa, ON, Canada: IEEE conference proceedings, 2019, , p. 6Conference paper (Refereed)
    Abstract [en]

    A structural health-monitoring system needed to come out from the problem associated due to the rapidly growing population of elderly and the health care demand. The paper discussed the consumer's electricity usage data, from the smart meter, how to support the healthcare sector by load profiling the normal or abnormal energy consumption. For this work, the measured dataset is taken from 12 households and collected by the smart meter with an interval of an hour for one month. The dataset is grouped according to the features pattern, reduced by matrix-based analysis and classified with K-Means algorithm data mining clustering method. We showed how the clustering result of the Sum Square Error (SSE) has connection trend to indicate normal or abnormal behavior of electricity usage and leads to determine the assumption of the consumer's health status.

  • 9. Ngyen, T.
    et al.
    Jafri, Syed
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. Turku Centre for Computer Science, Finland.
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland .
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Dytckov, Sergei
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Plosila, Juha
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland .
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
    FIST: A framework to interleave spiking neural networks on CGRAs2015In: Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, IEEE , 2015, p. 751-758Conference paper (Refereed)
    Abstract [en]

    Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern embedded applications. In many application domains (e.g. robotics and cognitive embedded systems), the CGRAs are required to simultaneously host processing (e.g. Audio/video acquisition) and estimation (e.g. audio/video/image recognition) tasks. Recent works have revealed that the efficiency and scalability of the estimation algorithms can be significantly improved by using neural networks. However, existing CGRAs commonly employ homogeneous processing resources for both the tasks. To realize the best of both the worlds (conventional processing and neural networks), we present FIST. FIST allows the processing elements and the network to dynamically morph into either conventional CGRA or a neural network, depending on the hosted application. We have chosen the DRRA as a vehicle to study the feasibility and overheads of our approach. Synthesis results reveal that the proposed enhancements incur negligible overheads (4.4% area and 9.1% power) compared to the original DRRA cell.

1 - 9 of 9
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