Change search
Refine search result
1 - 8 of 8
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1. Guang, Liang
    et al.
    Liljeberg, P.
    Nigussie, Ethiopia
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A review of dynamic power management methods in NoC under emerging design considerations2009In: 2009 NORCHIP, 2009, p. 1-6Conference paper (Refereed)
    Abstract [en]

    A review of dynamic and adaptive techniques for power management of on-chip interconnects, under emerging design considerations, is presented. The progress of IC technology has introduced novel methods, architectures and new challenges for power-aware design exploration. An examination of stateof-the-art power management techniques enables feasible and efficient design of future NoC platforms. This review first analyzes the new challenges, architectures and technologies, including PVT (process, voltage, temperature) variations, rapidly increasing leakage power, multiple on-chip PDN (power delivery network) as well as other architectures, which bring new considerations in low-power design exploration. A wide selection of dynamic power-saving techniques for onchip interconnects are examined, classified into several categories including run-time datapath configuration, supply configuration and adaptive encoding. The effects and feasibility of these methods, especially their potentials in future technology, are judiciously analyzed. An outlook on generic power management paradigms in next-generation NoCs concludes the review.

  • 2. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Isoaho, Jouni
    Rantala, Pekka
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Interconnection alternatives for hierarchical monitoring communication in parallel SoCs2010In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 34, no 5, p. 118-128Article in journal (Refereed)
    Abstract [en]

    Interconnection architectures for hierarchical monitoring communication in parallel System-on-Chip (SoC) platforms are explored. Hierarchical agent monitoring design paradigm is an efficient and scalable approach for the design of parallel embedded systems. Between distributed agents on different levels, monitoring communication is required to exchange information, which forms a prioritized traffic class over data traffic. The paper explains the common monitoring operations in SoCs, and categorizes them into different types of functionality and various granularities. Requirements for on-chip interconnections to support the monitoring communication are outlined. Baseline architecture with best-effort service, time division multiple access (TDMA) and two types of physically separate interconnections are discussed and compared, both theoretically and quantitatively on a Network-on-Chip (NoC)-based platform. The simulation uses power estimation of 65 nm technology and NoC microbenchmarks as traffic traces. The evaluation points out the benefits and issues of each interconnection alternative. In particular, hierarchical monitoring networks are the most suitable alternative, which decouple the monitoring communication from data traffic, provide the highest energy efficiency with simple switching, and enable flexible reconfiguration to tradeoff power and performance.

  • 3. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Koskinen, Lauri
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication2009In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Volume 5455 LNCS, 2009, p. 183-194Conference paper (Refereed)
    Abstract [en]

    An autonomous-DVFS-enabled supply island architecture on network-on-chip platforms is proposed. This architecture exploits the temporal and spatial network traffic variations in minimizing the communication energy while constraining the latency and supply management overhead. Each island is equipped with autonomous DVFS mechanism, which traces the local and nearby network conditions. In quantitative simulations with various types of representative traffic patterns, this approach achieves greater energy efficiency than two other low-energy architectures (typically 10% - 27% lower energy). With autonomous supply management on a proper granularity as demonstrated in this study, the communication energy can be minimized in a scalable manner for many-core NoCs.

  • 4. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Rantala, Pekka
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip2010In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 9, no 3, p. 25-Article in journal (Refereed)
    Abstract [en]

    Hierarchical agent framework is proposed to construct a monitoring layer towards self-aware parallel systems-on-chip (SoCs). With monitoring services as a new design dimension, systems are capable of observing and reconfiguring themselves dynamically at all levels of granularity, based on application requirements and platform conditions. Agents with hierarchical priorities work adaptively and cooperatively to maintain and improve system performance in the presence of variations and faults. Function partitioning of agents and hierarchical monitoring operations on parallel SoCs are analyzed. Applying the design approach on the Network-on-Chip (NoC) platform demonstrates the design process and benefits using the novel approach.

  • 5. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip2010In: Proceedings - IEEE International SOC Conference, SOCC 2010, 2010, p. 481-486Conference paper (Refereed)
    Abstract [en]

    System-level exploration of a novel Network-on-Chip (NoC) architecture with run-time communication bypassing is presented. Fine-grained DVFS (Dynamic Voltage and Frequency Scaling) is an effective power reduction technique. We propose run-time reconfigurable interconnect on each inter-router channel to minimize the latency and energy overhead. When two routers are running on the same frequency, FIFO-channel is bypassed by direct interconnect. Distributed algorithm is designed for per-core DVFS. Proper power delivery and clocking scheme are integrated. Simulation shows significant energy and latency saving.

  • 6. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    System-level exploration of run-time clusterization for energy-efficient on-chip communication2009In: 2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42, 2009, p. 63-68Conference paper (Refereed)
    Abstract [en]

    System-level exploration of run-time power clusterization for energy-efficient on-chip communication is presented. Facilitated by multiple on-chip power-delivery-networks, areas of heavy or low traffics can be dynamically identified and adaptively supplied with new power schemes. This method is superior to design-time voltage island partitioning, in dealing with unpredictable spatial and temporal variations of communication traffics in large NoCs. Architectural design of the platform and online iterative configuration process are presented. The effectiveness of the proposed approach is demonstrated quantitatively on a NoC simulator with 65nm power models. With synthetic traffic traces characterizing various communication patterns, run-time power clusterization achieves considerable energy benefits compared to existing energy-efficient architectures (9% - 42% lower). The latency penalty is predictable and moderately bounded with minimal area overhead. The proposed architecture presents an ideal tradeoff, prioritizing energy efficiency, for massively parallel on-chip computing.

  • 7. Guang, Liang
    et al.
    Rantala, P.
    Nigussie, Ethiopia
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Low-latency and Energy-efficient Monitoring Interconnect for Hierarchical-agent-monitored NoCs2008In: Norchip - 26th Norchip Conference, Formal Proceedings, 2008, p. 227-232Conference paper (Refereed)
    Abstract [en]

    This paper presents quantitative analysis of monitoring interconnect architecture alternatives in hierarchical agent-based NoC platform. Hierarchical monitoring design methodology provides scalable dynamic management services with agents monitoring different levels. To enable low-latency and lowenergy agent communication, we examined three interconnect alternatives: TDM-based virtual channeling, unified dedicated monitoring network, and separate dedicated monitoring networks. With Orion and Cadence simulators, we estimated the energy and latency of monitoring communications on the three architectures for an 8*8 mesh network in 65nm technology. The results suggest that separate dedicate links mostly minimize the communication delay and energy consumption (66.7% and 82.1% respectively compared to TDM-based interconnect), while incurring moderate area penalty.

  • 8.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Yin, A.
    Rantala, P.
    Nigussie, Ethiopia
    Department of Information Technology, University of Turku, Finland.
    Liljeberg, P.
    Isoaho, Jouni
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    Hierarchical Power Monitoring for On-chip Networks2009In: Proceedings of Work in Progress Session in Euromicro PDP 2009 Conference, 2009Conference paper (Refereed)
1 - 8 of 8
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf