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  • 1. Aktas, Adem
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ahola, Rami
    Ismail, Mohammed
    A 4 Ghz 0.18um CMOS PLL Frequency Synthesizer withWide-Band VCO for Multi-Standard Wireless Applications2003In: Proc. 22nd Norchip Conference, 2003, p. 248-251Conference paper (Refereed)
  • 2.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Carlsson, Mats
    Hedenas, Charlotta
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Low Power, Startup Ensured and Constant Amplitude Class-C VCO in 0.18 mu m CMOS2011In: IEEE Microwave and Wireless Components Letters, ISSN 1531-1309, E-ISSN 1558-1764, Vol. 21, no 8, p. 427-429Article in journal (Refereed)
    Abstract [en]

    A low power and robust class-C voltage-controlled oscillator (VCO) is presented in this letter. It features 1) an automatic startup loop to achieve the optimal point and address the inherent risk of startup failure and 2) a digital amplitude control loop to stabilize amplitude and enhance the PVT ( process, voltage and temperature) tolerance. The design is implemented in a 0.18 mu m CMOS process. Measurement demonstrates the VCO has a 20% tuning range and phase noise of -123.0 dBc/Hz at 1 MHz offset from a 3.1 GHz carrier while consuming 1.57-mW power from a 1 V supply, yielding a Figure-of-Merit (FoM) of 191.1. While operating under the minimum power of 560 mu W, it produces -111.3 dBc/Hz phase noise at 1 MHz offset from a 3.1 GHz carrier showing a 183.8 FoM.

  • 3.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Carlsson, Mats
    Hedenäs, Charlotta
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Flicker noise conversion in CMOS LC oscillators: capacitance modulation dominance and core device sizing2011In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 68, no 2, p. 145-154Article in journal (Refereed)
    Abstract [en]

    Flicker noise upconversion mechanisms in oscillators have been acquired in the literature, however their relative weights are still under investigation. It is desirable to find the dominant one, since a certain noise suppression method reduces one mechanism but may increase another. In this work, we propose a systematic simulation method to distinguish their relative impacts. The outcome indicates parasitic capacitance is the dominant factor for both tail 1/f noise and switch pair 1/f noise upconversions, implying to use small dimension core devices. Design guidelines on sizing devices are presented and two suppression techniques are compared. Two voltage-controlled oscillators (VCOs) with these suppression techniques are fabricated in a 0.18 mu m CMOS process, allowing us to compare their performance. The two VCOs can be Focused-Ion-Beam (FIB) trimmed to change the width of switch pair FETs. The fair comparison of measurement results among them verify the dominant role of parasitic capacitance in 1/f noise upconversion. The measurement results also confirm the design guidelines and demonstrate the difference of two suppression methods.

  • 4.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    Carlsson, Mats
    Hedenäs, Charlotta
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhou, Dian
    Experimental Validation of Device Sizing on CMOS LC-VCO Phase NoiseManuscript (preprint) (Other academic)
    Abstract [en]

    This work investigates the impact of device sizingon phase noise in CMOS LC-tank oscillators, based on specificdesigns and careful measurements. It experimentally verified thepreviously published equations and clarified some conflictingdesign guidelines. The conclusions are grounded on the faircomparison of seven VCOs with the core device width varyingfrom 40 um to 280 um. These VCOs are originated from the samedie by using Focused Ion Beam (FIB), guaranteeing the sameorder of process variation. With the aid of a switched capacitorbank, they are able to operate at practically same oscillationfrequency under the same bias. These conditions assure the faircomparison. It validated that phase noise from tail devices isstrongly dependent to core device size (14 dB from measurements)while phase noise from core devices themselves shows smallerdependence (4 dB). Design guidelines, applying to different tailnoise cases, are concluded and generally advise the minimumcore device width especially when tail noise is dominant.

  • 5.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Olsson, Håkan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhou, Dian
    State Key Laboratory of ASIC & System, Fudan University, Shanghai.
    A Current Shaping Technique to Lower Phase Noise in LC Oscillators2008In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008, p. 392-395Conference paper (Refereed)
  • 6.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Fast and Accurate Phase Noise Measurement of Free Running Oscillators Using a Single Spectrum Analyzer2010In: 28th Norchip Conference, NORCHIP 2010, 2010Conference paper (Refereed)
    Abstract [en]

    This paper presents a practical phase noise measurement approach, which only requires a spectrum analyzer and a computer, featuring fast setups, accurate results and low cost. Not like the conventional methods using extra assistant circuits to get rid of the frequency drift problem, this approach takes advantage of modern spectrum analyzers to acquire IQ data to calculate phase noise. The low quantization noise of the instrument makes this approach suitable for most CMOS integrated oscillators. The IQ data sampling time can be made small enough so that the frequency drift is not so obvious to harm the measurement accuracy. The experimental results clearly demonstrates the accuracy and the effectiveness of this method through measuring phase noise of two voltage controlled oscillators (VCOs) in 180nm CMOS process at 2.6 GHz and 3.0 GHz respectively.

  • 7.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Carlsson, Mats
    Catena Wireless Electronic AB.
    Hedenas, Charlotta
    Catena Wireless Electronic AB.
    Zhou, Dian
    Fudan University.
    Quantitative Comparison of 1/f Noise Upconversion in CMOS LC Oscillators2009In: In the 9th Swedish System-on-Chip Conference, 2009Conference paper (Refereed)
  • 8.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Fudan University.
    Sizing of MOS device in LC-tank oscillators2007In: 2007 Norchip, 2007, p. 90-95Conference paper (Refereed)
    Abstract [en]

    Since previous publications show conflicting results about sizing device, relationship between device size and 1/f(2) phase noise is studied and closed-form equations are derived in order to help designers to size devices in LC-tank oscillators for good phase noise performance. The analysis is divided into two steps. Firstly, periodic noise transfer functions of each VCO noise source to the output of switch FETs are derived, and the impact of sizing on these functions is discussed. Secondly, phase noise equations are derived with these functions. Experiments show that phase noise predicted by the equations agrees with that from simulations.

  • 9.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Rong, Liang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 5, p. 1154-1164Article in journal (Refereed)
    Abstract [en]

    An improved architecture of polar transmitter (TX) is presented. The proposed architectureis digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phasemodulation, a 1-bit low-pass delta sigma (Delta Sigma) modulator for envelop modulation, and aH-bridge class-D power amplifier (PA) for differential signaling. The (Delta Sigma) modulator isclocked using the phase modulated RF carrier to ensure phase synchronization between theamplitude and phase path, and to guarantee the PA is switching at zero crossings of theoutput current.An on chip pre-filter is used to reduce the parasitic capacitance from packages at theswitch stage output. The high over sampling ratio of the (Delta Sigma) modulator move quantizationnoise far away from the carrier frequency, ensuring good in-band performance and relax filterrequirements. The on-chip filter also acts as impedance matching and differential to singleended conversion. The measured digital transmitter consumes 58 mW from a 1 V at 6.8 dBm output power.

  • 10.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Rong, Liang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator2011In: Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, IEEE , 2011, p. 1-4Conference paper (Refereed)
    Abstract [en]

    A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm2. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.

  • 11. Feng, Chien-Hsiung
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ismail, Mohammed
    Olsson, Håkan
    Analysis of Non-linearities in rf CMOS Amplifiers ICECS1999In: Proc. The 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, p. 137-140Conference paper (Refereed)
  • 12. Jonsson, Fredrik
    A frequency synthesizer and a method for synthesizing a frequency2000Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    This invention relates to a method of synthesizing a frequency by means of a frequency synthesizer comprising a local oscillator, which generates an output signal, a phase locked loop, which provides a control signal to the local oscillator, and a frequency divider, which divides the frequency of said output signal and provides a frequency divided input signal to the phase locked loop, wherein the method comprises the steps of: providing, in a receiving mode, said output signal to a receiver for tuning thereof; locking, by means of said phase locked loop, the frequency of said output signal to a channel frequency of a channel to be received; and turning off said phase locked loop when said output signal frequency is locked to said channel frequency and keeping the phase locked loop off during a following receive cycle. The invention also relates to a frequency synthesizer and a transceiver respectively, for performing the method.

  • 13.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Design and Calibration of integrated PLL Frequency Synthesizers2008Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical PLL implementations suffer from unwanted frequency components such as phasenoise and spurious tones, and since these components affect system performance they must be predicted and minimized.

    This thesis discuss the design and implementation of fully integrated PLL circuits. Techniques to predict system performance are investigated. The strongly non-linear operation of PLL building blocks are analyzed, using both analytical and numerical methods. Techniques to reduce impact of interferer down-conversion and noise folding are suggested. Methods to perform automatic calibration in order to make circuits less sensitive to process variations are proposed. The techniques are verified through a number of PLL implementations.

    The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510 MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and their impact on over all system performance are analyzed. The combined integrated phase noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better than 2.5 dB in both the 2.4 and 5 GHz bands.

    A low power frequency synthesizer targeting Frequency Shift Keying applications such as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation of the carrier, but unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. This allows the use of a small area on-chip loop filter without violating noise or spurious requirements. To handle the frequency drift normally associated with open-loop implementations, a low-leakage charge-pump is proposed. The synthesizer is implemented using a 0.18μm CMOS process. Total power consumption is 9 mW and the circuit area including the VCO inductors and on-chip loopfilter is 0.32mm2. Measured leakage current is less than 2 fA.

    A small area amplitude detector circuit is proposed. The wide-band operation and small input capacitance make the circuit suitable for embedding in an RF system on-chip, allowing measurement of on-chip signal levels and automatic calibration.

    Finally an oscillator topology reducing the phase noise in voltage controlled oscillators is suggested. By using on-chip decoupling and an amplitude control circuit to adjust oscillator bias, the impact of current source noise is eliminated. The theoretical phase noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias current.

  • 14. Jonsson, Fredrik
    Kvadraturfasstyrslinga2002Patent (Other (popular science, discussion, etc.))
  • 15. Jonsson, Fredrik
    Laddningspump av lågläckagetyp2002Patent (Other (popular science, discussion, etc.))
  • 16. Jonsson, Fredrik
    Prescaler innefattande en pulssväljarkrets; plussväljarkrets samt frekvenssyntesator2000Patent (Other (popular science, discussion, etc.))
  • 17.
    Jonsson, Fredrik
    KTH.
    Voltage Controlled Oscillator2001Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    This invention relates to an integrated circuit voltage controlled oscillator comprising a resonator circuit; an amplifier circuit connected to said resonator circuit; a first input terminal; and anoutput terminal. The amplifier and resonator circuits are arranged as a differential circuit having a first and as econd branch. The resonator circuit comprises a variable capacitance circuit and an inductance circuit connecte to an interacting with said variable capacitance circuit. The input terminal is provided at a first balanced input node of said variable capacitance circuit between said first and second branches. The capacitance of at least a part of said variable capacitance circuit, and the frequency of an output signal at said input terminal. The capacitance circuit comprises a first pair of varaible capacitance units being DC isolated and being connected to said balanced input node and to said first and second branches respectively.

  • 18.
    Jonsson, Fredrik
    et al.
    Spirea AB.
    et al.,
    A Single Chip 802.11 a/b/g WLAN Transceiver2004In: 22nd Norchip Conference: Oslo; 8 November 2004 through 9 November 2004, 2004, p. 233-236Conference paper (Refereed)
    Abstract [en]

    A dual-band triple mode radio compliant with the IEEE 802.11 a/b/g standard implemented in a 0.18 μm CMOS process is presented. The transceiver is compatible with a large number of basebands due to its flexible interface towards AD / DA converters and on-chip automatic calibration of on-chip filters and oscillators. The transceiver achieves a receiver noise figure of 4.9/5.6dB for the 2.4GHz/5GHz bands, respectively, and a minimum transmit error vector magnitude (EVM) of 2.5% for both bands. A quadrature accuracy of 0.3° in phase and 0.05dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a better than -34dBc total integrated phase noise. The chip passes ±2kV human body model ESD testing on all pins, including the RF pins. The total die area is 12mm2. The power consumption is 207mW in the receive mode and 247mW in the transmit mode using a 1.8V supply.

  • 19.
    Jonsson, Fredrik
    et al.
    Spirea AB.
    et al.,
    A single-chip CMOS transceiver for 802.11a/b/g wireless LANs2004In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 39, no 12, p. 2250-2258Article in journal (Refereed)
    Abstract [en]

    A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-mum CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3degrees in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes +/-2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm(2). The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.

  • 20.
    Jonsson, Fredrik
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Olsson, Håkan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A low-leakage open-loop frequency synthesizer allowing small-area on-chip loop filter2009In: IEEE Transactions on Circuits and Systems II: Express Briefs, ISSN 1549-7747, Vol. 56, no 3, p. 195-199Article in journal (Refereed)
    Abstract [en]

    A frequency synthesizer targeting low-power packet-based frequency-shift-keying (FSK) applications using open-loop modulation of the oscillator is presented. Unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. It is, therefore, possible to use a wide loop-filter bandwidth without violating the noise or spurious requirements. A wideband loop-filter can be implemented using small component values, allowing an on-chip loop filter. To handle the frequency drift associated with open-loop implementations, a low-leakage charge pump is proposed. The synthesizer is implemented using a 0.18-mu m CMOS process. The total power consumption is 9 mW, and the circuit area including the voltage-controlled oscillator (VCO) inductors and on-chip loop-filter is 0.32 mm(2). The measured frequency drift indicates a leakage current of below 2 fA.

  • 21.
    Jonsson, Fredrik
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Olsson, Håkan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A quadrature oscillator using simplified phase and amplitude calibration2008In: 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008: Seattle, WA; 18 May 2008 through 21 May 2008, 2008, p. 992-995Conference paper (Refereed)
    Abstract [en]

    A quadrature oscillator using automatic calibration of phase and amplitude is presented. It is shown that phase errors in a quadrature oscillator will create an amplitude difference between the outputs. The proposed calibration scheme use on-chip amplitude detectors connected in a negative feedback loop to detect and compensate these amplitude differences. The calibration scheme can be implemented using small chip area and low current consumption compared to other calibration schemes. A quadrature oscillator using the proposed calibration is simulated using a 0.18 mu m CMOS process to verify the feasibility of the proposed method.

  • 22.
    Jonsson, Fredrik
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Olsson, Håkan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Folding of Noise and Interferers in PLL Charge-Pumps2007Article in journal (Other academic)
  • 23.
    Jonsson, Fredrik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    RF detector for on-chip amplitude measurements2004In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 40, no 20, p. 1239-1241Article in journal (Refereed)
    Abstract [en]

    A novel on-chip amplitude detector that allows for efficient debugging of complex RF circuits is proposed. The simplicity, low power consumption, flat frequency response, minimal loading of the tested circuit and possibility of multiplexing makes this detector suitable for on-chip RF amplitude measurements. Simulations and measurements confirm the detector operation.

  • 24.
    Jonsson, Fredrik
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Olsson, Håkan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Techniques to Reduce Folding of Noise and Interferers in PLL Charge-Pump2008In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008Conference paper (Refereed)
    Abstract [en]

    Due to its strongly non-linear operation, charge-pump Phase Locked Loops (PLL) suffer from folding of noise and interferers. Analysis and methods reducing this effect are scarce. We analyze and propose firstly band-limiting the charge pump currents and secondly carefully selecting the minimum phase detector pulse width to eliminate specific interferers. A PLL has also been measured confirming the predicted results. Measured improvements are typically 5 dB and 20 dB for the two methods, respectively.

  • 25.
    Jonsson, Fredrik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sandén, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Elnaggar, Mohammed Ismail
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A Voltage Controlled Oscillator with Automatic Amplitude Control in SiGe Technology2001In: 19th Norchip: Kista 12-13 November 2001, 2001, p. 28-33Conference paper (Refereed)
  • 26.
    Jue, Shen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li-Rong, Zheng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jun, Yu
    Non-linear Quantization Effects and Impacts on Phase Noise of Integer-N ALL Digital Phase Locked-Loop2011In: China Journal, ISSN 1324-9347, E-ISSN 1835-8535Article in journal (Refereed)
  • 27. Li, Xiaopeng
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Olsson, Håkan
    Ismail, Mohammed
    A High-Speed Low-Power architecture for GHz CMOS Dual-Modulus Prescaler2000In: Proc. International Analog VLSI Workshop, IEEJ, 2000, p. 6-9Conference paper (Refereed)
  • 28.
    Mao, Jia
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mismatch aware power and area optimization of successive-approximation ADCs2010In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, 2010, p. 882-885Conference paper (Other academic)
    Abstract [en]

    In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and process mismatch information into account, it is able to minimize power dissipations by reducing the size of the unit capacitor area without dynamic range degradation due to capacitor mismatch. As a case study, a low power 12 bits SAR ADC has been designed in 0.18 #x03BC;m CMOS process, with 1-100 kHz sample rate.

  • 29.
    Mao, Jia
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sarmiento M., David
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhou, Qin
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Jian
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Wang, Peng
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A 90nm CMOS UHF/UWB asymmetric transceiver for RFID readers2011In: European Solid-State Circuits Conference, 2011, p. 179-182Conference paper (Other academic)
    Abstract [en]

    This paper presents an integrated asymmetric transceiver in 90nm CMOS technology for RFID reader. The proposed reader uses UHF transmitter to power up and inventory the tags. In the reverse link, a non-coherent Ultra-wide Band (UWB) receiver is deployed for data reception with high throughput and ranging capability. The transmitter delivers 160 kb/s ASK modulated data by an integrated modulator and a Digital Controlled Oscillator (DCO) in UHF band with 11% tuning range. The DCO consume 6 mW with 0.12 mm2 area. On the other side, adopting two integration channels, the 3-5 GHz energy detection receiver supports maximum 33 Mb/s data rate both in OOK and PPM modulations. The receiver front-end provides 59 dB voltage gain and 8.5 dB noise figure (NF). Measurement results shows that the receiver achieves an input sensitivity of -79 dBm at 10 Mb/s, with power consumption of 15.5 mW.

  • 30.
    Mao, Jia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mendoza Sarmiento, David
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications2012In: NORCHIP, 2012, IEEE , 2012, p. 6403099-Conference paper (Refereed)
    Abstract [en]

    This paper presents a 3-5 GHz, high output amplitude, carrier-less based Ultra Wideband (UWB) transmitter for wirelessly powered RFID application. The UWB transmitter consists of a baseband pulse generator, a driver amplifier and an output on-chip filter. The baseband pulse generator and the driver amplifier are designed as zero DC power consuming circuit, which enables scalable power with the pulse rate. IC pad and bonding wire parasitics are considered to be absorbed as part of output filtering network, realizing package co-design. The simulation result shows that the proposed transmitter radiates 2.34 pJ/pulse energy with 1.63 V pulse amplitude. The total energy consumption under 1.8 V power supply is 18 pJ/pulse, corresponding to 13% energy efficiency.

  • 31.
    Mäntysalo, Matti
    et al.
    TUT.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Feng, Yi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Cabezas, Ana Lopez
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    System integration of smart packages using printed electronics2012In: Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, IEEE , 2012, p. 997-1002Conference paper (Refereed)
    Abstract [en]

    The last decade has shown enormous interest in additive and printed electronics manufacturing technologies, especially in intelligent packaging. Scientists and engineers all over the world are developing printed organic circuits. Despite their effort, the performance and yield of all-printed devices cannot replace silicon-based devices in smart package applications. Therefore, we have developed a hybrid interconnection platform to seamlessly integrate printed electronics with silicon-based electronics, close the gap between the two technologies, and to anticipate adaption of printed electronic technologies. We studied the suitability of a printed interconnection platform by fabricating a printed sensor-box that contains printed nano-Ag-interconnections on low-temperature plastic, a printable humidity sensor based on functionalized MWCNTs, a printed battery, conventional SMDs, and a silicon-based MCU.

  • 32.
    Rong, Liang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    A 11.4dBm 90nm CMOS H-Bridge Resonating Polar Amplifier using RF Sigma Delta Modulation2011In: Proceedings of the ESSCIRC (ESSCIRC), 2011, IEEE , 2011, p. 307-310Conference paper (Refereed)
    Abstract [en]

    Using RF Sigma Delta Modulation (RFSDM), aclass-D polar amplifier in H-Bridge configuration can work in resonatingmode and minimize the switching loss for high efficiencypolar transmitters. The high oversampling ratio envelop bitstream created by the low pass RFSDM is phase modulated anddigitally mixed with quantized RF carrier to give a modulatedRF digital signal. By taking the advantage of high speed andaccurate digital CMOS process, this ’information combination’architecture can achieve high efficiency and reduce the need forexternal filter components. A polar power amplifier based on thisconcept is implemented in 90nm CMOS process and achieved apeak output power of 11.4dBm with 19.3% efficiency at 1.0Vpower supply. The total area is 0.72mm2 including an on-chipfilter matching network designed for 2.4GHz to 2.7GHz band.

  • 33.
    Rong, Liang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Switch Mode Resonating H-Bridge Polar Transmitter using RF Sigma Delta Modulation2010In: IEEE INT SYMP CIRC SYST PROC, 2010, p. 1911-1914Conference paper (Refereed)
    Abstract [en]

    Using saturated power amplifier (PA) as the last stage, polar transmitter has the potential to be the most power efficient architecture to transmit large Peak-to-Average Ratio (PAR) signals. In this work, a polar transmitter using H-Bridge configured Class-D amplifiers is proposed. To fully exploit low voltage resource, maintain linearity and meet the spectrum mask requirements, RF Sigma-Delta Modulation (SDM) is used. An on-chip transformer based filter network is designed to filter out SDM noise and provide load matching. The system verification is carried out by using Matlab passband simulation on a 13dB PAR mobile WiMAX signal. Evaluation of noise shaping and spectral regrowth shows the proposed architecture can achieve -45dBc/10kHz ACPR in a 140MHz bandwidth range. This provides a solid ground for the circuit design work.

  • 34.
    Rong, Liang
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Carlsson, M
    Catena Wireless AB.
    Hedenas, C
    Catena Wireless AB.
    High Efficiency RF Transmitter System Architecture Investigation for Mobile WiMAX Applications2008Manuscript (preprint) (Other academic)
    Abstract [en]

    Wireless broadband digital communicationsystems are facing more and more critical power efficiencyproblems. Crest Factor (PAPR) is reported to be in 10-12dBrange for WiMAX 802.16e systems implementing OFDMIFFT-1024 and 64-QAM modulation. In this work,outphasing (LINC) and Polar transmitter architectures areinvestigated and compared with Direct Conversionarchitecture. Complete system solution targeting 23dBmoutput power is evaluated. Simulation result shows LINCconsumes more power than DC if non-clipping modulationscheme used and its complete system efficiency may not be ashigh as expected when linear combiner used. And polarsystem has stringent 3 degree phase matching and 0.5dB gainmatching requirements constrained by RCE and spectrummask specifications.

  • 35.
    Rong, Liang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Carlsson, Mats
    Hedenas, Charlotta
    RF Transmitter Architecture Investigation for Power Efficient Mobile WiMAX Applications2008In: 2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi J, Takala J, Vainio O, NEW YORK: IEEE , 2008, p. 114-117Conference paper (Refereed)
    Abstract [en]

    Wireless broadband digital communication systems with high spectral efficiency suffer from severe power efficiency problem. Peak-to-Average Power Ratio is reported up to 12dB for WiMAX 802.16e systems implementing OFDM IFFT-1024 and 64-QAM modulation. In this work, outphasing (LILAC) and polar transmitter architectures are investigated and compared with direct conversion (DC) architecture. Complete system solution targeting 23dBm output power is evaluated. System level simulation result shows that, with linear power combiner, LILAC consumes more power than DC if non-clipping modulation scheme used. And polar system has stringent 3 degree phase matching and 0.5dB gain matching requirements to meet EVM and spectrum mask specifications.

  • 36. Sanden, Martin
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Östling, Mikel
    Marinov, O.
    Deen, M. Jamal
    Up-Conversion of Device 1/f Noise to Phase Noise in Voltage Controlled Oscillators2001In: Proc 16th International Conference on Noise in Physical Systems and1/f Fluctuations, ICNF, 2001, p. 449-502Conference paper (Refereed)
  • 37.
    Sarmiento M., David
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhou, Qin
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Wang, Peng
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Analog front-end RX design for UWB impulse radio in 90nm CMOS2011In: 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, 2011, p. 1552-1555Conference paper (Refereed)
    Abstract [en]

    In this paper a reconfigurable differential Ultra Wideband-Impulse Radio (UWB-IR) energy receiver architecture has been simulated and implemented in UMC 90nm. The signal is amplified, rectified and integrated. By using an integration windowed scheme the SNR requirements are relaxed increasing the sensitivity. The design has been optimized for large bandwidths, low implementation area and configurability. The RX can be adapted to work at different data rates, processing gains, and channel environments. It works between the 3.1-4.8 GHz bands with OOK or PPM modulation with a tunable data rate up to 33Mb/s. In order to relax the ADC sampling time an interleave mode of operation has been implemented. It has a maximum power consumption of 22m W with a power supply of 1V. The complete RX occupies an area of 1.11mm2.

  • 38.
    Shen, Jue
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Jian
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University, China.
    Phase noise improvement and noise modeling of type-I ADPLL with non-linear quantization effects2015In: NORCHIP 2014 - 32nd NORCHIP Conference: The Nordic Microelectronics Event, IEEE conference proceedings, 2015Conference paper (Refereed)
    Abstract [en]

    This paper presents a phase noise improvement method for fine tuning of type-I ADPLL by exploiting its nonlinear quantization effects. When quantization step approaches the same orders of magnitude of standard deviation of input noise, quantization effects become nonlinear, and additive noise modeling of quantization effects is no longer applicable. By proper offsetting the input signals in this case, the feedback loop of ADPLL can be very sensitive to frequency phase deviation. It results in a larger loop bandwidth, and in turn smaller in-band phase noise than in linear quantization case. A theoretic s-domain noise model is proposed to quantify the phase noise in nonlinear case. Results are verified in Modelsim simulations. Proposed method offers possibility of achieving lower phase noise by lower quantization resolution and less circuit design efforts.

  • 39.
    Shen, Jue
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Intelligent Packaging with Inkjet-Printed Electrochromic Paper Display –A Passive Display Infotag2012In: NIP28 : 28th international conference on digital printing technologies : technical program and proceedings : Digital fabrication 2012 : September 9-13, 2012, Quebec City, Quebec, Canada., The Society for Imaging Science and Technology, 2012, p. 164-167Conference paper (Refereed)
    Abstract [en]

    In this paper, we study the electronic performance of the inkjet-printed electrochromic (EC) display which uses Poly (3,4-ethylenedioxythiophene) (PEDOT) doped with poly (styrenesulfonate) (PSS) as the active material, and extract its equivalent RC model. Results show that by charging PEDOT:PSS with 1.8V for averagely 10s, it can be switched from transparent (oxidation state) to blue (reduced state) and keeps the color for an average of 300s in the absence of energy supply, consuming much lower power than other flexible display technologies. However, it suffers from significant crosstalk effects in passive-matrix addressing and from performance variation as sample changes or time goes on. Based on the results, we design a programmable digital display driver with two different operation modes, and analyze the feasibility to integrate such display function in passive intelligent packaging systems. System simulation results prove it as a promising solution from evaluation of power budget and driving ability with printed interconnections and offchip conductors.

  • 40.
    Wang, Peng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Fudan University, China.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Low Noise Amplifier Architecture Analysis for OFDM-UWB System in 0.18 um CMOS2008In: 26th Norchip Conference, Norchip, 2008, p. 184-189Conference paper (Refereed)
    Abstract [en]

    This paper analyzes architectures of the low noise amplifier (LNA) for orthogonal-frequency-division-multiplexing ultra-wideband (OFDM-UWB) application. Until now, most UWB LNA implementations are focusing how to realize a single LNA covering the whole frequency band. In this work three popular wide-band LNA architectures are compared to a proposed parallel LNA architecture in which different amplifiers cover different frequency bands. Our study reveals that by reusing the source degenerated inductor between the different frequency bands, the parallel LNA architecture can achieve better performance than the single wide-band LNA (S11<-10 dB, voltage gain >15 dB, NF >4.5 dB, power consumption <10 mW) at the expense of a slightly increased circuit area.

  • 41.
    Wang, Peng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A novel low-power fully-differential current-reuse cascaded CG-CS-LNA for 6-9-GHz UWB receivers2010In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, 2010, p. 1188-1191Conference paper (Refereed)
    Abstract [en]

    This paper proposes a novel low-power fully-differential ultra-wideband (UWB) low noise amplifier (LNA) for 6-9-GHz UWB receivers in digital 90nm CMOS. The capacitive cross-coupled common-gate (CG) stage is cascaded with a cross-coupled common-source (CS) second stage to perform the wideband input impedance matching, low noise figure (NF), low power, and flat-high-wideband gain which is due to the stagger tuning amplification. The DC power consumption is further reduced by the current-reuse topology. The simulation results achieve the minimum NF of 2.55dB, maximum voltage gain of 24.8dB with 3-dB bandwidth of 6-9-GHz, and IIP3 of 3.57dBm at 9GHz. The return loss is less than -12dB in the desired band because of the CG stage as the input stage. The proposed UWB LNA consumes 2.3mW core DC power at 1V supply voltage.

  • 42.
    Wang, Peng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Low Noise Amplifier Architecture Analysis for UWB System2008In: 2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi J, Takala J, Vainio O, NEW YORK: IEEE , 2008, p. 53-56Conference paper (Refereed)
    Abstract [en]

    This paper analyzes the architecture of wideband low noise amplifier (LNA) for multi-band orthogonal frequency division multiplexing modulation (MB-OFDM) ultra-wideband (UWB) system. Noise matching and input impedance matching are compared among different LNA architectures. Power consumption and area for different kinds of LNA architectures are also compared through the figure of merit (FOM).

  • 43.
    Wang, Peng
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Sarmiento Mendoza, David
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A 3.1-4.8-GHz energy-detector front-end for non-coherent OOK impulse-radio UWB2010In: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, p. 485-488Conference paper (Refereed)
    Abstract [en]

    This paper proposes a 0-33.3Mb/s front-end of the energy detector for 3.1-4.8-GHz impulse-radio ultra-wideband (IR-UWB). Fully differential architecture with the non-coherent on-off-keying (OOK) modulation is adopted. Targeting at - 98dBm sensitivity, the low noise amplifier (LNA) is designed to achieve <3.5dB noise figure, <-10dB S11, and >15dB gain. Interleaved integrating scheme relaxes the implementation of digital circuits. Thanks to the duty-cycling, the front-end achieves 420pJ/bit energy efficiency for OOK modulation. The bias is generated by band-gap circuits. The layout design and verification are completed with Cadence Spectre using UMC 90nm CMOS.

  • 44. Westman, Fredrik
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Tommy
    Hedqvist, Christer
    Hemani, Ahmed
    A Robust CMOS Bluetooth Radio/Modem System-on-Chip2002In: IEEE Circuit and Systems Magazine, p. 7-9Article in journal (Refereed)
  • 45. Wu, Yue
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kim, Hong-Sun
    Ismail, Mohammed
    Olsson, Håkan
    Analysis of Non-linearities of CMOS Low Noise Amplifier1999In: Proc. 17th Norchip Conference, 1999, p. 189-196Conference paper (Refereed)
  • 46. Wu, Yue
    et al.
    Kim, Hong-Sun
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ismail, Mohammed
    Olsson, Håkan
    Nonlinearity Analysis of a Short Channel CMOS Circuit for RF IC Applications1999In: Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration:Systems on a Chip, Kluwer Academic Publishers, 1999, p. 61-68Conference paper (Refereed)
  • 47.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mantysalo, Matti
    TUT.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Feng, Yi
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lopez, Ana
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Inkjet Printing in System Integration: Printed Humidity Sensor-Box2012In: 2012 Flexible Electronics & Displays Conference, 2012Conference paper (Refereed)
  • 48.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mäntysalo, Matti
    TUT.
    Lopez, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Feng, Yi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Electrical performance and reliability evaluation of inkjet-printed Ag interconnections on paper substrates2012In: Materials letters (General ed.), ISSN 0167-577X, E-ISSN 1873-4979, Vol. 88, p. 68-72Article in journal (Refereed)
    Abstract [en]

    Printing technology, especially inkjet printing, enables mass manufacturing of electronics on various substrate materials. Paper is one potential carrier for printed electronics to realize low-cost, flexible, recyclable smart packages. However, concerns exist regarding commonly used photo paper substrate, in terms of price and reliability against environmental variation. In this work, for the first time, ordinary low-cost and high-moisture-resistance package paper is investigated as an alternative to be the substrate of printed electronics. The surface morphology and electrical performance of inkjet printed interconnections on six different paper substrates from two categories (inkjet paper and package paper) are examined and compared. The printed interconnections on inkjet papers show smaller sheet resistance and better repeatability than those on package papers. However, low-cost package paper stands higher temperature and exhibits better reliability during 85°C/85 RH aging test. Package paper is suitable for smart package applications that have relaxed requirements of conductivity and high requests of moisture resistance.

  • 49.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shen, Jue
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Co-design of flip chip interconnection with anisotropic conductive adhesives and inkjet-printed circuits for paper-based RFID tags2011In: 2011 61st Electronic Components and Technology Conference, ECTC 2011, IEEE conference proceedings, 2011, p. 1752-1757Conference paper (Other academic)
    Abstract [en]

    In this paper we study the radio frequency performance of interconnect using anisotropic conductive film (ACF). A series of experiments are conducted in order to measure and model the electrical characteristics of inkjet-printed circuits on paper substrate as well as the impedance parameters of ACF interconnect at high frequency. Four-point measurement structure, time domain reflectometry (TDR), vector network analyzer (VNA) and de-embedded technology are used to ensure the accuracy of experiments. Equivalent circuit models are built based on the experimental results. Finally, these models are considered as parts of the matching network and circuit design for the RFID receiver, which can be co-designed for developing paper-based electronic systems. It is found that since the difference between RFID tags with and without ACF interconnects is negligible, the influence of ACF interconnects can be ignored for paper-based UHF RFID tag. ACF is a feasible interconnect material for paper-based RFID tags.

  • 50.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mantysalo, Matti
    TUT.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A system-on-chip and paper-based inkjet printed electrodes for a hybrid wearable bio-sensing system2012In: Engineering in Medicine and Biology Society (EMBC), 2012 Annual International Conference of the IEEE, IEEE , 2012, p. 5026-5029Conference paper (Refereed)
    Abstract [en]

    This paper presents a hybrid wearable bio-sensing system, which combines traditional small-area low-power and high-performance System-on-Chip (SoC), flexible paper substrate and cost-effective Printed Electronics. Differential bio-signals are measured, digitized, stored and transmitted by the SoC. The total area of the chip is 1.5 × 3.0 mm2. This enables the miniaturization of the wearable system. The electrodes and interconnects are inkjet printed on paper substrate and the performance is verified in in-vivo tests. The quality of electrocardiogram signal sensed by printed electrodes is comparable with commercial electrodes, with noise level slightly increased. The paper-based inkjet printed system is flexible, light and thin, which makes the final system comfortable for end-users. The hybrid bio-sensing system offers a potential solution to the next generation wearable healthcare technology.

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