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  • 1.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Edholm, Jonas
    Lu, J.
    Uppsala University, Ångström Laboratory.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A robust spacer gate process for deca-nanometer high-frequency MOSFETs2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 3, p. 434-439Article in journal (Refereed)
    Abstract [en]

    This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

  • 2.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    Zha, Chaolin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Dongping
    Lu, Jun
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hultman, Lars
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1-xPtx silicide films2010In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 96, no 3Article in journal (Refereed)
    Abstract [en]

    The formation of ultrathin silicide films of Ni1-xPtx at 450-850 degrees C is reported. Without Pt (x=0) and for t(Ni)< 4 nm, epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 degrees C. For t(Ni)>= 4 nm, polycrystalline NiSi films form and agglomerate at lower temperatures for thinner films. Without Ni (x=1) and for t(Pt)=1-20 nm, the annealing behavior of the resulting PtSi films follows that for the NiSi films. The results for Ni1-xPtx of other compositions support the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability.

  • 3.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interaction of NiSi with dopants for metallic source/drain applications2010In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 28, no 1, p. C1I1-C1I11Article in journal (Refereed)
    Abstract [en]

    This work has a focus on NiSi as a possible metallic contact for aggressively scaled complementary metal oxide semiconductor devices. As the bulk work function of NiSi lies close to the middle of Si bandgap, the Schottky barrier height (SBH) of NiSi is rather large for both electron (similar to 0.65 eV) and hole (similar to 0.45 eV). Different approaches have therefore been intensively investigated in the literature aiming at reducing the effective SBH: dopant segregation (DS), surface passivation (SP), and alloying, in order to improve the carrier injection into the conduction channel of a field-effect transistor. The present work explores DS using B and As for the NiSi/Si contact system. The effects of C and N implantation into Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. A combined use of DS or SP with alloying could be considered for more effective control of effective SBH, but an examination of undesired compound formation and its probable consequences is necessary. Furthermore, an analysis of the metal silicides that have a small "intrinsic" SBH reveals that only a very small number of them are of practical interest as most of the silicides require either a high formation temperature or possess a high specific resistivity.

  • 4.
    Qiu, Zhijun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 1, p. 396-403Article in journal (Refereed)
    Abstract [en]

    An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SUDS is relatively simple in processing, but the silicidation process is dopant-dependent, leading to local variations of silicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation.

  • 5.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of silicide nanowires as Schottky barrier source/drain in FinFETs2008Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices.

    First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts.

    Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp).

    Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM.

    Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap.

  • 6.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT).
    Lu, Jun
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT).
    A novel self-aligned process for platinum silicide nanowires2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 11-12, p. 2107-2111Article in journal (Refereed)
    Abstract [en]

    Directly accessible, ultralong, uniform platinum silicide nanowires in PtSi and Pt2Si are mass-fabricated by combining a sidewall transfer lithography (STL) technology and a self-aligned silicide process. The STL technology is based on standard Si technology. The self-aligned platinum silicide (PtSix) process consists of two sequential steps in a single run: a silicidation step in N-2 to ensure a controllable silicide formation followed by an oxidation step in O-2 to form a reliable protective SiOx layer on top of the grown PtSix. The achieved nanowires are characterised by a low resistivity: 26 +/- 3 and 34 +/- 2 mu Omega cm for the Pt2Si- and PtSi-dominated nanowires.

  • 7.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ni2Si nanowires of extraordinarily low resistivity2006In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 21, p. 213103-Article in journal (Refereed)
    Abstract [en]

    Ultralong, polycrystalline Ni2Si nanowires are fabricated by combining sidewall transfer lithography with self-aligned silicidation. Upon formation at 500 degrees C, the nanowires that are 400 mu m long with a rectangular cross section of 37.5 by 25.3 nm are characterized by a resistivity of 25 +/- 1 mu Omega cm which is similar to the value for Ni2Si thin films. Further annealing at 800 degrees C results in an extraordinarily low wire resistivity of 10 mu Omega cm. Such a drastic decrease in resistivity is attributed to a significant grain growth and a low density of defects in the nanowires.

  • 8.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Performance fluctuation of FinFETs with Schottky barrier source/drain2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, p. 506-508Article in journal (Refereed)
    Abstract [en]

    A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.

  • 9.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Olsson, Jörgen
    The Ångström Laboratory, Uppsala University.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 1, p. 125-127Article in journal (Refereed)
    Abstract [en]

    MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.

  • 10.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Liu, Ran
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schottky-barrier height tuning by means of ion implantation into preformed silicide films followed by drive-in anneal2007In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 7, p. 565-568Article in journal (Refereed)
    Abstract [en]

    An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to similar to 1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV The process window for the most pronounced SBH modification is dopant dependent.

  • 11.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Robust, scalable self-aligned platinum silicide process2006In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 14, p. 142114-Article in journal (Refereed)
    Abstract [en]

    A robust, scalable PtSix process is developed. The process consists of two consecutive annealing steps in a single run; the first is silicidation of Pt films on Si substrates carried out in N-2, whereas the second is surface oxidation of the resultant PtSix in O-2. By adequately adjusting the temperature during the oxidation step, a protective SiOx hard mask forms on PtSix of different thicknesses and compositions. Such a surface oxidation is absent for Pt on SiO2 isolation, which is crucial for the subsequent selective wet etch for a self-aligned process. Ultralong PtSix nanowires are fabricated using this robust self-aligned process.

  • 12.
    Zhang, Zheng
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Electrically robust ultralong nanowires of NiSi, Ni2Si and Ni31Si122006In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 88, no 4, p. 043104-Article in journal (Refereed)
    Abstract [en]

    Mass fabrication of directly accessible, ultralong, uniform Si nanowires is realized by employing a controllable and reproducible method based on standard Si technology. High-conductivity polycrystalline Ni-silicide nanowires around 30 nm by 30 nm in cross section, able to support extremely high currents at similar to 10(8) A/cm(2), are obtained by means of solid-state reaction of the Si nanowires with subsequently deposited Ni films. By properly adjusting the Ni film thickness, NiSi, Ni2Si, and Ni31Si12 nanowires characterized with distinct resistivity and temperature coefficient of resistance are obtained. Upon annealing, the electrical continuity of the nanowires breaks at temperatures about 0.7 times the melting points of the silicides.

  • 13.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gudmundsson, Valur
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Towards Schottky-Barrier Source/Drain MOSFETs2008In: 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 / [ed] Yu M, An X, NEW YORK: IEEE , 2008, p. 146-149Conference paper (Refereed)
    Abstract [en]

    This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of silicide growth. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. In the past two years several groups have demonstrated high-performance SB MOSFETs, which places the technology as a promising candidate for future generations of CMOS technology.

  • 14.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellstrom, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shili
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Device integration issues towards 10 nm MOSFETs2006In: 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, NEW YORK, NY: IEEE , 2006, p. 25-30Conference paper (Refereed)
    Abstract [en]

    An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high K gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO(2)/Al(2)O(3). Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated, Finally ultra thin body Sol devices with high mobility SiGe channels are demonstrated.

1 - 14 of 14
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