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  • 1.
    Behere, Sagar
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Zhang, Xinhai
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.).
    Izosimov, Viacheslav
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Törngren, Martin
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.).
    A Functional Brake Architecture for Autonomous Heavy Commercial Vehicles2016In: SAE 2016 World Congress and Exhibition, sae international , 2016Conference paper (Refereed)
    Abstract [en]

    Heavy commercial vehicles constitute the dominant form of inland freight transport. There is a strong interest in making such vehicles autonomous (self-driving), in order to improve safety and the economics of fleet operation. Autonomy concerns affect a number of key systems within the vehicle. One such key system is brakes, which need to remain continuously available throughout vehicle operation. This paper presents a fail-operational functional brake architecture for autonomous heavy commercial vehicles. The architecture is based on a reconfiguration of the existing brake systems in a typical vehicle, in order to attain dynamic, diversified redundancy along with desired brake performance. Specifically, the parking brake is modified to act as a secondary brake with capabilities for monitoring and intervention of the primary brake system. A basic fault tree analysis of the architecture indicates absence of single points of failure, and a reliability analysis shows that it is reasonable to expect about an order of magnitude improvement in overall system reliability. Copyright © 2016 SAE International.

  • 2. Eles, P.
    et al.
    Izosimov, Viacheslav
    Dept. of Computer and Information Science, Linköping University, SE-581 83 Linköping, Sweden.
    Pop, P.
    Peng, Z.
    Synthesis of Fault-Tolerant Embedded Systems2008In: Proceedings -Design, Automation and Test in Europe, DATE, 2008, 1117-1122 p.Conference paper (Refereed)
    Abstract [en]

    This work addresses the issue of design optimization for fault-tolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated system synthesis approaches decide the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors, such that multiple transient faults are tolerated, transparency requirements are considered, and the timing constraints of the application are satisfied.

  • 3.
    Izosimov, Viacheslav
    et al.
    Semcon AB, EIS, Linkoping, Sweden.
    Di Guglielmo, G.
    Lora, M.
    Pravadelli, G.
    Fummi, F.
    Peng, Z.
    Fujita, M.
    Time-Constraint-Aware Optimization of Assertions in Embedded Software2012In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 28, no 4, 469-486 p.Article in journal (Refereed)
    Abstract [en]

    Technology shrinking and sensitization have led to more and more transient faults in embedded systems. Transient faults are intermittent and non-predictable faults caused by external events, such as energetic particles striking the circuits. These faults do not cause permanent damages, but may affect the running applications. One way to ensure the correct execution of these embedded applications is to keep debugging and testing even after shipping of the systems, complemented with recovery/restart options. In this context, the executable assertions that have been widely used in the development process for design validation can be deployed again in the final product. In this way, the application will use the assertion to monitor itself under the actual execution and will not allow erroneous out-of-the-specification behavior to manifest themselves. This kind of software-level fault tolerance may represent a viable solution to the problem of developing commercial off-the-shelf embedded systems with dependability requirements. But software-level fault tolerance comes at a computational cost, which may affect time-constrained applications. Thus, the executable assertions shall be introduced at the best possible points in the application code, in order to satisfy timing constraints, and to maximize the error detection efficiency. We present an approach for optimization of executable assertion placement in time-constrained embedded applications for the detection of transient faults. In this work, assertions have different characteristics such as tightness, i.e., error coverage, and performance degradation. Taking into account these properties, we have developed an optimization methodology, which identifies candidate locations for assertions and selects a set of optimal assertions with the highest tightness at the lowest performance degradation. The set of selected assertions is guaranteed to respect the real-time deadlines of the embedded application. Experimental results have shown the effectiveness of the proposed approach, which provides the designer with a flexible infrastructure for the analysis of time-constrained embedded applications and transient-fault-oriented executable assertions.

  • 4.
    Izosimov, Viacheslav
    et al.
    Embedded Intell. Solutions (EIS), Semcon AB, Linköping, Swede.
    Eles, P.
    Peng, Z.
    Value-Based Scheduling of Distributed Fault-Tolerant Real-Time Systems with Soft and Hard Timing Constraints2010In: 2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia'10, IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    We present an approach for scheduling of fault-tolerant embedded applications composed of soft and hard real-time processes running on distributed embedded systems. The hard processes are critical and must always complete on time. A soft process can complete after its deadline and its completion time is associated with a value function that characterizes its contribution to the quality-of-service of the application. We propose a quasi-static scheduling algorithm to generate a tree of fault-tolerant distributed schedules that maximize the application's quality value and guarantee hard deadlines.

  • 5.
    Izosimov, Viacheslav
    et al.
    EIS by Semcon AB, Sweden.
    Ingelsson, U.
    Wallin, A.
    Requirement Decomposition and Testability in Development of Safety-Critical Automotive Components2012Conference paper (Refereed)
    Abstract [en]

    2ISO26262 is a recently approved standard for functional safety in road vehicles. It provides guidelines on minimization of unreasonable safety risks during development of embedded systems in road vehicles. However, the development process specified in ISO26262 involves a number of steps that will require changing traditional and well established development processes. In a transition phase, however, due to lack of tool support, the steps may be performed manually, increasing the risk for delays and increased cost. This paper describes a case study in which we have successfully worked with traceability and testability of functional safety requirements, as well as safety requirements assigned to a testing tool that automates integration and verification steps, leading to standard-compliant tool qualification. Our tool qualification method employs fault injection as a validation method to increase confidence in the tool. Our case study will help to avoid many of the new pitfalls that can arise when attempting to realize standard-compliant development.

  • 6.
    Izosimov, Viacheslav
    et al.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Sweden.
    Lora, M.
    Pravadelli, G.
    Fummi, F.
    Peng, Z.
    Di Guglielmo, G.
    Fujita, M.
    Optimization of Assertion Placement in Time-Constrained Embedded Systems2011Conference paper (Refereed)
    Abstract [en]

    We present an approach for optimization of assertion placement in time-constrained HW/SW modules for detection of errors due to transient and intermittent faults. During the design phases, these assertions have to be inserted into the executable code and, hence, will always be executed with the corresponding code branches. As the result, they can significantly increase execution time of a module, in particular, contributing to a much longer execution of the worst case, and cause deadline misses. Assertions have different characteristics such as tightness (or "local error coverage") and execution latency. Taking into account these properties can increase efficiency of assertion checks in time-constrained embedded HW/SW modules. We have developed a design optimization framework, which (1) identifies candidate locations for assertions, (2) associates a candidate assertion to each location, and (3) selects a set of assertions in terms of performance degradation and assertion tightness. Experimental results have shown the efficiency of the proposed techniques.

  • 7.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Polian, I.
    Pop, P.
    Eles, P.
    Peng, Z.
    Analyse und Optimierung von fehlertoleranten Eingebetteten Systemen mit gehärteten Prozessoren2009Conference paper (Refereed)
    Abstract [de]

    Wir stellen einen Ansatz zur Entwurfsoptimierung von fehlertoleranten harten Echtzeitsystemen vor, der Hardware- und Software-Fehlertoleranztechniken kombiniert. Es wird zwischen selektiver Härtung in Hardware und Prozessneuausführungen in Software abgewogen, um benötigte Fehlertoleranz zu geringst möglichen Kosten zu erreichen. Die vorgestellten Entwurfsoptimierungsheuristiken legen die fehlertolerante Architektur und Prozesszuordnung fest, so dass die Systemkosten minimiert, die Deadlines eingehalten und die Zuverlässigkeitsanforderungen erfüllt werden..

  • 8.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Polian, I.
    Pop, P.
    Eles, P.
    Peng, Z.
    Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors2009Conference paper (Refereed)
    Abstract [en]

    In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.

  • 9.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Pop, P.
    Eles, P.
    Peng, Z.
    Design Optimization of Time- and Cost- Constrained Fault-Tolerant Distributed Embedded Systems2005Conference paper (Other academic)
    Abstract [en]

    In this paper we present an approach to the design optimization of fault tolerant embedded systems for safety-critical applications. Processes are statically scheduled and communications are performed using the time-triggered protocol. We use process re-execution and replication for tolerating transient faults. Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

  • 10.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Pop, P.
    Eles, P.
    Peng, Z.
    Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems2006Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safetycritical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable.

     

  • 11.
    Izosimov, Viacheslav
    et al.
    Embedded Intelligent Solut EIS Semcon AB, Sweden.
    Pop, P.
    Eles, P.
    Peng, Z.
    Scheduling and Optimization of Fault-Tolerant Embedded Systems with Transparency/Performance Trade-Offs2012In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 11, no 3, 61Article in journal (Refereed)
    Abstract [en]

    In this article, we propose a strategy for the synthesis of fault-tolerant schedules and for the mapping of fault-tolerant applications. Our techniques handle transparency/performance trade-offs and use the fault-occurrence information to reduce the overhead due to fault tolerance. Processes and messages are statically scheduled, and we use process reexecution for recovering from multiple transient faults. We propose a fine-grained transparent recovery, where the property of transparency can be selectively applied to processes and messages. Transparency hides the recovery actions in a selected part of the application so that they do not affect the schedule of other processes and messages. While leading to longer schedules, transparent recovery has the advantage of both improved debuggability and less memory needed to store the fault-tolerant schedules.

  • 12.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Pop, P.
    Eles, P.
    Peng, Z.
    Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints2008Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarantee the deadlines for the hard processes even in the case of faults, while maximizing the overall utility. We use time/utility functions to capture the utility of soft processes. Process re-execution is employed to recover from multiple faults. A single static schedule computed off-line is not fault tolerant and is pessimistic in terms of utility, while a purely online approach, which computes a new schedule every time a process fails or completes, incurs an unacceptable overhead. Thus, we use a quasi-static scheduling strategy, where a set of schedules is synthesized off-line and, at run time, the scheduler will select the right schedule based on the occurrence of faults and the actual execution times of processes. The proposed schedule synthesis heuristics have been evaluated using extensive experiments.

  • 13.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Pop, P.
    Eles, P.
    Peng, Z.
    Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication2006Conference paper (Other academic)
    Abstract [en]

    We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example

  • 14.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Pop, P.
    Eles, P.
    Peng, Z.
    Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-offs for Distributed Embedded Systems2006Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to the scheduling of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. If process recovery is performed such that the operation of other processes is not affected, we call it transparent recovery. Although transparent recovery has the advantages of fault containment, improved debuggability and less memory needed to store the fault-tolerant schedules, it will introduce delays that can violate the timing constraints of the application. We propose a novel algorithm for the synthesis of fault-tolerant schedules that can handle the transparency/performance trade-offs imposed by the designer, and makes use of the fault-occurrence information to reduce the overhead due to fault tolerance. We model the application as a conditional process graph, where the fault occurrence information is represented as conditional edges and the transparent recovery is captured using synchronization nodes.

  • 15.
    Izosimov, Viacheslav
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Pop, P.
    Eles, P.
    Peng, Z.
    Synthesis of Flexible Fault-Tolerant Schedules for Embedded Systems with Soft and Hard Timing Constraints2010In: Design and Test Technology for Dependable Systems-on-Chip / [ed] R. Ubar, J. Raik, H. T. Vierhaus, IGI Global , 2010Chapter in book (Refereed)
  • 16.
    Izosimov, Viacheslav
    et al.
    Computer and Information Science Dept., Linköping University, Sweden.
    Pop, P.
    Eles, P.
    Peng, Z.
    Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems2008Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach for scheduling with preemption for fault-tolerant embedded systems composed of soft and hard real-time processes. We are interested to maximize the overall utility for average, most likely to happen, scenarios and to guarantee the deadlines for the hard processes in the worst case scenarios. In many applications, the worst-case execution times of processes can be much longer than their average execution times. Thus, designs for the worst-case can be overly pessimistic, i.e., result in low overall utility. We propose preemption of process executions as a method to generate flexible schedules that maximize the overall utility for the average case while guarantee timing constraints in the worst case. Our scheduling algorithms determine off-line when to preempt and when to resurrect processes. The experimental results show the superiority of our new scheduling approach compared to approaches without preemption.

  • 17. Kleberger, P.
    et al.
    Javaheri, A.
    Izosimov, Viacheslav
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Broberg, H.
    Security Concerns in Communication with the Connected Car using DoIP2011Conference paper (Other academic)
    Abstract [en]

    n this paper, we investigate the threats and challenges when using untrusted network links for communication with the connected car. A prototype system using the Diagnostics over IP (DoIP) protocol has been implemented within our project. We highlight the DoIP security challenges that we have identified. We further discuss how the environment appears to attackers, which vulnerabilities can be exploited and what the possible consequences can be. Possible countermeasures and security mechanisms are discussed to address these threats and vulnerabilities.

  • 18. Lifa, A.
    et al.
    Eles, P.
    Peng, Z.
    Izosimov, Viacheslav
    Embedded Intelligent So lutions, Linköping, Sweden .
    Hardware/Software Optimization of Error Detection Implementation for Real-Time Embedded Systems2010Conference paper (Other academic)
    Abstract [en]

    This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applica-tions. An application is modeled as a set of processes communicat-ing by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resil-iency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.

  • 19.
    Mohan, Naveen
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Törngren, Martin
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Izosimov, Viacheslav
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Kaznov, Viacheslav
    Roos, P.
    Svahn, J.
    Gustavsson, Joakim
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Nesic, Damir
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Challenges in architecting fully automated driving; With an emphasis on heavy commercial vehicles2016In: Proceedings - 2016 Workshop on Automotive Systems/Software Architectures, WASA 2016, Institute of Electrical and Electronics Engineers (IEEE), 2016, 2-9 p.Conference paper (Refereed)
    Abstract [en]

    Fully automated vehicles will require new functionalities for perception, navigation and decision making - an Autonomous Driving Intelligence (ADI). We consider architectural cases for such functionalities and investigate how they integrate with legacy platforms. The cases range from a robot replacing the driver - with entire reuse of existing vehicle platforms, to a clean-slate design. Focusing on Heavy Commercial Vehicles (HCVs), we assess these cases from the perspectives of business, safety, dependability, verification, and realization. The original contributions of this paper are the classification of the architectural cases themselves and the analysis that follows. The analysis reveals that although full reuse of vehicle platforms is appealing, it will require explicitly dealing with the accidental complexity of the legacy platforms, including adding corresponding diagnostics and error handling to the ADI. The current fail-safe design of the platform will also tend to limit availability. Allowing changes to the platforms, will enable more optimized designs and fault-operational behaviour, but will require initial higher development cost and specific emphasis on partitioning and control to limit the influences of safety requirements. For all cases, the design and verification of the ADI will pose a grand challenge and relate to the evolution of the regulatory framework including safety standards.

  • 20.
    Oscarsson, Joakim
    et al.
    KTH.
    Stolz-Sundnes, Max
    KTH.
    Mohan, Naveen
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Izosimov, Viacheslav
    KTH.
    Applying Systems-Theoretic Process Analysis in the Context of Cooperative Driving2016In: 2016 11TH IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES), IEEE, 2016Conference paper (Refereed)
    Abstract [en]

    Highly automated, cooperative driving vehicles will allow for a more fluid flow of traffic, resulting in more efficient, eco-friendly and safe traffic situations. The automotive industry however, is safety critical and current safety standards were not designed to deal with cooperative driving. In this paper, we apply a modern safety analysis method, Systems-Theoretic Process Analysis, in the context of cooperative driving as part of the Grand Cooperative Driving Challenge (GCDC) and present our reflections on the method.

  • 21. Ottavi, Marco
    et al.
    Pontarelli, S.
    Gizopoulos, D.
    Bolchini, C.
    Michael, M. K.
    Anghel, L.
    Tahoori, M.
    Paschalis, A.
    Reviriego, P.
    Bringmann, O.
    Izosimov, Viacheslav
    Semcon, Sweden.
    Manhaeve, H.
    Strydis, C.
    Hamdioui, S.
    Dependable Multicore Architectures at Nanoscale: The View From Europe2015In: IEEE Design & Test, ISSN 2168-2356, Vol. 32, no 2, 17-28 p., 6905763Article in journal (Refereed)
    Abstract [en]

    The introduction of multicore chips allowed the constant increase in delivered performance otherwise impossible to achieve. Multiple microprocessor cores from different instruction set architectures stay at the epicenter of such chips and are surrounded by memory cores of different technologies, sizes and functionalities, as well as by peripheral controllers, special function cores, analog and mixed-signal cores, reconfigurable cores, etc. The functionality as well as the complexity of multicore chips is unprecedented.

  • 22. Pop, P.
    et al.
    Eles, P.
    Peng, Z.
    Izosimov, Viacheslav
    Linköping University, Sweden.
    Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems2004Conference paper (Refereed)
    Abstract [en]

    We present an approach to partitioning and mapping for multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have proposed a schedulability analysis for such systems, including a worst-case queuing delay analysis for the gateways responsible for routing inter-cluster traffic. Based on this analysis, we address design problems characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, and mapping of processes onto architecture nodes. We present a branch-and-bound algorithm for solving these problems. Our algorithm is able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

  • 23. Pop, P.
    et al.
    Eles, P.
    Peng, Z.
    Izosimov, Viacheslav
    Linköping University, Sweden.
    Hellring, M.
    Bridal, O.
    Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications2004Conference paper (Refereed)
    Abstract [en]

    We present an approach to design optimization of multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In this paper, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, process mapping, and the optimization of parameters corresponding to the communication protocol. We present several heuristics for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

  • 24. Pop, P.
    et al.
    Izosimov, Viacheslav
    Eles, P.
    Peng, Z.
    Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems with Checkpointing and Replication2009In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 17, no 3, 389-402 p.Article in journal (Refereed)
    Abstract [en]

    We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are statically scheduled. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that multiple transient faults are tolerated and the timing constraints of the application are satisfied. We present several design optimization approaches which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

  • 25. Pop, P.
    et al.
    Poulsen, K.
    Izosimov, Viacheslav
    Eles, P.
    Scheduling and Voltage Scaling for Energy/Reliability Tradeoffs in Fault-Tolerant Time-Triggered Embedded Systems2007Conference paper (Other academic)
  • 26. Poulsen, K.
    et al.
    Pop, P.
    Izosimov, Viacheslav
    Linköping University, Sweden.
    A Constraint Logic Programming Framework for the Synthesis of Fault-Tolerant Schedules for Distributed Embedded Systems2007Conference paper (Refereed)
    Abstract [en]

    We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on. distributed heterogeneous architectures. We address time-triggered systems, where processes and messages are statically scheduled based on schedule tables. We use process re-execution for recovering from multiple transient faults. We propose three scheduling approaches, which each present a trade-off between schedule simplicity and performance, (i) full transparency, (it) slack sharing and (iii) conditional, and provide various degrees of transparency. We have developed a CLP framework that produces the fault-tolerant schedules, guaranteeing schedulability in the presence of transient faults. We show how the framework call be used to tackle design optimization problems. The proposed approach has been evaluated using extensive experiments.

  • 27. Poulsen, K.
    et al.
    Pop, P.
    Izosimov, Viacheslav
    Linköping University, Sweden.
    Energy-Aware Synthesis of Fault-Tolerant Schedules for Real-Time Distributed Embedded Systems2007Conference paper (Other academic)
  • 28. Warg, F.
    et al.
    Gassilewski, M.
    Tryggvesson, J.
    Izosimov, Viacheslav
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Werneman, A.
    Johansson, R.
    Defining autonomous functions using iterative hazard analysis and requirements refinement2016In: International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2016 and International Workshop on Assurance Cases for Software-Intensive Systems, ASSURE 2016, Workshop on Dependable Embedded and Cyber-physical Systems and Systems-of-Systems, DECSoS 2016, 5th International Workshop on Next Generation of System Assurance Approaches for Safety-Critical Systems, SASSUR 2016, and 1st International Workshop on the Timing Performance in Safety Engineering, TIPS 2016, Springer, 2016, 286-297 p.Conference paper (Refereed)
    Abstract [en]

    Autonomous vehicles are predicted to have a large impact on the field of transportation and bring substantial benefits, but they present new challenges when it comes to ensuring safety. Today the standard ISO 26262:2011 treats each defined function, or item, as a complete scope for functional safety; the driver is responsible for anything that falls outside the items. With autonomous driving, it becomes necessary to ensure safety at all times when the vehicle is operating by itself. Therefore, we argue that the hazard analysis should have the wider scope of making sure the vehicle’s functions together fulfill its specifications for autonomous operation. The paper proposes a new iterative work process where the item definition is a product of hazard analysis and risk assessment rather than an input. Generic operational situation and hazard trees are used as a tool to widen the scope of the hazard analysis, and a method to classify hazardous events is used to find dimensioning cases among a potentially long list of candidates. The goal is to avoid dangerous failures for autonomous driving due to the specification of the nominal function being too narrow.

  • 29. Åström, Alexander
    et al.
    Izosimov, Viacheslav
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Örsmark, Ola
    Efficient Software Tool Qualification for Automotive Safety-Critical Systems2011Conference paper (Other academic)
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