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  • 1.
    Chabloz, Jean-Michel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sharif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An Algorithm for Constructing a Fastest Galois NLFSR Generating a Given Sequence2010In: SEQUENCES AND THEIR APPLICATIONS-SETA 2010 / [ed] Carlet C; Pott A, 2010, Vol. 6338, p. 41-54Conference paper (Refereed)
    Abstract [en]

    The problem of efficient implementation of security mechanisms for advanced contactless technologies like RFID is gaining increasing attention. Severe constraints on resources such as area, power consumption, and production cost make the application of traditional cryptographic techniques to these technologies a challenging task. Non-Linear Feedback Shift Register (NLFSR)-based stream ciphers are promising candidates for cryptographic primitives for RFIDs because they have the smallest hardware footprint of all existing cryptographic systems. This paper presents a heuristic algorithm for constructing a fastest Galois NLFSR generating a given sequence. The algorithm takes an NLFSR in the Fibonacci configuration and transforms it to an equivalent Galois NLFSR which has the minimal delay. Our key idea is to find a best position for a given feedback connection without changing the positions of the other feedback connections. We use a technology dependent cost function which approximates the delay of an NLFSR after the technology mapping. The experimental results on 57 NLFSRs used in existing stream ciphers show that, on average, the presented algorithm allows us to decrease the delay by 25.5% as well as to reduce the area by 4.1%.

  • 2.
    Dubrova, Elena
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A BDD-Based Method for LFSR Parellelization with Application to Fast CRC Encoding2013In: Journal of Multiple-Valued Logic and Soft Computing, ISSN 1542-3980, E-ISSN 1542-3999, Vol. 21, no 5, p. 561-575Article in journal (Refereed)
    Abstract [en]

    Galois Fields of order $2^k$, $GF(2^k)$, provide a unified theoretical framework for constructing parallel devices generating $k$ output bits per clock cycle. In this paper, we use $GF(2^k)$ for constructing Linear Feedback Shift Registers (LFSRs) for the parallel encoding of Cyclic Redundancy Check (CRC) codes.CRC codes are widely used in data communication and storage for detecting burst errors. Traditional methods for the parallel encoding of CRC are based on computing the $k$th power of the connection matrix of the LFSR. We propose an alternative method based on computing the $k$th power of the transition relation of the LFSR. We use Binary Decision Diagrams (BDDs) for representing the transition relation in a partitioned form. This allows us to bound the size of BDDs by $O(n^2)$, where $n$ is the size of the LFSR. The presented algorithm is asymptotically faster than previous algorithms for LFSR parallelization.

  • 3.
    Dubrova, Elena
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sarif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A BDD-based approach to constructing LFSRs for parallel CRC encoding2012In: Proceedings, IEEE 42nd International Symposium on Multiple-Valued Logic. ISMVL 2012, IEEE Computer Society, 2012, p. 128-133Conference paper (Refereed)
    Abstract [en]

    Cyclic Redundancy Check codes (CRC) are widely used in data communication and storage devices for detecting burst errors. In applications requiring high-speed data transmission, multiple bits of an CRC are computed in parallel. Traditional methods for constructing an Linear Feedback Shift Register (LFSR) generating k bits of an CRC in parallel are based on computing kth power of the connection matrix of the LFSR. We propose an alternative method which is based on computing kth power of the transition relation of the LFSR. We use Binary Decision Diagrams (BDDs) for representing the transition relation and we keep the transition relation partitioned. This allows us to bound the size of BDDs by O(n(2)), where n is the size of the LFSR. Our experimental results show that the presented algorithm asymptotically improves the complexity of previous approaches.

  • 4.
    Dubrova, Elena
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sharif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A BDD-Based Method for LFSR Parallelization with Application to Fast CRC Encoding2013In: Journal of Multiple-Valued Logic and Soft Computing, ISSN 1542-3980, E-ISSN 1542-3999, Vol. 21, no 5-6, p. 561-574Article in journal (Refereed)
    Abstract [en]

    Galois Fields of order 2(k), GF(2(k)), provide a unified theoretical framework for constructing parallel devices generating k output bits per clock cycle. In this paper, we use GF(2(k)) for constructing Linear Feedback Shift Registers (LFSRs) for the parallel encoding of Cyclic Redundancy Check (CRC) codes. CRC codes are widely used in data communication and storage for detecting burst errors. Traditional methods for the parallel encoding of CRC are based on computing the kth power of the connection matrix of the LFSR. We propose an alternative method based on computing the kth power of the transition relation of the LFSR. We use Binary Decision Diagrams (BDDs) for representing the transition relation in a partitioned form. This allows us to bound the size of BDDs by O(n(2)), where it is the size of the LFSR. The presented algorithm is asymptotically faster than previous algorithms for LFSR parallelization.

  • 5.
    Li, Nan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sharif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Secure Key Storage Using State Machines2013In: 2013 IEEE 43rd International Symposium On Multiple-Valued Logic (ISMVL 2013), IEEE Computer Society, 2013, p. 290-295Conference paper (Refereed)
    Abstract [en]

    In hardware implementations of cryptographic systems, secret keys are commonly stored in an on-chip memory. This makes them prone to physical attacks, since the location of a memory on a chip in usually easy to spot. We propose to encode secret keys using a state machine which can be concealed in the rest of the logic on a chip. We present an heuristic algorithm which constructs a minimal state machine for a given set of secret keys. We show that, by using m-ary encoding, we are able to construct state machines which are smaller than the ones constructed using binary encoding. The presented algorithm is feasible for storing up to 1Mbits of random data.

  • 6.
    Liu, Ming
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sharif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Faster Shift Register Alternative to Filter Generators2013In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE , 2013, p. 713-718Conference paper (Refereed)
    Abstract [en]

    LFSR-based filter generators are used as a basic building block in many stream ciphers. Filter generators are popular because their well-defined mathematical description enables a detailed formal security analysis. In this paper, we show how to modify a filter generator into a nonlinear feedback shift register which is faster, but slightly larger, than the original filter generator. For example, the propagation delay can be reduced 1.54 times at the expense of 1.27% extra area. The presented method might be important for applications which require very high data rates, e.g. 4G mobile communication technology.

  • 7.
    Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An improved hardware implementation of the quark hash function2013In: Radio Frequency Identification Security and Privacy Issues 9th International Workshop, RFIDsec 2013, Graz, Austria, July 9-11, 2013, Revised Selected Papers, Springer Berlin/Heidelberg, 2013, Vol. 8262, p. 113-127Conference paper (Refereed)
    Abstract [en]

    We present an implementation of U-Quark, the lightest instance of the Quark family of hash functions, which is optimized for throughput. The throughput is increased by converting the Feedback Shift Registers (FSRs) of Quarks permutation block from the original Fibonacci configuration to the Galois configuration. In this way, the complex feedback functions of the FSRs are decomposed into several simpler feedback functions. As a result, the throughput of U-Quark is increased by 34 % on average without any area penalty. The power consumption of the hash function also improves by 19 %.

  • 8.
    Mansouri, Shohreh Sharif
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Protecting Ring Oscillator Physical Unclonable Functions Against Modeling Attacks2014In: INFORMATION SECURITY AND CRYPTOLOGY - ICISC 2013, 2014, p. 241-255Conference paper (Refereed)
    Abstract [en]

    One of the most common types of Physical Unclonable Functions (PUFs) is the ring oscillator PUF (RO-PUF), a type of PUF in which the output bits are obtained by comparing the oscillation frequencies of different ring oscillators. One application of RO-PUFs is to be used as strong PUFs: a reader sends a challenge to the RO-PUF and the RO-PUF's response is compared with an expected response to authenticate the PUF. In this work we introduce a method to choose challenge-response pairs so that a high number of challenge-response pairs is provided but the system has a good tolerance to modeling attacks, a type of attacks in which an attacker guesses the response to a new challenge by using his knowledge about the previously-exchanged challenge-response pairs. Our method targets tag-constrained applications, i. e. applications in which there are strong limitations of cost, area and power on the system in which the PUF has to be implemented.

  • 9.
    Sarif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An architectural countermeasure against power analysis attacks for FSR-based stream ciphers2012In: Lect. Notes Comput. Sci., 2012, p. 54-68Conference paper (Refereed)
    Abstract [en]

    Feedback Shift Register (FSR) based stream ciphers are known to be vulnerable to power analysis attacks due to their simple hardware structure. In this paper, we propose a countermeasure against non-invasive power analysis attacks based on switching activity masking. Our solution has a 50% smaller power overhead on average compared to the previous standard cell-based countermeasures. Its resistance against different types of attacks is evaluated on the example of Grain-80 stream cipher.

  • 10.
    Sharif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Design and Implementation of Efficient and Secure Lightweight Cryptosystems2014Doctoral thesis, monograph (Other academic)
    Abstract [en]

    In recent years there has been a wide-spread deployment of battery-powered and passive devices such as RFID tags, systems with very strong limitations on area, cost and power budgets. Deploying cryptographic solutions for these systems is both important, because it could unlock several security-critical applications, and challenging, due to the stringent budgets: the overheads of even the smallest block ciphers are often one or more orders of magnitude too high. Because of this reason there is a growing interest in lightweight cryptography, a discipline that tries to develop cryptographic solutions for systems with very tight cost, area and power constraints. The importance of lightweight cryptography is forecasted to continue growing in the future, with lightweight systems becoming more ubiquitous and more common in sensitive applications.In this work we analyse and solve several problems related to light weight cryptography. We first study efficient implementations of feedback shift registers (FSR)-based cryptosystems, such as stream ciphers and hash functions, that are especically designed for highly-constrained environments. The core of our solution is to apply a Fibonacci-to-Galois transformation that changes the structure of an FSR to minimise its critical path. Along with this transformation we apply several hardware optimization techniques, such as pipelining and double-frequency clock generators, that are necessary to obtain through-put benefits. Our results show impressive throughput improvements (100% for some cryptographic systems) without any area and power penalties. In a second part, we show how to protect FSR-based stream ciphers from power analysis attacks, a type of attack that exploits the information content in the power trace of a system. It is well known that, due to their very simple hardware structure, FSR-based stream ciphers are very vulnerable to this type of attacks. We introduce two different countermeasures against power analysis attacks: one at the architectural level (masking the switching activity of the FSRs) and the other one at the physical level ( flattening the power curve to one among two power levels). Both solutions exploit the properties of FSR-based stream ciphers with the specic goal to minimise their area and power overheads. We demonstrate them on the FSR-based stream cipher Grain by performing Differential Power Analysis (DPA) and Mutual Information Analysis (MIA) attacks at SPICE level. However, the techniques we introduce are general and can potentially be applied to any FSR-based stream ciphers. In a third part, we focus on Ring Oscillator Physical Unclonable Functions (RO-PUFs), a type of digital fingerprint used for chip identication that is well-suited for lightweight cryptography. We suggest solutions to two well-known problems related to this type of PUF: how to generate a secure and large challenge-response database and how to increase PUF reliability in presence of temperature variations. We validate our solutions at SPICE level by modelling the random variations introduced during manufacturing.

    Download full text (pdf)
    Thesis
  • 11.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A countermeasure against power analysis attacks for FSR-based stream ciphers2011In: Proc. ACM Great Lakes Symp. VLSI GLSVLSI, 2011, p. 235-240Conference paper (Refereed)
    Abstract [en]

    In this paper we analyze the power characteristics of Feedback Shift Registers (FSRs) and their e ect on FSR-based stream ciphers. We introduce a technique to isolate the switching activity of a stream cipher by equalizing the current drawn from the cipher with lower power overhead compared to previously introduced countermeasures. By re-implementing the Grain-80 and the Grain-128 ciphers with the presented approach, we lower their power consumption respectively by 20% and 25% compared to previously proposed countermeasures.

  • 12.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An improved hardware implementation of the Grain stream cipher2010In: Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010, 2010, p. 433-440Conference paper (Refereed)
    Abstract [en]

    A common approach to protect confidential information is to use a stream cipher which combines plain text bits with a pseudo-random bit sequence. Among the existing stream ciphers, Non-Linear Feedback Shift Register (NLFSR)-based ones provide the best trade-off between cryptographic security and hardware efficiency. In this paper, we show how to further improve the hardware efficiency of the Grain stream cipher. By transforming the NLFSR of Grain from its original Fibonacci configuration to the Galois configuration and by introducing new hardware solutions, we double the throughput of the 80 and 128-bit key 1 bit/cycle architectures of Grain with no area and power penalty.

  • 13.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An Improved Hardware Implementation of the Grain-128a Stream Cipher2012In: Lecture Notes in Computer Science / [ed] Springer-Verlag, 2012, p. 278-292Conference paper (Refereed)
    Abstract [en]

    We study efficient high-throughput hardware implementations of the Grain-128a family of stream ciphers. To increase the throughput compared to the standard design, we apply five different techniques in combination: isolation of the authentication section, Fibonacci-to-Galois transformation of the feedback shift registers, multi-frequency implementation, simplification of the pre-outputs functions and internal pipelining. The combined effect of all these techniques enables an average 56% higher keystream generation throughput among all the ciphers, at the expense of an average 8% area penalty, an average 4% power overhead and a 21% slower keystream initialization phase. An alternative combination of techniques allows an average 23% throughput improvement in all phases.

  • 14.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Double-edge transformation for optimized power analysis suppression countermeasures2013In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE , 2013, p. 353-359Conference paper (Refereed)
    Abstract [en]

    We introduce a power optimization technique for suppression countermeasures against Power Analysis attacks that can potentially be applied to any type of crypto-system implemented as a synchronous digital system. Since the power consumption of systems protected by suppression countermeasures is proportional to current peaks, we propose a simple transformation to move some of the switching activity of the crypto-system from the rising edge to the falling edge of the clock, so that current peaks are reduced. The transformation is easy to apply, requires only standard cell logic gates, has a low area overhead but can reduce the maximal working frequency of a system by at most a factor 2. We prove our method on an ASIC implementation of the Grain-80 stream cipher using SPICE-level simulation, obtaining 50% power savings compared to the non-optimized suppression countermeasure.

  • 15.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Power-security trade-off in multi-level power analysis countermeasures for FSR-based stream ciphers2012In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2012), IEEE , 2012, p. 81-84Conference paper (Refereed)
    Abstract [en]

    Feedback Shift Register (FSR) based stream ciphers are one of the most promising new groups of cryptographic algorithms, which target applications characterized by strong power, area and cost constraints. Due to high sensibility against power analysis attacks, there is a strong need for countermeasures which increase the immunity of this class of ciphers without introducing large power and area overheads. In this paper we study analog multi-level countermeasures which can protect FSR-based stream ciphers against Differential Power Analysis (DPA) attacks, with lower power overhead compared to alternative solutions that can be found in literature. We highlight a trade-off between power consumption and security, and propose an approach which ensures at the same time low power overhead and high security against power analysis attacks.

  • 16.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Pulse Latch Based FSRs for Low-Overhead Hardware Implementation of Cryptographic Algorithms2010In: 2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2010, p. 253-259Conference paper (Refereed)
    Abstract [en]

    In this paper, we address the problem of low-overhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flip-flop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power.

  • 17.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ring oscillator physical unclonable function with multi level supply voltages2012In: Computer Design (ICCD), 2012 IEEE 30th International Conference on, IEEE Computer Society, 2012, p. 520-521Conference paper (Refereed)
    Abstract [en]

    In this paper we introduce a new type of Ring Oscillator PUF (RO-PUF) in which the inverters composing the ring oscillators can be supplied by independent voltages. This new RO-PUF can improve the reliability of the PUF in case of temperature variations.

1 - 17 of 17
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