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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density2016In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper (Refereed)
    Abstract [en]

    Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Moeen, Mahdi
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Cappetta, Carmine
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Sensitivity of the crystal quality of SiGe layers grown at low temperatures by trisilane and germane2016In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 613, p. 38-42Article in journal (Refereed)
    Abstract [en]

    This work investigates the crystal quality of SiGe layers grown at low temperatures using trisilane, and germane precursors. The crystal quality sensitivity was monitored for hydrogen chloride and/or minor oxygen amount during SiGe epitaxy or at the interface of SiGe/Si layers. The quality of the epi-layerswas examined by quantifying noise parameter, K-1/f obtained from the power spectral density vs. 1/f curves. The results indicate that while it is difficult to detect small defect densities in SiGe layers by physical material characterization, the noise measurement could reveal the effects of oxygen contamination as low as 0.16mPa inside and in the interface of the layers.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Noroozi, Mohammad
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Primetzhofer, Daniel
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry.H
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    GeSnSi CVD Epitaxy using Silane, Germane, Digermane, and Tin tetrachlorideArticle in journal (Refereed)
    Abstract [en]

    In this study, strain relaxed and compressive strained Ge1-x-ySnxSiy (0.015≤x≤0.15 and 0≤y≤0.15) layers were epitaxially grown on Si substrate in a chemical vapor deposition reactor at atmospheric pressure. Digermane (Ge2H6) and germane (GeH4) were used as Ge precursors and tin tetrachloride (SnCl4) was used as Sn precursor. The growth temperature was kept below 400ᵒC to suppress Sn out diffusion. The layers crystal quality and strain were characterized using XRD, high resolution reciprocal lattice mapping and transmission electron microscopy and the surface morphology was investigated by atomic force microscopy (AFM). Furthermore, the low temperature epitaxial growth up to 15% Si atoms incorporation in Ge0.94Sn0.06 was demonstrated by adding silane (SiH4) as Si precursor. Sn contents calculated from high resolution XRD patterns were confirmed by Rutherford backscattering spectroscopy which shows that Sn atoms are mostly positioned in substitutional sites. AFM analysis showed below 1nm surface roughness for both strained and strain relaxed GeSn layers which make the promising materials for photonics and electronics applications.

  • 4.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 5.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 6.
    Asadollahi, Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zabel, Thomas
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of strained Ge on insulator via room temperature wafer bonding2014In: 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014, IEEE Computer Society, 2014, p. 81-84Conference paper (Refereed)
    Abstract [en]

    This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si 0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).

  • 7.
    Asadollahi, Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zabel, Thomas
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Roupillard, Gabriel
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of relaxed germanium on insulator via room temperature wafer bonding2014In: ECS Transactions: Volume 64, Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, Electrochemical Society, 2014, no 6, p. 533-541Conference paper (Refereed)
    Abstract [en]

    We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

  • 8.
    Atwa, Mohamed M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Alaskalany, Ahmed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elgammal, Karim
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. KTH, Centres, SeRC - Swedish e-Science Research Centre.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hammar, Mattias
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Trilayer Graphene as a Candidate Material for Phase-Change Memory Applications2016In: MRS Advances, ISSN 2316-7858, E-ISSN 1610-191X, Vol. 1, no 20, p. 1487-1494Article in journal (Refereed)
    Abstract [en]

    There is pressing need in computation of a universal phase change memory consolidating the speed of RAM with the permanency of hard disk storage. A potentiated scanning tunneling microscope tip traversing the soliton separating a metallic, ABA-stacked phase and a semiconducting ABC-stacked phase in trilayer graphene has been shown to permanently transform ABA-stacked regions to ABC-stacked regions. In this study, we used density functional theory (DFT) calculations to assess the energetics of this phase-change and explore the possibility of organic functionalization using s-triazine to facilitate a reverse phase-change from rhombohedral back to Bernal in graphene trilayers. A significant deviation in the energy per simulated atom arises when s-triazine is adsorbed, favoring the transformation of the ABC phase to the ABA phase once more. A phase change memory device utilizing rapid, energy-efficient, reversible, field-induced phase-change in graphene trilayers could potentially revolutionize digital memory industry.

  • 9. Balestra, F.
    et al.
    Parker, E.
    Leadley, D.
    Mantl, S.
    Dubois, E.
    Engstrom, O.
    Clerc, R.
    Cristoloveanu, S.
    Kurz, H.
    Raskin, J. P.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Ionescu, A.
    Moselund, K. E.
    Boucart, K.
    Kasper, E.
    Karmous, A.
    Baus, M.
    Spangenberg, B.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Sangiorgi, E.
    Ghibaudo, G.
    Flandre, D.
    NANOSIL network of excellence-silicon-based nanostructures and nanodevices for long-term nanoelectronics applications2008In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 11, no 5-6, p. 148-159Article in journal (Refereed)
    Abstract [en]

    NANOSIL Network of Excellence [NANOSIL NoE web site < www.nanosil-noe.eu >], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed-with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades.

  • 10.
    Berrier, Audrey
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Mulot, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Anand, Srinivasan
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Electrical conduction through a 2D InP-based photonic crystal - art. no. 63220J2006In: Tuning the Optic Response of Photonic Bandgap Structures III / [ed] Braun, PV; Weiss, SM, 2006, Vol. 6322, p. J3220-J3220Conference paper (Refereed)
    Abstract [en]

    This work investigates the current transport across two-dimensional PhCs dry etched into InP-based low-index-contrast vertical structures using Ar/Cl-2 chemically assisted ion beam etching. The electrical conduction through the PhC field is influenced by the surface potential at the hole sidewalls, which is modified by dry etching. The measured current-voltage (I-V) characteristics are linear before but show a current saturation at higher voltages. This behaviour is confirmed by simulations performed by ISE-TCAD software. We investigate the dependence of the conductance of the PhC area as a function of the geometry of the photonic crystal as well as the material parameters. By comparing the experimental and simulated conductance of the PhC, we deduce that the Fermi level is pinned at 0.1 eV below the conduction band edge. The method presented here can be used for evaluating etching processes and surface passivation methods. It is also applicable for other material systems and sheds new light on current driven PhC tuning.

  • 11.
    Berrier, Audrey
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Mulot, Mikaël
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Anand, Srinivasan
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Carrier transport through a dry-etched InP-based two-dimensional photonic crystal2007In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 101, no 12, p. 123101-1-123101-6Article in journal (Refereed)
    Abstract [en]

    The electrical conduction across a two-dimensional photonic crystal (PhC) fabricated by Ar/Cl-2 chemically assisted ion beam etching in n-doped InP is influenced by the surface potential of the hole sidewalls, modified by dry etching. Carrier transport across photonic crystal fields with different lattice parameters is investigated. For a given lattice period the PhC resistivity increases with the air fill factor and for a given air fill factor it increases as the lattice period is reduced. The measured current-voltage characteristics show clear ohmic behavior at lower voltages followed by current saturation at higher voltages. This behavior is confirmed by finite element ISE TCAD (TM) simulations. The observed current saturation is attributed to electric-field-induced saturation of the electron drift velocity. From the measured and simulated conductance for the different PhC fields we show that it is possible to determine the sidewall depletion region width and hence the surface potential. We find that at the hole sidewalls the etching induces a Fermi level pinning at about 0.12 eV below the conduction band edge, a value much lower than the bare InP surface potential. The results indicate that for n-InP the volume available for conduction in the etched PhCs approaches the geometrically defined volume as the doping is increased.

  • 12. Bolten, J.
    et al.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ternon, C.
    Serre, P.
    Fabrication of Nanowires2014In: Beyond CMOS Nanodevices 1, Wiley Blackwell , 2014, p. 5-23Chapter in book (Other academic)
    Abstract [en]

    Several fabrication processes of silicon nanowires have been developed in the research community. They can be divided into bottom-up or top-down approaches. This chapter describes top-down fabrication of silicon nanowires using electron beam lithography (EBL), which combined with optical lithography can be a viable approach if not too many silicon nanowires need to be patterned on a wafer. It also describes the sidewall transfer lithography (STL) technique using I-line stepper lithography to pattern a vast amount of silicon nanowires on a silicon wafer. In addition the chapter examines how bottom-up Si nanowires synthesized by vapor-liquid-solid (VLS)-chemical vapor deposition (CVD) can be assembled at low cost in an efficient way for further use as a sensing material. Among the solution-based assembly methods for the nanostructured network (nanonet) fabrication, the vacuum filtration method is highly simple, versatile, low cost and scalable to large areas.

  • 13.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Current Gain Degradation in 4H-SiC Power BJTs2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 702-705Article in journal (Refereed)
    Abstract [en]

    SiC airs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.

  • 14.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 10, p. 2664-2670Article in journal (Refereed)
    Abstract [en]

    The influence of the emitter-base geometry on the current gain has been investigated by means of measurements and simulations. Particular attention has been placed on the emitter width and on the distance between the emitter edge and the base contact. When the emitter width is decreased from 40 to 8 mu m, the current gain is reduced by 20%, whereas when the distance between the base contact and the emitter edge is decreased from 5 to 2 mu m, the current gain is reduced by 10%. Simulations have been used to investigate the reasons for the current gain reduction. The reduction of the emitter width induces two mechanisms of current gain reduction: earlier forward biasing of the base-collector junction and higher recombination in the emitter region. Both mechanisms result from the higher current density flowing under the emitter region. Placing the base contact very close to the emitter edge increases the base current by increasing the gradient of the electron concentration toward the base contact. The effect of increasing the base doping in the extrinsic region has been simulated, and the results demonstrate that the current gain can be improved if a high doping concentration in the range of 5 x 10(18) cm(-3) is used.

  • 15.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 3, p. 704-711Article in journal (Refereed)
    Abstract [en]

    Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10(-15) cm(2), and a trap concentration of 2 x 10(12) cm(-2). Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base ( which has a doping concentration of 3 x 10(17) cm(-3)) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.

  • 16.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Temperature Modeling and Characterization of the Current Gain in 4H-SiC Power BJTs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, p. 1061-1064Article in journal (Refereed)
    Abstract [en]

    The current gain of 4H-SiC BJTs has been modeled using interface traps between SIC and SiO2 to describe surface recombination, by a positive temperature dependence of the carrier lifetime in the base region and by bandgap narrowing in the emitter region. The interface traps have been modeled by one single level at 1 eV above the valence band, with capture cross section of 1 x 10(-15) cm(2) and concentration of 2 x 10(12) cm(-2). The temperature behavior of SiC BJTs has been simulated and the results have been compared with measurements. An analysis of the carrier concentration has been performed in order to describe the mechanisms for fall-off of the current gain at high collector current. At room temperature high injection in the base and forward biasing of the base-collector junction occur simultaneously causing an abrupt drop of the current gain. At higher temperatures high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the only acting mechanism for the current gain fall-off at high collector current. This mechanism and the negative temperature dependence of the carrier mobility can also explain the reduction of the knee current for gain fall-off with increasing temperature. Simulations with different emitter widths have been also performed and analyzed to characterize the emitter size effect. Higher current density caused by reducing the emitter width introduces higher carrier recombination in the emitter region, leading to a reduction of the current gain.

  • 17.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 2081-2087Article in journal (Refereed)
    Abstract [en]

    The ON-resistance of silicon carbide bipolar transistors is characterized and simulated. Output characteristics are compared at different base currents and different temperatures in order to validate the physical model parameters. A good agreement is obtained, and the key factors, which limit the improvement of R-ON, are identified. Surface recombination and material quality play an important role in improving device performances, but the device design is also crucial. Based on simulation results, a design that can enhance the conductivity modulation in the lowly doped drift region is proposed. By increasing the base doping in the extrinsic region, it is possible to meet the requirements of having low voltage drop, high current density, and satisfactory forced current gain. According to simulation results, if the doping is 5 x 10(18) cm(-3), it is possible to conduct 200 A/cm(2) at V-CE = 1 V by having a forced current gain of about 8, which represents a large improvement, compared with the simulated value of only one in the standard design.

  • 18.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Investigation of Current Gain Degradation in 4H-SiC Power BJTs2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1131-1134Article in journal (Refereed)
    Abstract [en]

    The current gain degradation of 4H-SiC BJTs with no significant drift of the on-resistance is investigated. Electrical stress on devices with different emitter widths suggests that the device design can influence the degradation behavior. Analysis of the base current extrapolated from the Gummel plot indicates that the reduction of the carrier lifetime in the base region could be the cause for the degradation of the gain. However, analysis of the base current of the base-emitter diode shows that the degradation of the passivation layer could also influence the reduction of the current gain.

  • 19.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl -Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simulations of Open Emitter Breakdown Voltage in SiC BJTs with non Implanted JTE2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 615-617, p. 841-844Article in journal (Refereed)
    Abstract [en]

    Ion implantation for selective doping of SiC is problematic due to damage generation during the process and low activation of dopants. In SiC bipolar junction transistor (BJT) the junction termination extension (JTE) can be formed without ion implantation using instead a controlled etching into the epitaxial base. This etched JTE is advantageous because it eliminates ion implantation induced damage and the need for high temperature annealing. However, the dose, which is controlled by the etched base thickness and doping concentration, plays a crucial role. In order to find the optimum parameters, device simulations of different etched base thicknesses have been performed using the software Sentaurus Device. A surface passivation layer consisting of silicon dioxide, considering interface traps and fixed trapped charge, has been included in the analysis by simulations. Moreover a comparison with measured data for fabricated SiC BJTs has been performed.

  • 20. Cho, H.
    et al.
    Leerungnawarat, P.
    Hays, D. C.
    Pearton, S. J.
    Chu, S. N. G.
    Strong, R. M.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ren, F.
    Ultradeep, low-damage dry etching of SiC2000In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 76, no 6, p. 739-741Article in journal (Refereed)
    Abstract [en]

    The Schottky barrier height (Phi(B)) and reverse breakdown voltage (V-B) of Au/n-SiC diodes were used to examine the effect of inductively coupled plasma SF6/O-2 discharges on the near-surface electrical properties of SiC. For low ion energies (less than or equal to 60 eV) in the discharge, there is minimal change in Phi(B) and V-B, but both parameters degrade at higher energies. Highly anisotropic features typical of through-wafer via holes were formed in SiC using an Al mask.

  • 21. Dahlquist, Fanny
    et al.
    Svedberg, J. -O
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Breitholtz, Bo
    Lendenmann, Heinz
    2.8 kV, forward drop JBS diode with low leakage2000In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 338-342, p. 1179-1182Article in journal (Refereed)
    Abstract [en]

    High voltage Schottky-, Junction Barrier Schottky (JBS)- and PiN-diodes with an implanted JTE termination have been fabricated on the same 4H-SiC wafer. Blocking voltages of 2.5-2.8 kV were reached for JBS and PiN diodes while the Schottky diodes reach about 2.0 kV. It is shown that the JBS design increases the blocking voltage effectively compared to the Schottky device with less than 10% increase in on-state static losses. Also, a comparison of static losses to a PiN diode gives a decrease of 40% for the JBS. The leakage current is also lowered by two decades compared to the Schottky device at its blocking voltage. Temperature measurements show that the low leakage current is maintained up to at least 225 °C.

  • 22. Dahlquist, Fanny
    et al.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rottner, K.
    Junction barrier Schottky diodes in 4H-SiC and 6H-SiC1998In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 264-268, no PART 2, p. 1061-1064Article in journal (Refereed)
    Abstract [en]

    The Junction Barrier Schottky (JBS) diode in silicon carbide is a promising candidate for a low-leakage power rectifier for high switching frequencies and elevated temperature operation. It has the advantage of a low forward voltage drop while keeping a low leakage current at high blocking voltage. JBS devices have been fabricated in 4H SiC and 6H SiC and then electrically characterised in comparison with pn and Schottky diodes on the same wafer. The JBS devices reached blocking voltages up to 1.0 kV at a leakage current density of 13 ÎŒA/cm2 and the forward conduction was limited by an on-resistance close to the theoretical value.

  • 23. Danielson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Forsberg, U.
    Janzen, E.
    Investigation of thermal properties in fabricated 4H-SiC high power bipolar transistors2003In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 47, no 4, p. 639-644Article in journal (Refereed)
    Abstract [en]

    Silicon carbide bipolar junction transistors have been fabricated and investigated. The transistors had a maximum current gain of approximately 10 times, and a breakdown voltage of 450 V. When operated at high power densities the device showed a clear self-heating effect, decreasing the current gain. The junction temperature was extracted during self-heating to approximately 150 degreesC, using the assumption that the current gain only depends on temperature. Thermal images of a device under operation were also recorded using an infrared camera, showing a significant temperature increase in the vicinity of the device. The device was also tested in a switched setup, showing fast turn on and turn off at 1 MHz and 300 V supply voltage. Device simulations have been used to analyze the measured data. The thermal conductivity is fitted against the self-heating, and the lifetime in the base is fitted against the measurement of the current gain.

  • 24. Danielsson, E.
    et al.
    Lee, S. K.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Inductively coupled plasma etch damage in 4H-SiC investigated by Schottky diode characterization2001In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 30, no 3, p. 247-252Article in journal (Refereed)
    Abstract [en]

    Ti Schottky diodes have been used to investigate the damage caused by inductively coupled plasma (ICP) etching of silicon carbide. The Schottky diodes were characterized using TV and CV measurements. An oxidation approach was tested in order to anneal the damage, and the diode characterization was used to determine the success of the annealing. The barrier height, leakage current, and ideality factor changed significantly on the sample exposed to the etch. When the etched samples were oxidized the electrical properties were recovered and were similar to the unetched reference sample (with oxidation temperatures ranging from 900 degreesC up to 1250 degreesC). Annealing in nitrogen at 1050 degreesC did not improve the electrical characteristics. A low energy etch showed little influence on the electrical characteristics, but since the etch rate was very low the etched depth may not be sufficient in order to reach a steady state condition for the surface damage.

  • 25. Danielsson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Linthicum, K.
    Thomson, D. B.
    Nam, O. H.
    Davis, R. F.
    The influence of band offsets on the IV characteristics for GaN/SiC heterojunctions2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 6, p. 827-835Article in journal (Refereed)
    Abstract [en]

    GaN/SiC heterojunctions can improve the performance considerably for bipolar transistors based on SiC technology. In order to fabricate such devices with a high current gain, the origin of the low turn-on voltage for the heterojunction has to be investigated, which is believed to decrease the minority carrier injection considerably. In this work heterojunction diodes are compared and characterized. For the investigated diodes, the GaN layers have been grown by molecular beam epitaxy (MBE), metal organic chemical vapor deposition, and hydride vapor phase epitaxy. A diode structure fabricated with MBE is presented here, whereas others are collected from previous publications. The layers were grown either with a low temperature buffer, AIN buffer, or without buffer layer. The extracted band offsets are compared and included in a model for a recombination process assisted by tunneling, which is proposed as explanation for the low turn-on voltage. This model was implemented in a device simulator and compared to the measured structures, with good agreement for the diodes with a GaN layer grown without buffer layer. In addition the band offset has been calculated from Schottky barrier measurements, resulting in a type II band alignment with a conduction band offset in the range 0.6-0.9 eV. This range agrees well with the values extracted from capacitance-voltage measurements.

  • 26. Danielsson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nikolaev, A.
    Nikitina, I. P.
    Dmitriev, V.
    Fabrication and characterization of heterojunction diodes with HVPE-Grown GaN on 4H-SiC2001In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 48, no 3, p. 444-449Article in journal (Refereed)
    Abstract [en]

    GaN/SiC heterojunctions can improve the performance considerably for BJTs and FETs. In this work, heterojunction diodes have been manufactured and characterized. The fabricated diodes have a GaN n-type cathode region on top of a JH-SIC p-type epi layer. The GaN layer was grown with HVPE directly on off-axis SiC without a buffer layer. Mesa structures were formed and a Ti metallization was used as cathode contact to GaN, and the anode contact was deposited on the backside using sputtered Al. Both current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed on the diode structures. The ideality factor of the measured diodes was 1.1 and was constant with temperature. A built in potential of 2.06 V was extracted from I-V-measurements and agrees well with the built in potential from C-V-measurements. The conduction band offset was extracted to 1.1 eV and the heterojunction was of type II. The turn on voltage for the diodes is about 1 V lower than expected and a suggested mechanism for this effect is discussed.

  • 27. Danielsson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tsvetkov, D.
    Dmitriev, V. A.
    Characterization of heterojunction diodes with hydride vapor phase epitaxy grown AlGaN on 4H-SiC2002In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 91, no 4, p. 2372-2379Article in journal (Refereed)
    Abstract [en]

    AlGaN/4H-SiC heterojunction diodes with varying composition of Al have been fabricated. Five different compositions were investigated, GaN, Al0.1Ga0.9N, Al0.15Ga0.85N, Al0.3Ga0.7N, and Al0.5Ga0.5N, along with a 4H-SiC homojunction diode for comparison. The turn on voltage was around 1 V, and the ideality factor between 1 and 2 for all heterojunction diodes except for the Al0.3Ga0.7N diode. This diode had an ideality factor between 2 and 3, and also showed a much lower series resistance, indicating a change in transport mechanism across the junction. A tunnel assisted recombination model was analyzed and compared to the extracted values of the GaN diode. The model agreed well with both current-voltage and capacitance-voltage measurements for this diode. This model was not applied to the other samples, since their characteristics could not be explained by a simple mechanism.

  • 28. Danielsson, Erik
    et al.
    Breitholtz, Bo
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simulation Study of on-state Losses as Function of Carrier Life-time for a GaN/SiC High Power HBT Design1999In: Physica scripta. T, ISSN 0281-1847, Vol. 79, p. 290-293Article in journal (Refereed)
    Abstract [en]

    SiC has several properties that makes it more suitable than silicon for high power devices. One problem with SiC bipolar devices is the short carrier life times, and this problem becomes more severe when designing devices for high voltage applications since the dimensions are larger. This work investigates how the Shockley-Read-Hall lifetime influences the on-state characteristics of a HBT or BJT switch in 4H-SiC. The on-state characteristics were simulated with varying SRH lifetimes in the base and drift region. Comparisons were made at 100 A/cm2 collector current density, Jc, and at the base current density, JB, where the total on-state power loss of the design is at minimum. The SRH lifetime in the drift region is the dominant parameter for on-state performance, whereas the SRH lifetime in the base is of much less importance. The simulations showed that to reach an acceptable JC/JB-ratio of 100 at power minimum a SRH lifetime of at least 100 ÎŒs in the drift region was needed for the HBT design. This lifetime is far from the experimental values reported for 4H-SiC. The advantages of the heterojunction in comparison to ordinary BJTs decreases with shorter SRH lifetimes, but an improvement could always be seen.

  • 29.
    Danielsson, Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schöner, Adolf
    Acreo AB.
    Hallin, Christer
    Department of Physics and Measurement Technology, Linköping University.
    A 4H-SiC BJT with an Epitaxially Regrown Extrinsic Base Layer2005In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 483-485, p. 905-908Article in journal (Refereed)
    Abstract [en]

    4H-SiC BJTs were fabricated using epitaxial regrowth instead of ion implantation to form a highly doped extrinsic base layer necessary for a good base ohmic contact. A remaining p(+) regrowth spacer at the edge of the base-emitter junction is proposed to explain a low current gain of 6 for the BJTs. A breakdown voltage of 1000 V was obtained for devices with Al implanted JTE.

  • 30.
    Danielsson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Schöner, Adolf
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Extrinsic base design of SiC bipolar transistors2004In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 457-460, no II, p. 1117-1120Article in journal (Refereed)
    Abstract [en]

    The SiC npn bipolar junction transistor (BJT) is a very promising device for high voltage and high power switches. The SiC BJT has, due to junction voltage cancellation, potentially a low on-resistance. However, the high resistivity in the base layer can induce a locally forward biased base collector junction and a premature current from the base to collector at on-state. In this work we propose a new technique to fabricate the extrinsic base using regrowth of the extrinsic base layer. This technique can put the highly doped region of the extrinsic base a few tenths of a micron from the intrinsic region. We also propose a new mobility model in our simulations to correctly account for the ionized impurities in minority carrier transport and elevated temperature.

  • 31. Danielsson, Erik
    et al.
    Harris, C. I.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Thermal stability of sputtered TiN as metal gate on 4H-SiC1998In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 264-268, no PART 2, p. 805-808Article in journal (Refereed)
    Abstract [en]

    MOS-structures were made with TiN as metal gate on 4H-SiC. The thermal stability and electrical properties of this gate was determined by CV-measurements. Comparison with Al gates showed that TiN worked well as a gate metal on 4H-SiC. The hysteresis and density of the interface states were comparable for the two gate types. The n-type samples had low leakage and a flatband voltage of a few volts, while the p-type samples had high leakage and a fiatband voltage of around -20 V. The structure showed poor characteristics after a 700°C anneal for one hour, which is probably caused by the formation of titanium silicide. The TiN films had a lower content of nitrogen than expected, which could influence the stability.

  • 32. Danielsson, Erik
    et al.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Breitholtz, B.
    Linthicum, K.
    Thomson, D. B.
    Nam, O. -H
    Davis, R. F.
    Simulation and electrical characterization of GaN/SiC and AlGaN/SiC heterodiodes1999In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 61-62, p. 320-324Article in journal (Refereed)
    Abstract [en]

    Heterojunctions on SiC is an area in rapid development, especially GaN/SiC and AlGaN/SiC heterojunctions. The heterojunction can improve the performance considerably for BJTs and FETs. In this work heterojunction diodes have been manufactured and characterized. The structure was a GaN or AlGaN n-type region on top of a 6H-SiC p-type substrate. Two different approaches of growing the n-type region were tested. The GaN was grown with the MBE technique using a polycrystalline GaN buffer, whereas the AlGaN was grown with CVD and an AlN buffer. The AlGaN had an aluminum mole fraction of around 0.1. Mesa structures were formed using Cl2 RIE of GaN/AlGaN, which showed good selectivity on 6H-SiC (about 1:6). A Ti metallization with subsequent RTA was used as contact to GaN and AlGaN, and the contact to 6H-SiC was liquid InGa. Both I-V and C-V measurements were performed on the heterojunction diode. The ideality factor of the diodes, doping concentration of the SiC, and the band alignment of the heterojunction were extracted. © 1999 Elsevier Science S.A.

  • 33. Danielsson, Erik
    et al.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Forsberg, U.
    Janzen, E.
    Investigation of thermal properties in fabricated 4H-SiC high-power bipolar transistors2002In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 389-393, no 2, p. 1337-1340Article in journal (Refereed)
    Abstract [en]

    Silicon Carbide bipolar junction transistors have been fabricated and investigated. The transistors had a maximmn current gain of approximately 10 times, and a breakdown voltage of up to 600 V. When operated at high power densities the device showed a clear self-heating effect, decreasing the current gain. The junction temperature was extracted during self-heating to approximately 150 °C, using the assumption that the current gain only depends on temperature. Thermal images of a device under operation were also recorded using an infrared camera, showing a significant temperature increase in the vicinity of the device. Physical device simulations have been used to analyze the measured data. The thermal conductivity is fitted to model the measured self-heating, and the lifetime in the base is fitted against the measurement of the current gain.

  • 34. Danielsson, Erik
    et al.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, S. K.
    Linthicum, K. J.
    Thomson, D. B.
    Nam, O. -H
    Davis, R. F.
    Dry etching and metallization schemes in a GaN/SiC heterojunction device process2000In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 338-342, p. 1049-1052Article in journal (Refereed)
    Abstract [en]

    Dry etching and metallization schemes are described for a GaN/SiC heterojunction. GaN was reactive ion etched in a chlorine based chemistry (Cl2/Ar), and an ICP etch was used on 4H-SiC using a fluorine based chemistry (SF6/Ar/O2). The etch rates obtained on GaN was above 400 nm/min. High sample temperature from self heating and large dc-bias was the probable cause for the high etch rate. The ICP etch rate on SiC approached 320 nm/min, and the etch selectivity to GaN was &gt;100. The metallization was based on Ti for both n-GaN and p-SiC. TLM and Kelvin structures were used to extract the specific contact resistivity, ρC. After a 950 °C anneal in N2 ρC on the GaN samples were below 1·10-6 Ωcm2 for sputtered contacts in room temperature, and an order of magnitude higher with evaporation. On p-SiC no ohmic behavior was found with a doping of 4·1018 cm-3, but the same contact metallization on highly doped areas (&gt;1020 cm-3) showed ohmic behavior with ρC below 10-4 Ωcm2.

  • 35. Del, Sepideh Khandan
    et al.
    Bornemann, Rainer
    Bablich, Andreas
    Schaefer-Eberwein, Heiko
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kowald, Torsten
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bolivar, Peter Haring
    Lemme, Max C.
    Optimizing the optical and electrical properties of graphene ink thin films by laser-annealing2015In: 2D Materials, ISSN 2053-1583, Vol. 2, no 1, article id 011003Article in journal (Refereed)
    Abstract [en]

    We demonstrate a facile fabrication technique for graphene-based transparent conductive films. Highly flat and uniform graphene films are obtained through the incorporation of an efficient laser annealing technique with one-time drop casting of high-concentration graphene ink. The resulting thin films are uniform and exhibit a transparency of more than 85% at 550 nm and a sheet resistance of about 30 kΩ/sq. These values constitute an increase of 45% in transparency, a reduction of surface roughness by a factor of four and a decrease of 70% in sheet resistance compared to un-annealed films.

  • 36. Del, Sepideh Khandan
    et al.
    Bornemann, Rainer
    Bablich, Andreas
    Schaefer-Eberwein, Heiko
    Li, Jiantong
    Kowald, Torsten
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bolivar, Peter Haring
    Lemme, Max C.
    University of Siegen, Germany.
    Optimizing the optical and electrical properties of graphene ink thin films by laser-annealing2015In: 2D Materials, ISSN 2053-1583, Vol. 2, no 1, article id 011003Article in journal (Refereed)
    Abstract [en]

    We demonstrate a facile fabrication technique for graphene-based transparent conductive films. Highly flat and uniform graphene films are obtained through the incorporation of an efficient laser annealing technique with one-time drop casting of high-concentration graphene ink. The resulting thin films are uniform and exhibit a transparency of more than 85% at 550 nm and a sheet resistance of about 30 k Omega/square. These values constitute an increase of 45% in transparency, a reduction of surface roughness by a factor of four and a decrease of 70% in sheet resistance compared to un-annealed films.

  • 37.
    Delekta, Szymon Sollami
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Smith, Anderson David
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Inkjet printed highly transparent and flexible graphene micro-supercapacitors2017In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 9, no 21, p. 6998-7005Article in journal (Refereed)
    Abstract [en]

    Modern energy storage devices for portable and wearable technologies must fulfill a number of requirements, such as small size, flexibility, thinness, reliability, transparency, manufacturing simplicity and performance, in order to be competitive in an ever expanding market. To this end, a comprehensive inkjet printing process is developed for the scalable and low-cost fabrication of transparent and flexible micro-supercapacitors. These solid-state devices, with printed thin films of graphene flakes as interdigitated electrodes, exhibit excellent performance versus transparency (ranging from a single-electrode areal capacitance of 16 mu F cm(-2) at transmittance of 90% to a capacitance of 99 mu F cm(-2) at transmittance of 71%). Also, transparent and flexible devices are fabricated, showing negligible capacitance degradation during bending. The ease of manufacturing coupled with their great capacitive properties opens up new potential applications for energy storage devices ranging from portable solar cells to wearable sensors.

  • 38.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Valerio, Sven
    KTH, School of Information and Communication Technology (ICT).
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O2013In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 160, no 11, p. D538-D542Article in journal (Refereed)
    Abstract [en]

    A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic precursor eliminates the need for a strong oxidizing agent (such as O-3) and provides a high deposition rate of similar to 1.5 angstrom/cycle. A thorough characterization of the process has been performed, identifying true ALD-type film growth in the temperature range 200-300 degrees C. The ALD process has been further investigated by extensive physical and electrical characterization of the deposited films in terms of-composition, crystalline phase, surface roughness and extraction of the dielectric constant. The films were found to be oxygen-rich Tm2O3, with low carbon impurity content at low deposition temperature and after annealing at 600 degrees C. The developed process produced polycrystalline films, with a surface roughness <1 nm RMS. Integration in MOS capacitors demonstrated well-behaved CV curves after annealing at 600 degrees C, with a relative dielectric constant of similar to 16.

  • 39.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs2013In: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS), IEEE , 2013, p. 122-125Conference paper (Refereed)
    Abstract [en]

    The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.

  • 40.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 20-25Article in journal (Refereed)
    Abstract [en]

    This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.

  • 41.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks2012In: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012, IEEE , 2012, p. 105-108Conference paper (Refereed)
    Abstract [en]

    This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 A) while preserving the electrical quality of the stack.

  • 42.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Thulium silicate interfacial layer for scalable high-k/metal gate stacks2013In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 10, p. 3271-3276Article in journal (Refereed)
    Abstract [en]

    Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.

  • 43.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks2014In: ULIS 2014: 2014 15th International Conference on Ultimate Integration on Silicon, 2014, p. 69-72Conference paper (Refereed)
    Abstract [en]

    Integration of high-k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high-k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS-compatible process for integration of thulium silicate (TmSiO) as interfacial layer, providing advantages in terms of EOT and channel mobility. This work demonstrates the compatibility of the TmSiO/HfO2 stack with the threshold voltage control techniques commonly employed in gate-last and gate-first integration schemes, namely the use of a dual-metal process and the integration of dielectric capping layers. We show that the flatband voltage can be set from -1V to +0.5V by proper choice of gate metal, while a shift of 150-400 mV is achievable by means of integration of Al2O3 or La2O3 capping layers.

  • 44.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs2015In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 3, no 5, p. 397-404, article id 7120903Article in journal (Refereed)
    Abstract [en]

    Integration of a high-k interfacial layer (IL) is considered the leading technological solution to extend the scalability of Hf-based high-k/metal gate CMOS technology. We have previously shown that thulium silicate (TmSiO) IL can provide excellent electrical characteristics and enhanced channel mobility at sub-nm EOT. This paper presents a detailed analysis of channel mobility in TmSiO/HfO<inf>2</inf>/TiN MOSFETs, obtained through measurements at varying temperature and under constant voltage stress. We show experimentally for the first time that integration of a high-k IL can benefit mobility by attenuating remote phonon scattering. Specifically, integration of TmSiO results in attenuated remote phonon scattering compared to reference SiO<inf>x</inf>/HfO<inf>2</inf> dielectric stacks having the same EOT, whereas it has no significant influence on remote Coulomb scattering.

  • 45.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Enhanced channel mobility by integration of sub-nm-EOT TmSiO/HfO2/TiNhigh-k/metal gate MOSFETsManuscript (preprint) (Other academic)
  • 46.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    (Invited) TmSiO As a CMOS-Compatible High-k Dielectric2016In: SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 6 / [ed] Roozeboom, F Narayanan, V Kakushima, K Timans, PJ Gusev, EP Karim, Z DeGendt, S, Electrochemical Society, 2016, no 4, p. 79-89Conference paper (Refereed)
    Abstract [en]

    Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

  • 47.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs2013In: 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), IEEE Computer Society, 2013, p. 155-158Conference paper (Refereed)
    Abstract [en]

    Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO 2/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 1013cm-2, yielding values of 180 and 75 cm2/Vs at EOT = 0.65 and 0.8 nm respectively.

  • 48.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 108, p. 24-29Article in journal (Refereed)
    Abstract [en]

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  • 49.
    Di Benedetto, Luigi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Strain balance approach for optimized signal-to-noise ratio in SiGe quantum well bolometers2009In: ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, 2009, p. 101-104Conference paper (Refereed)
    Abstract [en]

    This work presents thermal and electrical characterization of SiGe/Si multi-quantum wells (MQWs) with different layer profiles in complete bolometer structures. The thermal property of the bolometers was studied by measuring thermal coefficient of resistivity (TCR) through I-V curves for five temperatures (25, 40, 55, 80 and 100°C) and for four different pixel areas. The results show a strong dependency of TCR on the Si/SiGe layer thickness and the presence of dopant impurity in the MQW. The noise measurements of MQWs were performed carefully by eliminating all external contributions and the noise spectroscopy provided the noise characteristic parameters. The results demonstrate that the noise depends on the geometric size of the MQW and it increases with decreasing of the pixel area. The investigations show the noise level in the bolometer structures is sensitive to any dopant segregation from the contact layers.

  • 50.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Hillkirk, Leonardo
    KTH, Superseded Departments, Electronics.
    Linnros, Jan
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Dynamic avalanche in 3.3-kV Si power diodes1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 4, p. 781-786Article in journal (Refereed)
    Abstract [en]

    Measurements of the safe reverse recovery limit were performed for 3.3-kV Si power diodes using a novel optical experimental technique. In this experiment, influence of the junction termination is effectively eliminated by optical generation of a laterally-localized carrier plasma. The turn-off failures observed in measurements at two temperatures showed no temperature dependence and could not be reproduced in ordinary one-dimensional (1-D) or two-dimensional (2-D) device simulations. To simulate the stability of the current density toward current filamentation, two 1-D diodes with an area ratio 1:19 and a 10% difference in initial carrier plasma level, were simulated in parallel. This resulted in a strongly inhomogeneous current distribution, and a rapid reverse voltage fall resembling the measured turn-off failures. Inhomogeneous current distribution in these simulations appears as the current decay ceases due to impact ionization, in qualitative agreement with a current instability condition proposed by Wachutka [1].

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