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  • 1.
    Dubrova, Elena
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Teslenko, Maxim
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Martinelli, Andrés
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Kauffman networks: Analysis and applications2005In: ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, p. 479-484Conference paper (Refereed)
    Abstract [en]

    A Kauffman network is an abstract model of gene regulatory networks. Each gene is represented by a vertex. An edge from one vertex to another implies that the former gene regulates the latter. Statistical features of Kauffman networks match the characteristics of living cells. The number of cycles in the network's state space, called attractors, corresponds to the number of different cell types. The attractor's length corresponds to the cell cycle time. The sensitivity of attractors; to different kinds of disturbances, modeled by changing a network connection, the state of a vertex, or the associated function, reflects the stability of the cell to damage, mutations and virus attacks. In order to evaluate attractors, their number and lengths have to be computed. This problem is the major open problem related to Kauffman networks. Available algorithms can only handle networks with less than a hundred vertices. The number of genes in a cell is often larger. In this paper, we present a set of efficient algorithms for computing attractors in large Kauffman networks. The resulting software package is hoped to be of assistance in understanding the principles of gene interactions and discovering a computing scheme operating on these principles.

  • 2.
    Dubrova, Elena
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Teslenko, Maxim
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Martinelli, Andrés
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    On relation between non-disjoint decomposition and multiple-vertex dominators2004In: 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, IEEE , 2004, p. 493-496Conference paper (Refereed)
    Abstract [en]

    This paper addresses the problem of non-disjoint decomposition of Boolean functions. Decomposition has multiple applications in logic synthesis, testing and formal verification. First, we show that the problem of computing non-disjoint decompositions of Boolean functions can be reduced to the problem of finding multiple-vertex dominators of circuit graphs. Then, we prove that there exists an algorithm for computing all multiple-vertex dominators of a fixed size in polynomial time. Our result is important because no polynomial-time algorithm for non-disjoint decomposition of Boolean functions is known. A set of experiments on benchmark circuits illustrates our approach.

  • 3.
    Martinelli, Andrés
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Advanced algorithms for boolean decomposition2004Licentiate thesis, monograph (Other scientific)
  • 4.
    Martinelli, Andrés
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Advances in Functional Decomposition: Theory and Applications2006Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing.

    This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient.

    The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering.

    The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time.

    The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function.

    The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches.

    Finally we present two publications that resulted from the many detours we have taken along the winding path of our research.

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  • 5.
    Martinelli, Andrés
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Bengtsson, Tomas
    Dubrova, Elena
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    A BDD-based fast heuristic algorithm for disjoint decomposition2003In: The IEEE Asia and South Pacific Design Automation Conference 2003 (ASP-DAC 2003), January, 2003, Kitakyushu, Japan,  Asia and South Pacific Design Automation Conference, 2003, p. 191-196Conference paper (Refereed)
    Abstract [en]

    This paper presents a heuristic algorithm for disjointdecomposition of a Boolean function based on its ROBDDrepresentation. Two distinct features make the algorithm feasiblefor large functions. First, for an n-variable function, it checks onlyO(n2) candidates for decomposition out of O(2n) possible ones. Aspecial strategy for selecting candidates makes it likely that allother decompositions are encoded in the selected ones. Second,the decompositions for the approved candidates are computedusing a novel IntervalCut algorithm. This algorithm does notrequire re-ordering of ROBDD. The combination of both techniquesallows us to decompose the functions of size beyond thatpossible with the exact algorithms. The experimental results on582 benchmark functions show that the presented heuristic finds95% of all decompositions on average. For 526 of those functions,it finds 100% of the decompositions.

  • 6.
    Martinelli, Andrés
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Bengtsson, Tomas
    Dubrova, Elena
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Roth-Karp Decomposition of LargeBoolean Functions with Applicationto Logic Design2002In: Proceedings of NORCHIP 2002(NORSHIP'02), Copenhagen, Denmark, November 2002, pp. 183-189, 2002, p. 183-189Conference paper (Refereed)
  • 7.
    Martinelli, Andrés
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    An efficient structural technique for boolean decomposition2005In: VLSI Circuits and Systems II, Pts 1 and 2 / [ed] Lopez, JF; Fernandez, FV; LopezVillegas, JM; DelaRosa, JM, BELLINGHAM: SPIE-INT SOC OPTICAL ENGINEERING , 2005, Vol. 5837, p. 913-918Conference paper (Refereed)
    Abstract [en]

    Boolean decomposition techniques offer a powerful alternative to traditional algebraic methods when partitioning a circuit graph in the technology independent stage of the circuit design flow. These techniques usually require to transform the circuit from a structural representation to a representation based on Binary Decision Diagrams (BDDs). It is well known that BDDs can grow exponentially in some cases, so the power of Boolean decomposition comes at the expense of an exponential increase in the size of the circuit representation. The following stages in the design flow may suffer severely from the space penalty imposed on each partitioned block. To cope with this space explosion, each block of the partitioned circuit has to be re-synthesized before further processing. The extra re-synthesis, on the other hand, may impose a prohibitive time/space penalty on the design flow. This paper proposes an inexpensive technique to avoid re-synthesizing the BDD blocks obtained after Boolean decomposition. This technique works by structurally partitioning the original circuit representation, according to information provided by the partitioned BDD blocks. After all the blocks have been recovered, the BDDs are not needed and can be discarded. The resulting circuit will be proportional to the original circuit representation, and not to the intermediate BDD representation.

  • 8.
    Martinelli, Andrés
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Bound set selection and circuit re-synthesis for area/delay driven decomposition2005In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, p. 430-431Conference paper (Refereed)
    Abstract [en]

    This paper addresses two problems related to disjoint-support decomposition of Boolean functions. First, we present a heuristic for finding a subset of variables, X, which results in the disjoint-support decomposition f(X, Y) = h(g(X), Y) with a good area/delay trade-off. Second, we present a technique for re-synthesis of the original circuit implementing f (X, Y) into a circuit implementing the decomposed representation h(g(x), Y)Preliminary experimental results indicate that the proposed approach has a significant potential.

  • 9.
    Martinelli, Andrés
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Krenz, René
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Disjoint-support boolean decomposition combining functional and structural methods2004In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2004, 2004, p. 597-599Conference paper (Refereed)
    Abstract [en]

    This paper presents an algorithm for disjoint-support decomposition of Boolean functions which combines functional and structural approaches. First, a set of proper cut points is identified in the circuit by using dominator relations (structural method). Then, the circuit is partitioned along these cut points and a BDD-based decomposition is applied to the resulting smaller functions (functional method). Previous work on Boolean decomposition used only single methods and did not integrate a combined strategy. The experimental results show that the presented technique is more robust than a pure BDD-based approach and produces better-quality decompositions.

  • 10.
    Martinelli, Andrés
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Krenz, René
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Dubrova, Elena
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Roth-karp decomposition combining functional and structural techniques2003In: Proceedings of International Workshop on Logic Synthesis, 2003, p. 18-23Conference paper (Other academic)
  • 11.
    Teslenko, Maxim
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Martinelli, Andrés
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Bound-set preserving ROBDD variable orderings may not be optimum2005In: IEEE Transactions on Computers, ISSN 0018-9340, E-ISSN 1557-9956, Vol. 54, no 2, p. 236-237Article in journal (Refereed)
    Abstract [en]

    This paper reports a result concerning the relation between the best variable orderings of an ROBDD G(f) and the decomposition structure of the Boolean function f represented by G(f). It was stated in [1] that, if f has a decomposition of type f(X) = g(h(1)(Y-1), h(2)(Y-2), ..., h(k)(Y-k)), where {Y-i}, i is an element of {1, 2, ..., k}, is a partition of X, then one of the orderings which keeps the variables within the sets {Y-i} adjacent is a best ordering for G(f). Using a counterexample, we show that this statement is incorrect.

1 - 11 of 11
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  • apa
  • ieee
  • modern-language-association-8th-edition
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  • en-US
  • fi-FI
  • nn-NO
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  • Other locale
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