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  • 1.
    Chaourani, Panagiotis
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    Sequential 3D Integration - Design Methodologies and Circuit Techniques2019Doktoravhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.

    As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.

    The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.

    To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.

    Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.

  • 2.
    Chaourani, Panagiotis
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Towards Monolithic 3D Integration: A Design Flow2016Inngår i: CDNLive2016, Cadence User Conference EMEA, Munich, Germany, May 2-4, 2016, 2016Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Monolithic 3D (M3D) integration is considered as a key enabling technology for thecontinuation of Moore’s Law. To facilitate the study of M3D circuits, a design flow isclearly needed. In this work we discuss the potentials and challenges of thistechnology and present a design flow for M3D circuits which includes a M3D ProcessDesign Kit (PDK) with parametric extraction capabilities.

  • 3.
    Chaourani, Panagiotis
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Hellström, Per-Erik
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Rodriguez, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Onet, Raul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Enabling Area Efficient RF ICs through Monolithic 3D Integration2017Inngår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, s. 610-613, artikkel-id 7927059Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

  • 4.
    Chaourani, Panagiotis
    et al.
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Rodriguez, Saul
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Hellström, Per-Erik
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Rusu, Ana
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019Inngår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, nr 2, s. 468-480Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 5.
    Chaourani, Panagiotis
    et al.
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    Stathis, Dimitrios
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Rodriguez, Saul
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Hellström, Per-Erik
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Rusu, Ana
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018Inngår i: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

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