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  • 1.
    Colmenares, Juan
    et al.
    KTH, School of Electrical Engineering (EES), Electric power and energy systems.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electric power and energy systems.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Temperature Passive Components for Extreme EnvironmentsManuscript (preprint) (Other academic)
    Abstract [en]

    Silicon carbide is an excellent candidate when high temperature power electronics applications are considered. Integrated circuits as well as several power devices have been tested at high temperature. However, little attention has been paid to high temperature passive components that could enable the full SiC potential. In this work, the high temperature performances of different passive components have been studied. Integrated capacitors in bipolar SiC technology has been tested up to 300 °C and, two different designs of inductors have been tested up to 600 °C.

  • 2.
    Colmenares, Juan
    et al.
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Temperature Passive Components for Extreme Environments2016In: 2016 IEEE 4TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA), IEEE conference proceedings, 2016, p. 271-274Conference paper (Refereed)
    Abstract [en]

    Silicon carbide is an excellent candidate when high temperature power electronics applications are considered. Integrated circuits as well as several power devices have been tested at high temperature. However, little attention has been paid to high temperature passive components that could enable the full SiC potential. In this work, the high-temperature performances of different passive components have been studied. Integrated capacitors in bipolar SiC technology have been tested up to 300 degrees C and, three different designs of inductors have been tested up to 700 degrees C.

  • 3.
    Ekström, Mattias
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hou, Shuoben
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, Vol. 924, p. 389-392Conference paper (Refereed)
    Abstract [en]

    Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

  • 4.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development.

    To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized.

    Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process.

    Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated.

    This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.

  • 5.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A wafer-scale Ni-salicide contact technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. P197-P200Article in journal (Refereed)
    Abstract [en]

    A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

  • 6.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. 197-200Article in journal (Refereed)
    Abstract [en]

    A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.

  • 7.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

  • 8.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT).
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    500 degrees C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 38, no 10, p. 1429-1432Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for hightemperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (J(C)), lower on-resistance (R-ON), and more uniform current distribution. A maximum current gain (beta) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs aremeasured fromroom temperature to 500 degrees C. An open-base breakdown voltage (V-CEO) of > 50 V is measured for the devices.

  • 9.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Process variation tolerant 4H-SiC power devices utilizing trench structures2013In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 740-742, p. 809-812Article in journal (Refereed)
    Abstract [en]

    Silicon carbide (SiC) is one of the most attractive semiconductors for high voltage applications. The breakdown voltage of SiC-based devices highly depends on the variation of the fabrication process including doping of the epilayers and the etching steps. In this paper, we show a way to diminish this variability by employing novel trench structures. The influence of the process variations in terms of doping concentration and etching has been studied and compared with conventional devices. The breakdown voltage variation (ΔVBr) of 450 V and 2100 V is obtained for the ±20% variation of doping concentration of the devices with and without the trench structures, respectively. For ±20% variation in etching steps, the maximum ΔVBR of 380 V is obtained for the device with trench structures in comparison to 1800 V for the conventional structure without trench structures. These results show that the breakdown voltage variation is significantly reduced by utilizing the proposed structure.

  • 10.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetteling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices2016In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 858, p. 978-981Article in journal (Other (popular science, discussion, etc.))
    Abstract [en]

    High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) are fabricated and optimized in terms of the length and remaining dose of JTEs. It is found that the JTE1 is the most effective one in spreading the electric field. Hence, for a given total termination length, a decremental JTE length from the innermost edge to the outermost mesa edge of the device results in better modification of the electric field. A breakdown voltage of 4.95 kV is measured for the modified device, which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches are fabricated. It is presented that the maximum current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

  • 11.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4366-4372Article in journal (Refereed)
    Abstract [en]

    A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H–SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.

  • 12.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    4.5-kV 20-mΩ. cm2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821, p. 838-841Article in journal (Refereed)
    Abstract [en]

    A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.

  • 13.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 2, p. 168-170Article in journal (Refereed)
    Abstract [en]

    Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.

  • 14.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modification of etched junction termination extension for the high voltage 4H-SiC power devices2016In: Silicon Carbide and Related Materials, Trans Tech Publications, 2016, p. 978-981Conference paper (Refereed)
    Abstract [en]

    High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) were fabricated and optimized in terms of the length (LJTE) and remaining dose (DJTE) of JTEs. It is found that for a given total termination length (Σ LJTEi), a decremental JTE length from the innermost edge to the outermost mesa edge of the device will result in better modification of the electric field. A breakdown voltage (BV) of 4.95 kV is measured for the modified device which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches were fabricated. The maximum current gain of 40 is achieved for a single finger device with the emitter width of 40 μm at IC = 0.25 A (JC = 310 A/cm2) which corresponds to RON = 33 mΩ.cm2. It is presented that the current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

  • 15.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. Ascatron AB, Sweden.
    Thierry-Jebali, N.
    Reshanov, S. A.
    Kaplan, W.
    Zhang, A.
    Lim, J. -K
    Bakowski, M.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Schöner, A.
    Design optimization of a high temperature 1.2 kV 4H-SiC buried grid JBS rectifier2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Inc., 2017, Vol. 897, p. 455-458Conference paper (Refereed)
    Abstract [en]

    1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 250ºC is analyzed and measured on wafer level. The forward voltage drop of 1.1 V at 100 A/cm2 and 3.8 V at 1000 A/cm2 is measured, respectively. At reverse voltage of 1 kV, a leakage current density below 0.1 μA/cm2 and below 0.1 mA/cm2 is measured at 25 and 250ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.

  • 16.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Silicon Carbide BJT Oscillator Design Using S-Parameters2018In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018Conference paper (Refereed)
    Abstract [en]

    Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

  • 17.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Silicon carbide BJT oscillator design using S-parameters2019In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 674-678Conference paper (Refereed)
    Abstract [en]

    Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation is further aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, an alternative small-signal, S-parameter based design method can be employed directly without going into complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 °C) was accessed by on-wafer probing and connected by RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

  • 18.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH.
    Schröder, Stephan
    KTH.
    Rodriguez, Saul
    KTH.
    Malm, B. Gunnar
    KTH.
    Östling, Mikael
    KTH.
    Rusu, Ana
    KTH.
    An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

  • 19.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, Bengt Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    An Intermediate Frequency Amplifier for High-Temperature Applications (vol 65, pg 1411, 2018)2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 8, p. 3694-3694Article in journal (Refereed)
    Abstract [en]

    This correspondence highlights an error in the above-titled paper. The corrected material is presented here.

  • 20.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Zumbro, John E.
    University of Arkansas.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)
    Abstract [en]

    This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

  • 21.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zumbro, John E.
    University of Arkansas.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)
    Abstract [en]

    This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

  • 22. Kargarrazi, S.
    et al.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT).
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT).
    500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed)
    Abstract [en]

    This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).

  • 23.
    Kargarrazi, Saleh
    et al.
    Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Saggini, Stefano
    DIEGM Univ Udine, I-33100 Udine, Italy..
    Senesky, Debbie
    Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    500 degrees C SiC PWM Integrated Circuit2019In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 34, no 3, p. 1997-2001Article in journal (Refereed)
    Abstract [en]

    This letter reports on a high-temperature pulsewidth modulation (PWM) integrated circuit microfabricated in 4H-SiC bipolar process technology that features an on-chip integrated ramp generator. The circuit has been characterized and shown to be operational in a wide temperature range from 25 to 500 degrees C. The operating frequency of the PWM varies in the range of 160 to 210 kHz and the duty cycle varies less than 17% over the entire temperature range. The proposed PWM is suggested to efficiently and reliably control power converters in extreme environments.

  • 24.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Östling,
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Gated base structure for improved current gain in SiC bipolar technology2017In: 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017, Editions Frontieres , 2017, p. 122-125Conference paper (Refereed)
    Abstract [en]

    Silicon Carbide (SiC) bipolar integrated circuits are a promising technology for extreme environment applications. SiC bipolar technology shows stable operation over a wide range of temperature. However, the current gain of the devices is suffering from high surface recombination, due to poor oxide passivation. In this paper we propose a gated base structure that offers improved current gain control. A polysilicon gate is formed on the passivation oxide on top of the base-link region. We investigate the current gain as a function of gate bias and temperature. A negative gate bias improves the gain at low collector current by more than 30% by suppressing the surface recombination. Measurements are presented at temperatures ranging from 300 K to 550 K and the gain is consistently improved. The proposed structure is also useful as a process monitor for the passivation oxide quality.

  • 25.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, B.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hassan, J. U.
    Bergman, P.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes2015In: Proceedings of the International Symposium on Power Semiconductor Devices and ICs, IEEE conference proceedings, 2015, p. 269-272Conference paper (Refereed)
    Abstract [en]

    Degradation-free ultrahigh-voltage (>10 kV) PiN diodes using on-axis 4H-SiC with low forward voltage drop (VF = 3.3 V at 100 A/cm2) and low differential on-resistance (RON = 3.4 m.cm2) are fabricated, measured, and analyzed by device simulation. The devices show stable on-state characteristics over a broad temperature range up to 300 °C. They show no breakdown up to 10 kV, i.e., the highest blocking capability for 4H-SiC devices using on-axis to date. The minority carrier lifetime (τP) is measured after epitaxial growth by time resolved photoluminescence (TRPL) technique at room temperature. The τP is measured again after device fabrication by open circuit voltage decay (OCVD) up to 500 K.

  • 26.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Area-optimized JTE simulations for 4.5 kV non ion-implanted sic BJT2013In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 740-742, p. 974-977Article in journal (Refereed)
    Abstract [en]

    Non ion-implantation mesa etched 4H-SiC BJT with three-zone JTE of optimized lengths and doses (descending sequences) has been simulated. This design presents an efficient electric field distribution along the device. The device area has been optimized and considerably reduced. As a result of this comprehensive optimization, a high breakdown voltage (>6 kV) and high current gain (β=50) have been achieved; meanwhile the device area with a constant emitter and base contact area (300×300 μm2) will be reduced by about 30%.

  • 27.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Jacobs, Keijo
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 1, p. 63-66Article in journal (Refereed)
    Abstract [en]

    Implantation-free mesa-etched ultra-high-voltage (0.08 mm(2)) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm(2) is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.

  • 28.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance2015In: 2015 IEEE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD), IEEE , 2015, p. 249-252Conference paper (Refereed)
    Abstract [en]

    Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of beta = 44 at a current density of 472 A/cm(2), and a specific on-resistance of R-ON = 18.8 m Omega.cm(2) is obtained for the device. The device shows a negative temperature coefficient of the current gain (beta = 14.5 at 200 degrees C) and a positive temperature coefficient of on-resistance (R-ON = 57.3 m Omega.cm(2) at 200 degrees C).

  • 29.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    15 kV-Class implantation-Free 4H-SiC BJTs with Record High Current Gain2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Other academic)
    Abstract [en]

    Implantation-free mesa-etched ultra-high-voltage 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension (O-JTE) is utilized in order to obtain a high and stable breakdown voltage without ion implantation. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared. The base size effect is investigated in order to improve current gain.

  • 30.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Comprehensive Study on the Geometrical Effects in High Power 4H-SiC BJTs2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 3, p. 882-887Article in journal (Refereed)
    Abstract [en]

    Geometrical effects on the forward characteristics of high-power bipolar junction transistors are studied.An implantation-free area optimized junction termination is implemented in order to have a stable breakdown voltage. The effect of varying the emitter-base geometry, i.e., the emitter width (WE), the base width (WB), emitter contact–emitter edge distance (Wn), and base contact–emitter edge (Wp) on the on-state characteristics is studied in the different emitter cell geometries. The emitter size effect shows the highest influence on the current gain (β). It shows a significant effect on the β (single finger design, about 61%; square cell geometry, about 98%;hexagon cell geometry, about 90%). The base size effect also shows a significant improvement on the β of about 23% at a given WE.

  • 31.
    Salemi, Arash
    et al.
    KTH.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    10+ kV implantation-free 4H-SiC PiN diodes2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Ltd , 2017, p. 423-426Conference paper (Refereed)
    Abstract [en]

    Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.

  • 32.
    Salemi, Arash
    et al.
    KTH.
    Elahipanah, Hossein
    KTH.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN Diodes2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, p. 568-572Conference paper (Refereed)
    Abstract [en]

    Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.

  • 33.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Geometrical effect dependency on the on-state characteristics in 5.6 kV 4H-SiC BJTs2016In: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015, Trans Tech Publications Ltd , 2016, p. 958-961Conference paper (Refereed)
    Abstract [en]

    The influence of varying the emitter-base geometry, i.e., the emitter width (WE), emitter contact-emitter edge distance (Wn), and base contact-emitter edge (Wp) on the on-state characteristics in 5.6 kV implantation free 4H-SiC BJTs is investigated. The BJTs present a clear emitter size effect pointing out that surface recombination has a significant influence on current gain (β). The results show that the influence of varying Wp on the β is higher than Wn. A distance of 3 μm between emitter contact and base contact to the emitter edge (Wn = Wp = 3 μm) is the optimized value to have a BJT with a high β, and low on-resistance (RON) at a given WE.

  • 34.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Investigation of the breakdown voltage in high voltage 4H-SiC BJT with respect to oxide and interface charges2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821-823, p. 834-837Article in journal (Refereed)
    Abstract [en]

    Ion implantation in silicon carbide (SiC) induces defects during the process. Implantation free processing can eliminate these problems. The junction termination extension (JTE) can also be formed without ion implantation in SiC bipolar junction transistor (BJT) using a well-controlled etching into the epitaxial base layer. The fixed charges at the SiC/SiO2 interface modify the effective dose of the JTEs, leakage current, and breakdown voltage. In this paper the influence of fixed charges (positive and negative) and also interface trap density at the SiC/SiO2 interface on the breakdown voltage in 4.5 kV 4H-SiC non-ion implanted BJT have been simulated. SiO2 as a surface passivation layer including interface traps and fixed charges has been considered in the analysis. Simulation result shows that the fixed charges influence the breakdown voltage significantly more than the interface traps. It also shows that the positive fixed charges reduce the breakdown voltage more than the negative fixed charges. The combination of interface traps and fixed charges must be considered when optimizing the breakdown voltage.

  • 35.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 10, p. 1069-1072Article in journal (Refereed)
    Abstract [en]

    Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (R-ON), current density (J(C)), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.

  • 36.
    Shakir, Muhammad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH.
    Hedayati, Raheleh
    KTH.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Electrical characterization of integrated 2-input TTL NAND Gate at elevated temperature, fabricated in bipolar SiC-technology2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, Vol. 924, p. 958-961Conference paper (Refereed)
    Abstract [en]

    This work presents the design and electrical characterization of in-house-fabricated 2-input NAND gate. The monolithic bipolar 2-input NAND gate employing transistor-transistor logic (TTL) is demonstrated in 4H-SiC and operates over a wide range of temperature and supply voltage. The fabricated circuit was characterized on the wafer by using a hot-chuck probe-station from 25 °C up to 500 °C. The circuit is also characterized over a wide range of voltage supply i.e. 11 to 20 V. The output-noise margin high (NMH) and output-noise margin low (NML) are also measured over a wide range of temperatures and supply voltages using voltage transfer characteristics (VTC). The transient response was measured by applying two square waves of, 5 kHz and 10 kHz. It is demonstrated that the dynamic parameters of the circuit are temperature dependent. The 2-input TTL NAND gate consumes 20 mW at 500 °C and 15 V.

  • 37.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    State of the art Power Switching Devices in SiC and their Applications2016In: 2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), IEEE, 2016, p. 122-123Conference paper (Refereed)
    Abstract [en]

    This paper gives an overview of the current state of the art device technology for SiC discrete devices and applications. The superior switching performance is discusses as well as the energy efficiency of SiC devices. New emerging applications of SiC devices are also discussed focusing on high temperature capability such as integrated digital and analog circuits up to 600 C. Finally, MEMS and Bio applications will be briefly reviewed.

1 - 37 of 37
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