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  • 1.
    Atallah, Jad. G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A direct conversion WiMAX RF receiver front-end in CMOS technology2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 37-40Conference paper (Refereed)
    Abstract [en]

    This paper presents a direct conversion RF receiver front-end supporting the WiMAX standard. The front-end is implemented in 0.18um CMOS technology and designed using the ARCHER software. It shows how the design flow can be accelerated starting from the standard specifications and going down to schematics. All this is accompanied by test benches to extract the relevant metrics. This front-end provides a total gain of 31dB, a noise figure of 3.3dB, an IIP2 of 49.5dBm, and an IIP3 of -13.8dBm.

  • 2.
    Chaourani, Panagiotis
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Onet, Raul
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Enabling Area Efficient RF ICs through Monolithic 3D Integration2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 610-613, article id 7927059Conference paper (Refereed)
    Abstract [en]

    The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

  • 3.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dürrenfeld, P.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Gothenburg, Sweden.
    A highly tunable microwave oscillator based on MTJ STO technology2014In: Microwave and optical technology letters (Print), ISSN 0895-2477, E-ISSN 1098-2760, Vol. 56, no 9, p. 2092-2095Article in journal (Refereed)
    Abstract [en]

    This article presents a fully ESD-protected, highly tunable microwave oscillator based on magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology. The oscillator consists of a compact MTJ STO and a 65 nm CMOS wideband amplifier, which amplifies the RF signal of the MTJ STO to a level that can be used to drive a PLL. The (MTJ STO+amplifier IC) pair shows a measured quality factor (Q) of 170 and a wide tunability range from 3 to 7 GHz, which demonstrate its potential to be used as a microwave oscillator in multiband, multistandard radios.

  • 4.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I: Analytical Model of the MTJ STO2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1037-1044Article in journal (Refereed)
    Abstract [en]

    Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.

  • 5.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II: Verilog-A Model Implementation2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1045-1051Article in journal (Refereed)
    Abstract [en]

    The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.

  • 6.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Redjai Sani, Sohrab
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of GMR-based spin torque oscillators and CMOS circuitry2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 111, p. 91-99Article in journal (Refereed)
    Abstract [en]

    This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

  • 7.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Alarcon, Eduard
    UPC Universitat Politecnica de Catalunya Barcelona, Spain.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 2 GHz - 8.7 GHz Wideband Balun-LNA with Noise Cancellation and Gain Boosting2012In: PRIME 2012: Proceedings of the 8th Coference on Ph.D. Research in Microelectronics and Electronics, 2012, IEEE conference proceedings, 2012, p. 59-62Conference paper (Refereed)
    Abstract [en]

    A wideband Balun-LNA covering the operation frequency range of magnetic tunnel junction Spin Torque Oscillator is presented. The LNA is a combination of common-source and cross-coupled common-gate stages, which provides wideband matching and noise cancellation, as well as gain boosting. The internal feedback introduced by the cross-coupling allows an additional degree of freedom to select transistor sizes and bias by decoupling the impedance matching, noise, and gain imbalance trade-offs which are present in similar topologies. Two LNAs using the proposed technique are designed in 65nm CMOS. The LNAs have a simulated bandwidth of  2 GHz - 8.7 GHz, gain of 16 dB, IIP3 of -3.5 dBm,  and NF < 3.8 dB while consuming 3.72 mW from a 1.2 V power supply.

  • 8.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wideband Amplifier Design for Magnetic Tunnel JunctionBased Spin Torque Oscillators2012In: Proc. of GigaHertz Symposium 2012, 2012Conference paper (Refereed)
    Abstract [en]

    Spin torque oscillator (STO) is a novel current-control-oscillator (CCO), based on two spintronic effects: spin momentum transfer torque and magneto-resistance (MR). It features large tunability, miniature size, high integration level, high quality factor, high operation frequency, etc., which makes it a promising technology for microwave and radar applications. However, the STO is still an immature technology, which requires intensive research for improving the spectrum purity and the output power performance [1]. This paper proposes a wideband amplifier targeting magnetic tunnel junction (MTJ) type of STO device, which compensates the low output power of the STO.

        The MTJ STO devices can cover a large part of ultra-wideband (UWB) from 3 - 8 GHz and provide an output power from -60 dBm to -40 dBm by tuning the bias DC current and the magnetic field [2][3]. One important and potential application of STO device is a local oscillator (LO) in an RF transceiver. To achieve this task, the amplifier requires a gain of 45 - 65 dB. In addition, the source impedance of different MTJ STO devices varies from a dozen to several hundred Ohms, which makes the amplifier design challenging. An universal amplifier, which fulfills the extracted design requirements, is proposed. It is composed of two types of Balun-LNAs depending on the MR of STO devices as the input stages, a broadband limiting amplifier chain and an output buffer. A combination of a common source (CS) stage and a cross-coupled common gate (CG) stage is employed for the input Balun-LNA in the low impedance case while a cascoded CS stage is used in the high impedance case. The output of both LNAs is connected to a limiting amplifier chain, which provides enough voltage gain. An output buffer is used as the output stage to convert the balanced output to single-ended output and to match the output impedance to 50 Ohms.

        The proposed wideband amplifier for MTJ STO is implemented in a 65nm CMOS process with   1.2 V supply. In the band of interest, it exhibits 55 dB gain with a maximum noise figure (NF) of    4.5 dB in the small MR case, and a 59 dB gain with a maximum NF of 3 dB in the large MR case. Besides the low noise performance and the high gain, the simulation results of the proposed amplifier also show that it has low power consumption and moderate impedance matching in the frequency range of 3 - 8 GHz, which is suitable for MTJ STO applications.

  • 9.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An Inductorless Wideband Balun-LNA for Spin Torque Oscillator-based Field Sensing2014In: Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on, IEEE conference proceedings, 2014, p. 36-39Conference paper (Refereed)
    Abstract [en]

    This paper presents a wideband inductorless Balun-LNA targeting spin torque oscillator-based magnetic field sensing applications. The LNA consistsof a CS stage combined with a cross-coupled CG stage, which offers wideband matching, noise/distortion cancellation and gain boosting, simultaneously. The Balun-LNA is implemented in a 65 nm CMOS technology, and it is fully ESD-protected and packaged. Measurement results show a bandwidth of 2 GHz - 7 GHz, a voltage gain of 20 dB, an IIP3 of +2 dBm, and a maximum NF of 5 dB. The LNA consumes 3.84 mW from a 1.2 V power supply and occupies a total silicon area of 0.0044 mm2. The measurement results demonstrate that the proposed Balun-LNA is highly suitable for the STO-based field sensing applications.

  • 10.
    Dora, Ayadi
    et al.
    University of Sfax, Tunisia .
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Loulou, Mourad
    University of Sfax, Tunisia.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    System level design of radio frequency receiver for IEEE 802.16 standard2008In: 3rd International Design and Test Workshop, 2008, IDT 2008, 2008, p. 82-86Conference paper (Refereed)
    Abstract [en]

    this paper presents a system level design of radio frequency receiver supporting WiMAX mobile standard. Based on direct conversion receiver, the distribution of the total radio system specifications to the individual receiver components is discussed. System level design techniques and theoretical calculation are developed. Simulation results and system simulation level are introduced for noise figure (NF), gain and linearity (third order intercept point, IIP3). Specifications obtained from the received budget can indicate that the noise and the linearity depend on the gain performance of the corresponding circuit blocks. The receiver achieves a total gain of 23dB and an IIP3 of -7.8dBm for low gain mode. It provides up to 68dB gain, 6.5dB noise figure and -16dBm IIP3 for high gain mode.

  • 11.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Low-Power CT Incremental 3rd Order Sigma Delta ADC for Biosensor Applications2013In: IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, ISSN 1549-8328, Vol. 60, no 1, p. 25-36Article in journal (Refereed)
    Abstract [en]

    This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15- mCMOStechnology,while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator’s power dissipation is 96 W from a 1.6 V power supply. This translates into the best figure-ofmerit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts.

  • 12.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    On Continuous-Time Incremental Sigma Delta ADCs With Extended Range2013In: IEEE Transactions on Instrumentation and Measurement, ISSN 0018-9456, E-ISSN 1557-9662, Vol. 62, no 1, p. 60-70Article in journal (Refereed)
    Abstract [en]

    In this paper, the use of continuous-time implementation in extended-range (ER) incremental sigma-delta analog-to-digital converters is analyzed in order to explore a possible solution to low-power multichannel applications. The operation principle, possible loop filter topologies, and critical issues are considered using a general approach. It is demonstrated that, in order to fully benefit from ER, careful attention has to be paid to the analog-digital transfer function mismatches. A third-order single-bit topology validates the theoretical analysis. Its performance is evaluated while the impact of key circuit nonidealities is quantified through behavioral-level simulations. It is shown that, by applying analog-digital mismatch compensation in the digital domain, it is possible to relax the amplifiers' finite gain-bandwidth product and finite dc gain requirements, thus allowing a power-conscious alternative.

  • 13.
    Grimaldi, Rocco
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 10-bit 5kHz level-crossing ADC2011In: 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011, 2011, p. 564-567Conference paper (Refereed)
  • 14.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Monolithic, 500 degrees C Operational Amplifier in 4H-SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 7, p. 693-695Article in journal (Refereed)
    Abstract [en]

    A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature operation of the amplifier is demonstrated from 25 degrees C to 500 degrees C. The measured closed loop gain is around 40 dB for all temperatures whereas the 3 dB bandwidth increases from 270 kHz at 25 degrees C to 410 kHz at 500 degrees C. The opamp achieves 1.46 V/mu s slew rate and 0.25% total harmonic distortion. This is the first report on high temperature operation of a fully integrated SiC bipolar opamp which demonstrates the feasibility of this technology for high temperature analog integrated circuits.

  • 15.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH.
    Schröder, Stephan
    KTH.
    Rodriguez, Saul
    KTH.
    Malm, B. Gunnar
    KTH.
    Östling, Mikael
    KTH.
    Rusu, Ana
    KTH.
    An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

  • 16.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zumbro, John E.
    University of Arkansas.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)
    Abstract [en]

    This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

  • 17.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pandey, Himadri
    University of Siegen.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    University of Siegen.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Optimization of a Compact I–V Model forGraphene FETs: Extending Parameter Scalability for Circuit Design Exploration2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3870-3875Article in journal (Refereed)
    Abstract [en]

    An optimization of the current-to-voltage transfer characteristic of a graphene FET (GFET) compact model, based on drift-diffusion carrier transport, is presented. The improved accuracy at Dirac point extends the model usability for GFETs when scaling parameters, such as voltage supply, gate length, oxide thickness, and mobility, for circuit design exploration. The model's accuracy is demonstrated through fitting to GFETs processed in-house. The model has been written in a standard behavioral language, and extensively run in an analog circuit simulator for designing basic circuits, such as inverters and cascode cells, demonstrating its robustness.

  • 18.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Department of Electrical Engineering and Computer Science Technology, University of Siegen, Siegen, Germany.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Design exploration of graphene-FET based ring-oscillator circuits: A test-bench for large-signal compact models2015In: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Communications Society, 2015, p. 2716-2719Conference paper (Refereed)
    Abstract [en]

    This paper presents a design-oriented characterization of ring-oscillator (RO) circuits based on complementary-inverters (INVs) implemented with graphene-FET (GFET) devices. A large-signal GFET compact model based on drift-diffusion transport is benchmarked at the circuit level against a second GFET compact model based on virtual source. Transient-based simulations of a 3-cell RO yield performance metrics in terms of operating frequency and voltage dynamic range. Against these metrics, a comprehensive design space exploration covering as input design variables parameters as GFET gate-oxide thickness tOX and channel-length L is presented. Methodologically, the work presents a general-purpose design framework, illustrated for ROs, which establishes a vertical circuit-device co-design environment. Its double-fold outcome is to provide guidelines both to bottom-up dimension and size the circuit, as well as top-down refine GFET device models and in turn GFET technology.

  • 19.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed)
    Abstract [en]

    This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

  • 20.
    Ivanisevic, Nikola
    et al.
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM2016In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), Vancouver, Canada: IEEE, 2016, article id 7604762Conference paper (Refereed)
    Abstract [en]

    This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

  • 21.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation2018Conference paper (Refereed)
    Abstract [en]

    A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

  • 22.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach2017In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy, 2017Conference paper (Refereed)
    Abstract [en]

    Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

  • 23. Kargarrazi, S.
    et al.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT).
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT).
    500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed)
    Abstract [en]

    This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).

  • 24.
    Kargarrazi, Saleh
    et al.
    Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT).
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT). KTH Royal Inst Technol, Sch Informat & Commun Technol, S-16440 Stockholm, Sweden..
    500 degrees C, High Current Linear Voltage Regulator in 4H-SiC BJT Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed)
    Abstract [en]

    This letter reports on a fully integrated 2-A linear voltage regulator operational in a wide temperature range from 25 degrees C up to 500 degrees C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 degrees C) and high-load driving capabilities (up to 2 A).

  • 25.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Dual-Output Thermoelectric Energy Harvesting Interface with 86.6% Peak Efficiency at 30 μW and Total Control Power of 160 nW2016In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173XArticle in journal (Refereed)
    Abstract [en]

    A thermoelectric energy harvesting interface based on a single-inductor dual-output (SIDO) boost converter is presented. A system-level design methodology combined with ultra-low power circuit techniques reduce the power consumption and minimize the losses within the converter. Additionally, accurate zero-current switching (ZCS) and zero-voltage switching (ZVS) techniques are employed in the control circuit to ensure high conversion efficiency at μW input power levels. The proposed SIDO boost converter is implemented in a 0.18 μm CMOS process and can operate from input voltages as low as 15 mV. The measurement results show that the converter achieves a peak conversion efficiency of 86.6% at 30 μW input power.

  • 26.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT).
    A High-Efficiency Energy Harvesting Interface for Implanted Biofuel Cell and Thermal Harvesters2017In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 33, no 5, p. 4125-4134, article id 7940053Article in journal (Refereed)
    Abstract [en]

    A dual-source energy harvesting interface that combines energy from implanted glucose biofuel cell and thermoelectric generator is presented. A single-inductor dual-input dual-output boost converter topology is employed to efficiently transfer the extracted power to the output. A dual-input feature enables the simultaneous maximum power extraction from two harvesters, while a dual-output allows a control circuit to perform complex digital functions at nW power levels. The control circuit reconfigures the converter to improve the efficiency and achieve zero-current and zero-voltage switching. The measurement results of the proposed boost converter, implemented in a 0.18 μm CMOS process, show a peak efficiency of 89.5% when both sources provide a combined input power of 66 μW. In the single-source mode, the converter achieves a peak efficiency of 85.2% at 23 μW for the thermoelectric source and 90.4% at 29 μW for the glucose biofuel cell. The converter can operate from minimum input voltages of 10 mV for the thermoelectric source and 30 mV for the glucose biofuel cell. 

  • 27.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    An Adaptive FET Sizing Technique for HighEfficiency Thermoelectric Harvesters2016In: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo: IEEE, 2016, p. 504-507Conference paper (Refereed)
    Abstract [en]

    A theoretical analysis of losses in low power thermoelectric harvester interfaces is used to find expressions for properly sizing the power transistors according to the input voltage level. These expressions are used to propose an adaptive FET sizing technique that tracks the input voltage level and automatically reconfigures the converter in order to improve its conversion efficiency. The performance of a low-power thermoelectric energy harvesting interface with and without the proposed technique is evaluated by circuit simulations under different input voltage/power conditions. The simulation results show that the proposed technique improves the conversion efficiency of the energy harvesting interface up to 12% at the lowest input voltage/power levels.

  • 28.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An Efficient Boost Converter Control for Thermoelectric Energy Harvesting2013In: Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on, IEEE conference proceedings, 2013, p. 385-388Conference paper (Refereed)
    Abstract [en]

    This paper presents an ultra-low power controlcircuit for a DC-DC boost converter targeting implantablethermoelectric energy harvesting applications. Efficiency of theinput converter is enhanced by utilizing zero-current switchingtechnique. Adaptive delay between ON states of switches assureszero-voltage switching of synchronous rectifier and reducesswitching losses. The control circuit employing both techniquesconsumes an average power of 620nW. This allows the converterto operate from harvested power below 5μW. For voltageconversion ratios above 20, the proposed circuits and techniquesdemonstrate efficiency improvement compared to the state-of-the-art solutions.

  • 29.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Analysis of Dead Time Losses in Energy Harvesting Boost Converters for Implantable Biosensors2014In: NORCHIP, 2014, IEEE conference proceedings, 2014, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Efficiency of an ultra-low power energy harvesting dc-dc converter depends on its losses and the power consumption of the control circuit. Unlike other loss mechanisms, losses related to dead times have not been thoroughly studied. Therefore, in most cases these losses are not adequately suppressed. This paper investigates dead time losses and their impact on the overall system efficiency. Simple expressions for fast estimation of dead time losses are derived. Analysis shows that in many applications where high voltage conversions are required, such as implantable biosensors, the efficiency reduction due to these losses can easily exceed 2%. The analysis is validated using an adaptive dead time circuit which minimizes the associated losses and improves the overall system efficiency according to the calculated values.

  • 30.
    Lemme, Max C.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Graphene for More Moore and More Than Moore applications2012In: IEEE Silicon Nanoelectronics Workshop, SNW, IEEE , 2012, p. 6243322-Conference paper (Refereed)
    Abstract [en]

    Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm 2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment [1, 2] and high contact resistance [3, 4]. In addition, graphene has no energy band gap (Figure 1) and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour [5]. This has steered interest away from logic to analog radio frequency (RF) applications [6, 7]. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology [8]. GFETs slightly lag behind in maximum cut-off frequency F T,max (Figure 2) up to a carrier mobility of 3000 cm 2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves.

  • 31.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Security and Privacy Issues in a GPS-enabled Mobile Application for Smart Traffic2010In: Proceedings of Smart Mobility Conference, 2010, 2010Conference paper (Refereed)
  • 32.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    MobiTraS: a mobile application for a Smart Traffic System2010In: Proceedings of the 8th IEEE International NEWCAS Conference, IEEE , 2010, p. 365-368Conference paper (Refereed)
    Abstract [en]

    Traffic monitoring systems deployed until now, use data collected mainly through fixed sensors. Advances on the modern mobile devices have made possible the development of S mart Traffic Systems, which use the traffic information g athered by the drivers' mobile devices to provide route guidance. Our work is focused on building a Real-Time Traffic Information System based mobile devices, which are used for both acquiring traffic information data and for providing feedback and guidance to drivers. This paper presents an analysis of the system, its security risks and requirements for dynamic route guidance together with possible solutions. A key component of the system is the mobile application that gathers data in an encrypted way and displays information to the users. The developed JavaME mobile application and its security/privacy features are also described.

  • 33.
    Morici, Andrea
    et al.
    Universita Politecnica delle Marche.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Turchetti, C.
    Universita Politecnica delle Marche.
    A 3.6 mW 90 nm CMOS 2.4 GHz Receiver Front-End Design for IEEE 802.15.4 WSNs2009In: ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, New York: IEEE , 2009, p. 77-80Conference paper (Refereed)
    Abstract [en]

    In this paper a low-power design of an integrated RF receiver for Wireless Sensor Networks (WSNs) in 90nm CMOS technology is proposed. The receiver is IEEE 802.15.4 physical specifications compliant. It is designed to operate in ISM band at 2.45 GHz center frequency. Target devices for this kind of transceiver are low-cost battery powered smart embedded devices and sensors. The receiver is designed to reduce the count of external components in the final system, integrating on silicon the balun for single-ended to differential conversion. The receiver is composed of an inductorless Low Noise Amplifier (LNA), a buffer stage, I and Q passive mixers and Variable Gain Amplifiers (VGAs) that also act as second order filters. A novel integration of balun into the LNA is described. The system is designed to have direct conversion from RF to 6 MHz low-IF. Voltage supply is 1.2 V with a current consumption of 3 mA including necessary biasing networks, and the total power consumption is 3.6 mW. The complete voltage gain is more than 41.5 dB with a Noise Figure (NF) of 12.6 dB. The receiver layout exhibits an area of only 0.12 mm(2). Simulations are provided, including mismatch scenarios.

  • 34. Onet, Raul
    et al.
    Neag, Marius
    Kovacs, Istvan
    Topa, Marina Dana
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Compact Variable Gain Amplifier for a Multistandard WLAN/WiMAX/LTE Receiver2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 1, p. 247-257Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel single-stage VGA architecture that employs two Gm cells, a voltage-controlled current attenuator, resistors and capacitors. The gain can be changed in three large steps by using digital controls, and continuously within these steps. The VGA bandwidth and output-related IP3 and 1dBCP are independent of the gain setting; the bandwidth can be programmed through a digitally-controlled capacitor array placed at its output. The proposed architecture was employed to realize the VGA for a WLAN/WiMAX/LTE radio receiver. Die area and power consumption were reduced by implementing the two Gm cells with one instantiation of a high-linearity Gm-core and scaled outputs; also, the current attenuator was implemented with a simple differential current steering circuit; finally, the load resistors were also used to sense the output common-mode level. The VGA was fabricated in 0.15 um standard CMOS process. Measurement results show the gain varying between 5 dB to 30 dB and the max bandwidth surpasses 60 MHz; 11.14 nV/root Hz input referred noise; O1dBCP of 8.6 dBm while taking 4.2 mA from a 1.8 V supply; it settles within 20 ns after a min-max step-change of the gain; it occupies 0.05 mm(2).

  • 35.
    Razzaghpour, Milad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Highly-Accurate Low-Power CMOS Potentiostat for Implantable BioSensors2011In: Biomedical Circuits and Systems Conference (BioCAS), 2011 IEEE, 2011, p. 5-8Conference paper (Refereed)
    Abstract [en]

    Current-mirror-based potentiostats suffer from sys-tematic and random errors causing offset, gain and linearityerror in reading out the sensor data. In this work, a newpotentiostat topology is proposed to eliminate the systematicerror via an error-cancellation loop. The loop takes advantageof an error-tracking amplifier connected to a transimpedanceamplifier with adjustable input common-mode voltage. Due tothe enhanced loop gain, the potentiostat is able to accuratelycopy the sensor current which will then be converted into theproportional voltage. Additionally, a theoretical discussion ofthe proposed topology is given and a thorough study on theeffect of random error sources is carried out. The potentiostat isdesigned and simulated in a 150nm CMOS process. The resultsverify a highly-linear highly-accurate performance in a low-noisecondition, while consuming only 32 μW.

  • 36.
    Rodriguez Duenas, Saul Alejandro
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Multi-Band Multi-Standard CMOS Receiver Front-Ends for 4G Mobile Applications2009Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The development of the transistor and its continuous down-scaling has allowed during the last decades the appearance of cheap wireless communication systems targeting consumer products. The complexity of these systems has increased dramatically during the last years, mainly fueled by both the Moore law and improvements in communication theory. Originally, the radio transceivers were composed of only a few transistors, and supported simple analog modulation schemes. Currently, radio transceivers are composed of thousands of transistors including not only radio/analog blocks but also a huge amount of digital circuitry as well. These radios use advanced digital modulation schemes, channel coding, and multiple access schemes.

    Despite the fact that digital circuits currently offer an impressive performance, pure digital signal processing of radio signals remains limited for relatively low frequencies below a few hundred MHz. On the other hand, frequency bands used in current mobile applications span from around 800MHz up to 6 GHz and hence demand the use of analog circuits to down-convert the radio signals to lower frequencies that are suitable for digital processing. The group of circuits that form this part of the receiver is known as the radio receiver front-end.

    The design of modern radio receiver front-ends has many challenges. One requirement is support of a multitude of standards with bands that are scattered all along the mobile radio spectrum. Accordingly, the noise and linearity specifications for these front-ends are very stringent. Also, these specifications have to be accomplished using low-power, low-cost, highly integrated circuit solutions.

    This thesis presents the design of multi-band multi-standard receiver front-ends for fourth generation mobile communications. A novel methodology that speeds up the development of multi-band multi-standard RF blocks by automating some steps in the design is shown. Examples of submicron and nanometer CMOS wideband receiver front-ends targeting 4G mobile applications are presented. New techniques for inductorless wideband front-ends using current-mode technology are presented. Finally, novel RF calibration techniques to cope with process, voltage, and temperature variations in modern CMOS processes are demonstrated.

  • 37.
    Rodriguez Duenas, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Duo, Xinzhong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Yamac, Sezi
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    CMOS UWB IR Non-Coherent Receiver for RF-ID Applications2006In: Circuits and Systems, 2006 IEEE North-East Workshop on, 2006, p. 213-216Conference paper (Refereed)
    Abstract [en]

    Ultra Wide Band Impulse-Radio (UWB-IR) bringsthe opportunity of increased bitrates in RFID systems. This paperpresents the implementation of a CMOS non-coherent UWBimpulse receiver targeted for readers in RFID applications. Thereceiver consists of an RF-front-end and an On-Off keying (OOK)10Mbps demodulator, which is implemented using a 0.18umCMOS process. The receiver works for 3.1GHz-5GHz, has asensitivity of -70dBm, and consumes 31mW from a 1.8V supply.

  • 38.
    Rodriguez, S.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ollmar, S.
    Waqar, M.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, A.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Batteryless Sensor ASIC for Implantable Bio-Impedance Applications2015In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990Article in journal (Refereed)
    Abstract [en]

    The measurement of the biological tissue’s electrical impedance is an active research field that has attracted a lot of attention during the last decades. Bio-impedances are closely related to a large variety of physiological conditions; therefore, they are useful for diagnosis and monitoring in many medical applications. Measuring living tissues, however, is a challenging task that poses countless technical and practical problems, in particular if the tissues need to be measured under the skin. This paper presents a bio-impedance sensor ASIC targeting a battery-free, miniature size, implantable device, which performs accurate 4-point complex impedance extraction in the frequency range from 2 kHz to 2 MHz. The ASIC is fabricated in 150 nm CMOS, has a size of 1.22 mm × 1.22 mm and consumes 165 μA from a 1.8 V power supply. The ASIC is embedded in a prototype which communicates with, and is powered by an external reader device through inductive coupling. The prototype is validated by measuring the impedances of different combinations of discrete components, measuring the electrochemical impedance of physiological solution, and performing ex vivo measurements on animal organs. The proposed ASIC is able to extract complex impedances with around 1 Ω resolution; therefore enabling accurate wireless tissue measurements.

  • 39.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Atallah, Jad G.
    Notre Dame University, Lebanon.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 2.3-GHz to 5.8-GHz CMOS receiver front-end for WiMAX/WLAN2010In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, 2010, p. 1068-1071Conference paper (Refereed)
    Abstract [en]

    This paper presents a wideband, direct-conversion radio receiver front-end that targets all WiMAX/WLAN bands from 2.3-GHz to 5.8-GHz. The receiver front-end is fabricated in 0.18-μm CMOS and achieves a gain of 25 dB, noise figure of 6 dB, and IIP3 of -6 dBm while dissipating 28 mW from a 1.8-V power supply. This performance is achieved while using only two integrated inductors.

  • 40.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: an automated RF-IC Rx front-end circuit design tool2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 255-270Article in journal (Refereed)
    Abstract [en]

    This paper presents a tool capable of automatically compiling the circuit of a direct-conversion receiver at the schematics level based on system specifications that include the frequency of operation, gain, noise figure, IIP2 and IIP3 linearity. The front-end of a direct-conversion receiver is built using inductive source degeneration (LSD) LNA and double-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that automatically size the transistors, passive components, and find the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout. Case studies involving WiMAX, UMTS, GSM, Bluetooth and WLAN are presented to reveal the capabilities of the tool in reducing the design time.

  • 41.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: An automated RF-IC Rx front-end circuit design tool2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 129-132Conference paper (Refereed)
    Abstract [en]

    This paper presents a tool capable of compiling automatically the schematic circuit design of a direct conversion receiver based on system specifications including frequency of operation, gain, noise figured and 123 linearity. The rx front-end of a direct conversion receiver is built using inductive source degeneration (LSD) LNA and single-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that size automatically the transistors, passive components, and finds the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout.

  • 42.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 6.4mW, 1-3.5GHz current-mode receiver front-end with noise cancellation2011In: ESSCIRC (ESSCIRC), 2011 Proceedings of the, 2011, p. 235-238Conference paper (Refereed)
    Abstract [en]

    A wideband receiver front-end which uses current-mode and noise cancellation techniques is presented. It is shown that the output impedance of the employed transconductance LNA can be very detrimental for the noise performance. The impact of the output impedance is quantified and considered in the design of a test circuit. An ESD protected prototype is fabricated in 150nm CMOS. Measurement results show a gain of 37dB, NF of 4dB and IIP3>-15dBm over a bandwidth of 1GHz-3.5GHz. The front-end consumes only 3.55mA from a 1.8V supply and its active area occupies 0.06mm2.

  • 43.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 65nm CMOS current-mode receiver front-end2011In: Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 2011, p. 530-533Conference paper (Refereed)
    Abstract [en]

    This paper briefly analyses the noise, bandwidth andlinearity performance advantage of nanometer CMOS currentmodecircuits compared to their voltage-mode counterparts andproposes a new current-mode receiver front-end targeting lowpowerwideband wireless applications. The proposed 65nmCMOS current-mode receiver front-end comprises a currentmodeLNA, and passive mixers, and covers all WiMAX/LTEbands from 700MHz to 5.8GHz. The front-end achieves an IIP3of 5 dBm, NF of 3.7-5dB while consuming 2.8mW from a 0.9Vpower supply. The analysis and simulation results show that thecurrent-mode techniques are very good candidates for wirelessapplications in low-voltage nanometer CMOS technologies.

  • 44.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    De la Rosa, Jose Maria
    Institute de Microelectronica de Sevilla IMSE-CNM.
    Overview of Carbon-Based Circuits and Systems2015In: Overview of Carbon-Based Circuits and Systems, IEEE , 2015, p. 2912-2915Conference paper (Refereed)
    Abstract [en]

    This paper presents an overview of the state of the art on carbon-based circuits and systems made up of carbon nanotubes and graphene transistors. A tutorial description of the most important devices and their potential benefits and limitations is given, trying to identify their suitability to implement analog and digital circuits and systems. Main electrical models reported so far for the design of carbon-based field-effect devices are surveyed, and the main sizing parameters required to implement such devices in practical integrated circuits are analyzed. The solutions proposed by cutting-edge integrated circuits and devices are discussed, identifying current trends, challenges and opportunities for the circuits and systems community1.

  • 45.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    4G CMOS Nanometer Receivers for Mobile Systems: Challenges and Solutions2009In: ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS,, NEW YORK: IEEE , 2009, p. 73-76Conference paper (Refereed)
    Abstract [en]

    This paper presents the design challenges and solutions for 4G nanometer radio receivers for mobile devices. The specifications for the ZERO-IF/LOW-IF 4G receiver architecture are derived. Limitations due to the use of low-voltage nanometer technologies are described and novel circuit techniques, such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are proposed. Finally, a 1.2-V 90nm CMOS receiver front-end for the proposed WiMAX/LTE receiver is designed employing novel circuit techniques. The front-end covers 700 MHz - 6 GHz, providing a total gain of 34 dB, noise figure of 4 dB, flicker noise corner of 10 kHz, and a third order intercept point of -10dBm/0dBm, while consuming a total power of 10.2 mW.

  • 46.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    WiMAX/LTE Receiver Front-End in 90nm CMOS2009In: ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, NEW YORK: IEEE , 2009, p. 1036-1039Conference paper (Refereed)
    Abstract [en]

    RFIC design using low-voltage nanometer CMOS technologies offers both advantages and challenges. This paper describes the limitations of using these technologies in receiver front-end design and proposes circuit solutions. Several techniques such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are reviewed and employed. A receiver front-end that covers 700MHz-6Ghz and supports the WiMAX/LTE standards is designed based on these circuit solutions. The front-end is designed using 1.2V 90nm CMOS and consumes a total power of 10.2mW. The total gain is 32dB, noise figure is 4dB, flicker noise corner is 10kHz, and third order intercept point is -10dBm/0dBm.

  • 47.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zheng, LiRong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A Novel BiST and Calibration Technique for CMOS Down-Converters2008In: Circuits and Systems for Communications, 2008. ICCSC 2008. 4th IEEE International Conference on, 2008, p. 828-832Conference paper (Refereed)
    Abstract [en]

    This paper presents a new digital calibration methodology that allows CMOS Gilbert cell down-converters to meet their block specifications under large process, temperature and power supply variations. The calibration method consists of a novel built-in self test for direct conversion receivers that is able to measure the gain, and the second and third order intermodulation products of the mixer. A random optimizer algorithm based on a least square error function provides digital control of the biasing circuit and the loads of the mixer. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is validated by calibrating a 0.18um CMOS mixer in several corner conditions.

  • 48.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    CMOS RF mixer with digitally enhanced IIP22008In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 44, no 2, p. 121-123Article in journal (Refereed)
    Abstract [en]

    A new method to enhance the IIP2 of a double-balanced Gilbert cell mixer through digital calibration is presented. The IIP2 calibration method consists of offset voltage cancellation in the switching pairs. The effectiveness of the method has been proven by calibrating a 0.18 mu m CMOS mixer at several combinations of worst-case mismatch conditions and corners. It has been found that the calibrated mixer can achieve its targeted IIP2 specification even at large process, temperature, and power supply variations.

  • 49.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Digital calibration of gain and linearity in a CMOS RF mixer2008In: Proceedings - IEEE International Symposium on Circuits and Systems, 2008, p. 1288-1291Conference paper (Refereed)
    Abstract [en]

    This paper presents a new digital calibration technique that allows CMOS Gilbert cell down-conversion mixers to meet their block specifications under large process, temperature and power supply variations. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is tested by calibrating a 0.18um CMOS mixer in several corner conditions. It is found that by using this calibration technique, the Gilbert cell mixer can achieve yields comparable to digital circuits, hence making it amenable to AMS SoC integration.

  • 50.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    Rusu, Ana
    Static Nonlinearity in Graphene Field Effect Transistors2014In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 61, no 8, p. 3001-3003Article in journal (Refereed)
    Abstract [en]

    The static linearity performance metrics of the graphene-based field effect transistor (GFET) transconductor are studied and modeled. Closed expressions are proposed for second-and third-order harmonic distortion (HD2, HD3), second-and third-order intermodulation distortion (Delta IM2, Delta IM3), and second-and third-order intercept points (A(IIP2), A(IIP3)). The expressions are validated through large-signal simulations using a GFET VerilogA analytical model and a commercial circuit simulator. The proposed expressions can be used during circuit design to predict the GFET biasing conditions at which linearity requirements are met.

12 1 - 50 of 75
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