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  • 1. Guang, Liang
    et al.
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hierarchical Agent Monitored System: An Innovative Paradigm for Parallel Computing2009In: ACACES 2009 (International Summer School of Advanced Computer Architecture and Compilation for Embedded Systems), 2009, p. 59-62Conference paper (Refereed)
  • 2. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Isoaho, Jouni
    Rantala, Pekka
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Interconnection alternatives for hierarchical monitoring communication in parallel SoCs2010In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 34, no 5, p. 118-128Article in journal (Refereed)
    Abstract [en]

    Interconnection architectures for hierarchical monitoring communication in parallel System-on-Chip (SoC) platforms are explored. Hierarchical agent monitoring design paradigm is an efficient and scalable approach for the design of parallel embedded systems. Between distributed agents on different levels, monitoring communication is required to exchange information, which forms a prioritized traffic class over data traffic. The paper explains the common monitoring operations in SoCs, and categorizes them into different types of functionality and various granularities. Requirements for on-chip interconnections to support the monitoring communication are outlined. Baseline architecture with best-effort service, time division multiple access (TDMA) and two types of physically separate interconnections are discussed and compared, both theoretically and quantitatively on a Network-on-Chip (NoC)-based platform. The simulation uses power estimation of 65 nm technology and NoC microbenchmarks as traffic traces. The evaluation points out the benefits and issues of each interconnection alternative. In particular, hierarchical monitoring networks are the most suitable alternative, which decouple the monitoring communication from data traffic, provide the highest energy efficiency with simple switching, and enable flexible reconfiguration to tradeoff power and performance.

  • 3. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Rantala, Pekka
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip2010In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 9, no 3, p. 25-Article in journal (Refereed)
    Abstract [en]

    Hierarchical agent framework is proposed to construct a monitoring layer towards self-aware parallel systems-on-chip (SoCs). With monitoring services as a new design dimension, systems are capable of observing and reconfiguring themselves dynamically at all levels of granularity, based on application requirements and platform conditions. Agents with hierarchical priorities work adaptively and cooperatively to maintain and improve system performance in the presence of variations and faults. Function partitioning of agents and hierarchical monitoring operations on parallel SoCs are analyzed. Applying the design approach on the Network-on-Chip (NoC) platform demonstrates the design process and benefits using the novel approach.

  • 4.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Plosila, J.
    Isoaho, Jouni
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    HAMSoC: A Monitoring-Centric Design Approach for Adaptive Parallel Computing2011In: Autonomic Networking-on-Chip: Bio-inspired Specification, Development and Verification / [ed] Phan Cong-Vinh, Taylor & Francis, 2011, p. 135-164Chapter in book (Other academic)
  • 5. Guang, Liang
    et al.
    Plosila, J.
    Isoaho, Jouni
    Tenhunen, Hannu
    University of Turku, Finland.
    Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification2010In: International Journal of Embedded and Real-Time Communication Systems (IJERTCS), ISSN 1947-3176, Vol. 1, no 2, p. 86-105Article in journal (Refereed)
    Abstract [en]

    In this paper, the authors present a formal specification of a novel design paradigm, hierarchical agent monitored SoCs (HAMSOC). The paradigm motivates dynamic monitoring in a hierarchical and distributed manner, with adaptive agents embedded for local and global operations. Formal methods are of essential importance to the development of such a novel and complex platform. As the initial effort, functional specification is indispensable to the non-ambiguous system modeling before potential property verification. The formal specification defines the manner by which the system can be constructed with hierarchical components and the representation of run-time information in modeling entities and every type of the monitoring operations. The syntax follows the standard set theory with additional glossary and notations introduced to facilitate practical SoC design process. A case study of hierarchical monitoring for power management in NoC (Network-on-chip), written with the formal specification, is demonstrated

  • 6.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Plosila, J.
    Isoaho, Jouni
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    Hierarchical Agent Monitoring Services on Reconfigurable NoC Platform: A Formal Approach2009In: Workshop Digest of DSNOC 09 (Diagnostic Services in Network-on-Chips), 2009, p. 98-101Conference paper (Refereed)
  • 7. Guang, Liang
    et al.
    Rantala, P.
    Nigussie, Ethiopia
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Low-latency and Energy-efficient Monitoring Interconnect for Hierarchical-agent-monitored NoCs2008In: Norchip - 26th Norchip Conference, Formal Proceedings, 2008, p. 227-232Conference paper (Refereed)
    Abstract [en]

    This paper presents quantitative analysis of monitoring interconnect architecture alternatives in hierarchical agent-based NoC platform. Hierarchical monitoring design methodology provides scalable dynamic management services with agents monitoring different levels. To enable low-latency and lowenergy agent communication, we examined three interconnect alternatives: TDM-based virtual channeling, unified dedicated monitoring network, and separate dedicated monitoring networks. With Orion and Cadence simulators, we estimated the energy and latency of monitoring communications on the three architectures for an 8*8 mesh network in 65nm technology. The results suggest that separate dedicate links mostly minimize the communication delay and energy consumption (66.7% and 82.1% respectively compared to TDM-based interconnect), while incurring moderate area penalty.

  • 8. Guang, Liang
    et al.
    Yang, B.
    Plosila, J.
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hierarchical Agent Monitoring Design Platform - towards Self-aware and Adaptive Embedded Systems2011In: PECCS 2011 - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems, 2011, p. 573-581Conference paper (Refereed)
    Abstract [en]

    Hierarchical agent monitoring design platform(HAM) is presented as a generic design approach for the emerging self-aware and adaptive embedded systems. Such systems, with various existing proposals for different advanced features, call for a concrete, practical and portable design approach. HAM addresses this necessity by providing a scalable and generically applicable design platform. This paper elaborately describes the hierarchical agent monitoring architecture, with extensive reference to the state-of-the-art technology in embedded systems. Two case studies are exemplified to demonstrate the design process and benefits of HAM design platform. One is about hierarchical agent monitored Network-on-Chip with quantitative experiments of hierarchical energy management. The other one is a projectional study of applying HAM on smart house systems, focusing on the design for enhanced dependability.

  • 9.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Yin, A.
    Rantala, P.
    Nigussie, Ethiopia
    Department of Information Technology, University of Turku, Finland.
    Liljeberg, P.
    Isoaho, Jouni
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    Hierarchical Power Monitoring for On-chip Networks2009In: Proceedings of Work in Progress Session in Euromicro PDP 2009 Conference, 2009Conference paper (Refereed)
  • 10.
    Tenhunen, Hannu
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Virtanen, S.
    Isoaho, Jouni
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Salakoski, Tapio
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Information Security Education in Knowledge Triangle2009Conference paper (Other academic)
  • 11. Tuuna, S.
    et al.
    Nigussie, E.
    Isoaho, Jouni
    Department of Information Technology, University of Turku.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Analysis of delay variation in encoded on-chip bus signaling under process variation2008In: 21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, p. 228-234Conference paper (Refereed)
    Abstract [en]

    In this paper we model on-chip signaling over a bus consisting of encoding, drivers, transmission lines, receivers and decoding. We characterize the signaling circuitry as a function of its load capacitance. The effective load capacitance seen by a driver is derived for the decoupling method and distributed RLC transmission line models. The driver delay and rise time corresponding to the derived effective capacitance are used to derive the far-end voltage of a transmission line bus. The effects of process variation are taken into account in the characterization of the signaling circuitry and in the wire analysis. The overall delay variation of the bus due to device and wire process variation is then calculated. The model is verified by comparing it to HSPICE. We implement regular voltage mode, level-encoded dual-rail and 1-of-4 signaling circuitry and apply the derived model to analyze them. The implementation and analysis are done in 45 nm technology.

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