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  • 1.
    Li, Jiantong
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhibin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Contact-electrode insensitive rectifiers based on carbon nanotube network transistors2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, p. 500-502Article in journal (Refereed)
    Abstract [en]

    This letter presents rectifiers based on the diode connection of carbon nanotube network (CNN) transistors. Despite a low density of carbon nanotubes in the CNNs, the devices can achieve excellent performance with a forward/reverse current ratio reaching 10(5). By casting nanotube suspension on oxidized Si substrates with predefined electrodes, CNN-based field-effect transistors are readily prepared. By short-circuiting the source and gate terminals, CNN-based rectifiers are realized with the rectification characteristics independent of whether Pd or Al is employed as the contact electrodes. This independence is especially attractive for applications of CNN-based transistors/rectifiers in flexible electronics with various printing techniques.

  • 2.
    Liu, Zhiying
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Qiu, Zhijun
    Zhang, Z B
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, S L
    Mobility Extraction for Nanotube TFTs2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 7, p. 913-915Article in journal (Refereed)
    Abstract [en]

    An extensive investigation of carrier mobility is presented for thin-film transistors (TFTs) with single-walled carbon nanotube (SWCNT) networks as the semiconductor channel. For TFTs particularly with low-density SWCNTs in the networks, the extracted mobility using the standard method for Si metal-oxide-semiconductor field-effect transistors is erroneous, mainly resulting from use of a parallel-plate capacitor model and assumption of the source-drain current being inversely proportional to the channel length. Large hysteresis in the transfer characteristics further complicates the extraction. By properly addressing all these challenges in this letter, a comprehensive methodology is established, leading to the extraction of mobility values that are independent of geometrical parameters.

  • 3.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Qiu, Zhi-Jun
    Zhang, David Wei
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    Effects of Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 6, p. 608-610Article in journal (Refereed)
    Abstract [en]

    The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased phi(bn) from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600 degrees C. Above this temperature, B-DS at this interface is evident thus keeping phi(bn) high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning phi(bn) above 1.0 eV by As-DS.

  • 4.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interaction of NiSi with dopants for metallic source/drain applications2010In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 28, no 1, p. C1I1-C1I11Article in journal (Refereed)
    Abstract [en]

    This work has a focus on NiSi as a possible metallic contact for aggressively scaled complementary metal oxide semiconductor devices. As the bulk work function of NiSi lies close to the middle of Si bandgap, the Schottky barrier height (SBH) of NiSi is rather large for both electron (similar to 0.65 eV) and hole (similar to 0.45 eV). Different approaches have therefore been intensively investigated in the literature aiming at reducing the effective SBH: dopant segregation (DS), surface passivation (SP), and alloying, in order to improve the carrier injection into the conduction channel of a field-effect transistor. The present work explores DS using B and As for the NiSi/Si contact system. The effects of C and N implantation into Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. A combined use of DS or SP with alloying could be considered for more effective control of effective SBH, but an examination of undesired compound formation and its probable consequences is necessary. Furthermore, an analysis of the metal silicides that have a small "intrinsic" SBH reveals that only a very small number of them are of practical interest as most of the silicides require either a high formation temperature or possess a high specific resistivity.

  • 5.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Dongping
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Qiu, Zhijun
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Lu, Jun
    Department of Physics, Chemistry and Biology, Linköping University.
    Hultman, Lars
    Department of Physics, Chemistry and Biology, Linköping University.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    On Different Process Schemes for MOSFETs With a Controllable NiSi-Based Metallic Source/Drain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 1898-1906Article in journal (Refereed)
    Abstract [en]

    This paper focuses on different silicidation schemes toward a controllable NiSi-based metallic source/drain (MSD) process with restricted lateral encroachment of NiSi. These schemes include thickness control of Ni, Ni-Pt alloying, and two-step annealing. Experimental results show that all the three process schemes can give rise to effective control of lateral encroachment during Ni silicidation. By controlling t(Ni), NiSi-based MSD metal-oxide-semiconductor field-effect transistors (MOSFETs) of gate length L-G = 55 nm are readily realized on ultrathin-body silicon-on-insulator substrates with 20-nm surface Si thickness. With the aid of dopant segregation (DS) to modifying the Schottky barrier heights of NiSi, both n- and p-type MSD MOSFETs show significant performance improvement, compared to reference devices without DS.

  • 6.
    Qiu, Zhijun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 1, p. 396-403Article in journal (Refereed)
    Abstract [en]

    An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SUDS is relatively simple in processing, but the silicidation process is dopant-dependent, leading to local variations of silicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation.

  • 7.
    Qiu, Zhijun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zuhua
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, J.
    Liu, R.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Lin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicide as diffusion source for dopant segregation in 70-nm MOSFETs with PtSi Schottky-barrier source/drain on ultrathin-body SOI2008In: ULIS 2008: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON / [ed] Esseni, D; Palestri, P; Selmi, L, NEW YORK: IEEE , 2008, p. 23-26Conference paper (Refereed)
    Abstract [en]

    In this paper, dopant segregation (DS) method is adopted to enhance device performance of PtSi-based Schottky-barrier source/drain MOSFETs (SB-MOSFETs) fabricated on ultrathin silicon-on-insulator. The DS formation is realized by means of Silicide As Diffusion Source. Without DS treatment, the devices are typically p-type, but with a rather large electron branch at positive gate bias. Dopant segregation with As is found to turn the devices to well-performing n-MOSFETs, and DS with B to greatly enhance the hole conduction in the p-MOSFETs. A large threshold voltage (V-t) shift is however observed in the p-MOSFET due to B lateral spread caused during the drive-in process for the DS formation. By reducing the drive-in temperature, this problem is partially addressed with a smaller V-t shift and a much better control of short channel effect.

  • 8.
    Qiu, Zhijun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zuhua
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Olsson, J.
    Lu, J.
    Hellström, Per Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Liu, R.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, ShiLin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Role of Si implantation in control of underlap length in Schottky-barrier source/drain MOSFETs on ultrathin body SOI2008In: ULIS 2008: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON / [ed] Esseni, D; Palestri, P; Selmi, L, NEW YORK: IEEE , 2008, p. 175-178Conference paper (Refereed)
    Abstract [en]

    This works demonstrates a novel approach using Si implantation prior to Pt deposition and PtSi formation to control the underlap length between the PtSi source/drain regions to the gate in Schottky-Barrier (SB-) MOSFETs. Dopant segregation at the PtSi/Si interface is used to enhance device performance. With the I-on/I-off current ratio as an indicator, optimized Si implant doses are found for both n- and p-channel SB-MOSFETs. Through an effective barrier width, the underlap length has direct implication on the leakage current.

  • 9.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Performance fluctuation of FinFETs with Schottky barrier source/drain2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, p. 506-508Article in journal (Refereed)
    Abstract [en]

    A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.

  • 10.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Olsson, Jörgen
    The Ångström Laboratory, Uppsala University.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 1, p. 125-127Article in journal (Refereed)
    Abstract [en]

    MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.

  • 11.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Liu, Ran
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schottky-barrier height tuning by means of ion implantation into preformed silicide films followed by drive-in anneal2007In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 7, p. 565-568Article in journal (Refereed)
    Abstract [en]

    An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to similar to 1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV The process window for the most pronounced SBH modification is dopant dependent.

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