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  • 1.
    Färm, Petra
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Advanced algorithms for logic synthesis2004Licentiatavhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observations: (1)Traditional logic synthesis applies literal count as theprimary quality metric during the technology independentoptimization phase. Thissimplistic metric often leads to badcircuit structures as it cannot foresee the impact of earlychoices on the final area, delay, power consumption, etc. (2)Although powerful, global Boolean optimization is not robustand corresponding algorithms cannot be used in practice withoutartificially restricting the application window. Othertechniques, such as algebraic methods scale well but provideweaker optimization power.

    In our most recent work, both problems are addressed byapplying a simulated annealing approach that is based on asimple circuit graph representation and a complete set of localtransformations, including algebraic and Boolean optimizationsteps. The objective of the annealing process can be tuned tocomplex cost functions, combining area, timing, routability,and power. Our experimental results on benchmark functionsdemonstrate the significant potential of the simulatedannealing approach.

    Earlier work includes a fast rule-based system fortechnology independent optimization. A Boolean network isoptimized by applying local structural transformations thatpreserve its functionality. NPN classes of Boolean functionsare used to identify replacement rules for localtransformations. It provides fast and roboust optimization, butuses a simplistic objective.

    Decomposition is one of the important steps of logicsynthesis. It can be applied during the technology independentoptimization phase as well as during the technology mapping. Wehave extended a conjunctive decomposition of Boolean functions[1]to multiple-valued input binary-valued output functions.Our extension provides a more efficient way for decomposingmutiple-output Boolean functions, since [1]only considerssingle-output functions.

    Furthermore, we address the problems of technology mappingand logic optimization for Chemically Assembled ElectronicNanotechnoloy (CAEN).CAEN is a promising alternative toCMOS-based technology, allowing construction of extremeleydense low-power computational elements with inexpensivechemical self-assembly.

  • 2.
    Färm, Petra
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Integrated Logic Synthesis Using Simulated Annealing2007Doktoravhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    A conventional logic synthesis flow is composed of three separate phases: technologyindependent optimization, technology mapping, and technology dependentoptimization. A fundamental problem with such a three-phased approach is thatthe global logic structure is decided during the first phase without any knowledge ofthe actual technology parameters considered during later phases. Although technologydependent optimization algorithms perform some limited logic restructuring,they cannot recover from fundamental mistakes made during the first phase, whichoften results in non-satisfiable solutions.We present a global optimization approach combining technology independentoptimization steps with technology dependent objectives in an annealing-basedframework. We prove that, for the presented move set and selection distribution, detailedbalance is satisfied and thus the annealing process asymptotically convergesto an optimal solution. Furthermore, we show that the presented approach cansmoothly trade-off complex, multiple-dimensional objective functions and achievecompetitive results. The combination of technology independent and technologydependent objectives is handled through dynamic weighting. Dynamic weightingreflects the sensitivity of the local graph structures with respect to the actual technologyparameters such as gate sizes, delays, and power levels. The results showthat, on average, the presented advanced annealing approach can improve the areaand delay of circuits optimized using the Boolean optimization technique providedby SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework canbe applied to two emerging technologies, chemically assembled nanotechnology andmolecule cascades. New technologies are emerging because a number of physicaland economic factors threaten the continued scaling of CMOS devices. Alternativesto silicon VLSI have been proposed, including techniques based on molecularelectronics, quantum mechanics, and biological processes. We are hoping that ourresearch in how to apply our developed logic synthesis framework to two of theemerging technologies might provide useful information for other designers movingin this direction.

  • 3.
    Färm, Petra
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Dubrova, Elena
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Kuehlmann, Andreas
    Cadence Berkeley Labs, Berkeley, CA 94704, United States .
    Integrated logic synthesis using simulated annealing2011Inngår i: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2011, s. 407-410Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Conventional logic synthesis flows are composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions. In this paper, we present a method for integrating the three synthesis phases using an annealing algorithm as optimization framework. The annealing-based search is driven by a complex objective function, combining both technology independent as well as technology dependent optimization criteria. Our experimental results shown that, on average, the presented approach can improve the area and delay of circuits optimized with script rugged of SIS by 11.2% and 32.5% respectively.

  • 4.
    Färm, Petra
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Dubrova, Elena
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Kuehlmann, Andreas
    Logic optimization using rule-based randomized search2005Inngår i: ASP-DAC 2005: Proceedings Of The Asia And South Pacific Design Automation Conference, IEEE , 2005, s. 998-1001Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper we describe a new logic synthesis approach based on rule-based randomized search using simulated annealing. Our work is motivated by two observations: (1) Traditional logic synthesis applies literal count as the primary quality metric during the technology independent optimization phase. This simplistic metric often leads to poor circuit structures as it cannot foresee the impact of early choices on the final area, delay, power consumption, etc. (2) Although powerful, global Boolean optimization is not robust and corresponding algorithms cannot be used in practice without artificially restricting the application window. Other techniques, such as algebraic methods scale well but provide weaker optimization power To address both problems, we use randomized search that is based on a simple circuit graph representation and a complete set of local transformations that include algebraic and Boolean optimization steps. The objective of the search process can be tuned to complex cost functions, combining area, timing, routability, and power Our experimental results on benchmark functions demonstrate the significant potential of the presented approach.

  • 5.
    Färm, Petra
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Dubrova, Elena
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Logic optimization technique for molecular cascades2005Inngår i: Nanotechnology II / [ed] Lugli, P; Kish, LB; Mateos, J, SPIE - International Society for Optical Engineering, 2005, Vol. 5838, s. 95-104Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Molecular cascades introduced in(1) provide new ways to exploit the motion of individual molecules in nanometer-scale structures. Computation is performed by purely mechanical means similarly to the toppling of a row of standing domino. A specific feature of molecular cascades is that an inverter cannot be build, because it would require that all molecules in the inverter's output untopple when the input cascade topples. This is not possible because an untoppled state has higher energy than a toppled one. As a solution, we propose to avoid the need for inverters by representing signals by the dual-rail convention. As a basic building block we use a molecular block, which has four inputs x(1),...,x(4) such that x(3) = x(1)', x(4) = x(2)', and two outputs f(1) = x(1) . x(2) and f(2) = x(3) + x(4). If input variables are available in both complemented and non-complemented form, then any Boolean function can be implemented by a composition of such molecular blocks. We present an experimental tool which first uses a rule-based randomized search to optimize a Boolean network and then maps it into a network of interconnected molecular blocks.

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