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  • 1.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Dongping
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Qiu, Zhijun
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Lu, Jun
    Department of Physics, Chemistry and Biology, Linköping University.
    Hultman, Lars
    Department of Physics, Chemistry and Biology, Linköping University.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    On Different Process Schemes for MOSFETs With a Controllable NiSi-Based Metallic Source/Drain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 1898-1906Article in journal (Refereed)
    Abstract [en]

    This paper focuses on different silicidation schemes toward a controllable NiSi-based metallic source/drain (MSD) process with restricted lateral encroachment of NiSi. These schemes include thickness control of Ni, Ni-Pt alloying, and two-step annealing. Experimental results show that all the three process schemes can give rise to effective control of lateral encroachment during Ni silicidation. By controlling t(Ni), NiSi-based MSD metal-oxide-semiconductor field-effect transistors (MOSFETs) of gate length L-G = 55 nm are readily realized on ultrathin-body silicon-on-insulator substrates with 20-nm surface Si thickness. With the aid of dopant segregation (DS) to modifying the Schottky barrier heights of NiSi, both n- and p-type MSD MOSFETs show significant performance improvement, compared to reference devices without DS.

  • 2.
    Persson, Stefan
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Wu, Dongping
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Lindgren, Ann Chatrin
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Variation of contact resistivity with Ge in TiW/p(+) SiGe contacts2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 49-52Article in journal (Refereed)
    Abstract [en]

    The dependence of contact resistivity on the Ge content in Si1-xGex is examined for TiW/p(+) Si1-xGex interfaces. Measurements are made on contacts with epitaxial Si1-xGex layers either at the surface or buried under a Si cap layer of various thicknesses. The contact resistivity is found to decrease by an order of magnitude with increasing Ge content from 0 to 30 at. %, which is attributed to an increase in the valence band energy of p(+) Si1-xGex. The measured contact resistivity is compared with a theoretical model, and the experimental results agree well with the modelled ones.

  • 3.
    von Haartman, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wu, Dongping
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Westlinder, J.
    Olsson, J.
    Low-frequency noise and Coulomb scattering in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics2005In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 49, no 6, p. 907-914Article in journal (Refereed)
    Abstract [en]

    Carrier mobility and low-frequency noise were investigated in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics. The devices were annealed in H2O Vapor, which reduced the negative charge in the gate dielectrics. The carrier mobility was characterized versus change in oxide charge, which allowed an estimation of the Coulomb scattering from the charge in the Al2O3. The low-frequency noise was measured between subthreshold and strong inversion conditions in the H2O annealed and the un-annealed devices. The combined number fluctuation and correlated mobility fluctuation noise model could successfully explain the observed 1/f noise. The mobility fluctuations were negatively correlated to the number fluctuations in the un-annealed devices, which contained a negative oxide charge. In the H2O annealed devices, on the other hand, a positive correlation could be observed. The maximum magnitude of the scattering parameter a was found to be around 1 X 10(4) Vs/C. The H2O annealing was used in this work as a non-destructive tool to modify the charge in the Al2O3, but it can also be a viable method to improve device performance by introducing/passivating charge.

  • 4.
    von Haartman, Martin
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Wu, Dongping
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with a metal/high-κ gate stack2003In: Proc. 17th Int. Conf.Noise and Fluctuations (ICNF),, 2003, p. 381-384Conference paper (Refereed)
  • 5.
    Wu, Dongping
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Novel concepts for advanced CMOS: Materials, process and device architecture2004Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.

    High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.

    A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.

    Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.

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  • 6.
    Wu, Dongping
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Lu, J.
    Persson, Stefan
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Hellström, Per Erik
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Vainonen-Ahlgren, E.
    Tois, E.
    Tuominen, M.
    Östling, Mikael
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Characterization of high-kappa nanolaminates of HfO2 and Al2O3 used as gate dielectrics in pMOSFETs2004In: Integration Of Advanced Micro-And Nanoelectronic Devices-Critical Issues And Solutions / [ed] Morais, J; Kumar, D; Houssa, M; Singh, RK; Landheer, D; Ramesh, R; Wallace, RM; Guha, S; Koinuma, H, 2004, Vol. 811, p. 19-24Conference paper (Refereed)
    Abstract [en]

    In order to combine the merits of both HfO2 and Al2O3 as high-kappa gate dielectrics for CMOS technology, high-kappa nanolaminate structures in the form of either Al2O3/HfO2/Al2O3 or Al2O3/HfAlOx/Al2O3 were implemented in pMOSFETs and electrically and microstructurally charachterized. ALD TiN film was used as the metal gate electrodes for the pMOSFETs. After full transistor-processing including a rapid thermal processing step at 930 T, the HfO2 film in the former nanolaminate was found to be crystallized. In contrast, the HfAlOx layer in the latter nanolaminate remained in the amorphous state. Both types of pMOSFETs exhibited a hysteresis as small as similar to20 mV in C-V characteristics in the bias range of +/- 2 V. They also showed a reduced gate leakage current. The pMOSFET with the Al2O3/HfAlOx/Al2O3 nanolaminate was characterized with a subthreshold slope of 77 mV/decade and a channel hole mobility close to the universal hole mobility curve. The pMOSFET with the Al2O3/HfO2/Al2O3, however, exhibited a subthreshold slope of 100 mV/decade and a similar to30W lower hole mobility than the universal curve.

  • 7.
    Wu, Donping
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Lu, J
    Radamson, Henry H.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Zhang, SL
    Östling, Mikael
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Vainonen-Ahlgren, E
    Tois, E
    Tuominen, M
    Influence of surface treatment prior to ALD high-kappa dielectrics on the performance of SiGe surface-channel pMOSFETs2004In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 25, no 5, p. 289-291Article in journal (Refereed)
    Abstract [en]

    Compressively strained Si0.7Ge0.3 surface-channel pMOSFETs with atomic layer deposition (ALD) Al2O3/HfO2/Al2O3 nanolaminate and low-pressure chemical vapor deposition p(+) poly-SiGe gate electrode were fabricated. Surface treatment with either hydrogen fluoride (HF) clean, or HF clean followed by water rinse was performed prior to the ALD processing. The devices with water rinse show a good control of interfacial layer and device reproducibility, while the devices without water rinse lack a clearly observable interfacial layer and show scattered electrical characteristics and distorted mobility curve. A similar to20% increase in hole mobility compared to the Si universal mobility and a similar to0.6-nm-thick continuous interfacial layer are obtained for the pMOSFETs with water rinse.

1 - 7 of 7
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