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  • 1.
    Minhass, Wajid Hassan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support2009In: 6th FPGAworld Conference, Academic Proceedings 2009, ACM , 2009, p. 52-57Conference paper (Refereed)
    Abstract [en]

    The Multi-Core NoC is a 4 by 4 Mesh NoC targeted for Altera FPGAs. It implements a deflective routing policy and is used to connect sixteen NIOS II processors. Each NIOS II is connected to the NoC via an address-mapped Resource Network Interface. The Multi-Core NoC is implemented on four separate Altera Stratix II FPGA boards, each hosting a Quad-Core NoC, which operates on a local 50 MHz clock. It has an onboard throughput of 650 Mbps (12.5 MFlit/s), and uses 28% of the LUs, 18% of the ALUTs, 22 % of the dedicated registers and 31% of the total memory blocks of a Stratix II FPGA. Asynchronous clock bridges, with a throughput of 50 Mbps (∼1MFlit/s), are used for the inter-board communication. Application programs use an MPI compatible Hardware Abstraction Layer (HAL) to communicate with the Resource Network Interface of the NoC. The RNI sets up message transfer, with a maximum length of 512 bytes, and sends flits with the size of 32 bit data plus 20 bit headers through the network. The MPI is the bottleneck of the system; it takes 46 us (43.4 kPackets/s) to send a minimum-sized packet through the protocol stack to a near neighbour and bounce it back to the original application. The bounce-back time for a far neighbour is 56 us.

  • 2.
    Minhass, Wajid Hassan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Implementation of a scalable, globally plesiochronous locally synchronous, off-chip NoC communication protocol2009In: 2009 NORCHIP, 2009, p. 1-5Conference paper (Refereed)
    Abstract [en]

    Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance the NoC-grid off-chip is needed. In this paper, we present such a method. As a proof of concept, the protocol is implemented on a 4 by 4 Mesh NoC, with NIOS II CPU cores as nodes, partitioned across four separate Altera FPGA boards, each board hosting a Quad-Core (2x2) NoC, operating on a local 50 MHz clock. The inter-chip communication protocol uses asynchronous clock bridges, with a throughput of 50 Mbps (~1MFlit/s) and is completely scalable. The NoC has an onboard throughput of 650 Mbps (12.5 MFlit/s). Each Quad-Core uses 28% of the LUs, 18% of the ALUTs, 22 % of the dedicated registers and 31% of the total memory blocks of the Stratix II FPGAs. Application programs use an MPI compatible Hardware Abstraction Layer (HAL) to communicate with each other over the NoC.

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