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  • 1.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 10, p. 2664-2670Article in journal (Refereed)
    Abstract [en]

    The influence of the emitter-base geometry on the current gain has been investigated by means of measurements and simulations. Particular attention has been placed on the emitter width and on the distance between the emitter edge and the base contact. When the emitter width is decreased from 40 to 8 mu m, the current gain is reduced by 20%, whereas when the distance between the base contact and the emitter edge is decreased from 5 to 2 mu m, the current gain is reduced by 10%. Simulations have been used to investigate the reasons for the current gain reduction. The reduction of the emitter width induces two mechanisms of current gain reduction: earlier forward biasing of the base-collector junction and higher recombination in the emitter region. Both mechanisms result from the higher current density flowing under the emitter region. Placing the base contact very close to the emitter edge increases the base current by increasing the gradient of the electron concentration toward the base contact. The effect of increasing the base doping in the extrinsic region has been simulated, and the results demonstrate that the current gain can be improved if a high doping concentration in the range of 5 x 10(18) cm(-3) is used.

  • 2.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 3, p. 704-711Article in journal (Refereed)
    Abstract [en]

    Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10(-15) cm(2), and a trap concentration of 2 x 10(12) cm(-2). Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base ( which has a doping concentration of 3 x 10(17) cm(-3)) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.

  • 3.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 2081-2087Article in journal (Refereed)
    Abstract [en]

    The ON-resistance of silicon carbide bipolar transistors is characterized and simulated. Output characteristics are compared at different base currents and different temperatures in order to validate the physical model parameters. A good agreement is obtained, and the key factors, which limit the improvement of R-ON, are identified. Surface recombination and material quality play an important role in improving device performances, but the device design is also crucial. Based on simulation results, a design that can enhance the conductivity modulation in the lowly doped drift region is proposed. By increasing the base doping in the extrinsic region, it is possible to meet the requirements of having low voltage drop, high current density, and satisfactory forced current gain. According to simulation results, if the doping is 5 x 10(18) cm(-3), it is possible to conduct 200 A/cm(2) at V-CE = 1 V by having a forced current gain of about 8, which represents a large improvement, compared with the simulated value of only one in the standard design.

  • 4.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I: Analytical Model of the MTJ STO2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1037-1044Article in journal (Refereed)
    Abstract [en]

    Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.

  • 5.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II: Verilog-A Model Implementation2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1045-1051Article in journal (Refereed)
    Abstract [en]

    The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.

  • 6. Corman, Thierry
    et al.
    Noren, K.
    Enoksson, Peter
    Melin, Jessica
    Stemme, Göran
    KTH, Superseded Departments, Signals, Sensors and Systems.
    Burst technology with feedback-loop control for capacitive detection and electrostatic excitation of resonant silicon sensors2000In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 47, no 11, p. 2228-2235Article in journal (Refereed)
    Abstract [en]

    A method for excitation and detection of resonant silicon sensors based on discontinuous, burst excitation is presented. The solution eliminates the crosstalk between electrostatic excitation and capacitive detection by separating them in time. High excitation voltages can be combined with highly sensitive detection electronics. The method facilitates the use of large distances between the resonator and electrodes used for elicitation and detection. The method was successfully tested with feedback-loop control on silicon resonant density and pressure sensors where the electrodes were positioned outside a glass, Continuous measurements of gas pressures and liquid densities were realized, The simplified fabrication process utilized reduces the risk of leakage from the ambient pressure to the low-pressure cavities in which the resonators are encapsulated since electrical feedthroughs are not needed, Excitation voltages alternating between 0 and 150 V could be applied to the resonators with measured electronics sensitivities of 0.4 fF Signal-to-noise ratios (SNRs) as high as 100 (density sensor) and 360 (pressure sensor) were obtained. The electronic evaluation revealed that the burst duty cycle (i.e,, the excitation time relative to the free oscillation time) had a strong influence on the output detection voltage, As few as two excitation periods with a burst cycle frequency of 115 Hz and a burst duty cycle of 1% was sufficient to select and lock the resonance frequency (28 042 Hz) for the tested pressure sensor. The same electrodes could be used for both excitation and detection, A novel solution is also presented that eliminates the charging effect of dielectric surfaces which otherwise can be a problem for capacitive detection.

  • 7. Danielsson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nikolaev, A.
    Nikitina, I. P.
    Dmitriev, V.
    Fabrication and characterization of heterojunction diodes with HVPE-Grown GaN on 4H-SiC2001In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 48, no 3, p. 444-449Article in journal (Refereed)
    Abstract [en]

    GaN/SiC heterojunctions can improve the performance considerably for BJTs and FETs. In this work, heterojunction diodes have been manufactured and characterized. The fabricated diodes have a GaN n-type cathode region on top of a JH-SIC p-type epi layer. The GaN layer was grown with HVPE directly on off-axis SiC without a buffer layer. Mesa structures were formed and a Ti metallization was used as cathode contact to GaN, and the anode contact was deposited on the backside using sputtered Al. Both current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed on the diode structures. The ideality factor of the measured diodes was 1.1 and was constant with temperature. A built in potential of 2.06 V was extracted from I-V-measurements and agrees well with the built in potential from C-V-measurements. The conduction band offset was extracted to 1.1 eV and the heterojunction was of type II. The turn on voltage for the diodes is about 1 V lower than expected and a suggested mechanism for this effect is discussed.

  • 8.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Thulium silicate interfacial layer for scalable high-k/metal gate stacks2013In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 10, p. 3271-3276Article in journal (Refereed)
    Abstract [en]

    Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.

  • 9.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Hillkirk, Leonardo
    KTH, Superseded Departments, Electronics.
    Linnros, Jan
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Dynamic avalanche in 3.3-kV Si power diodes1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 4, p. 781-786Article in journal (Refereed)
    Abstract [en]

    Measurements of the safe reverse recovery limit were performed for 3.3-kV Si power diodes using a novel optical experimental technique. In this experiment, influence of the junction termination is effectively eliminated by optical generation of a laterally-localized carrier plasma. The turn-off failures observed in measurements at two temperatures showed no temperature dependence and could not be reproduced in ordinary one-dimensional (1-D) or two-dimensional (2-D) device simulations. To simulate the stability of the current density toward current filamentation, two 1-D diodes with an area ratio 1:19 and a 10% difference in initial carrier plasma level, were simulated in parallel. This resulted in a strongly inhomogeneous current distribution, and a rapid reverse voltage fall resembling the measured turn-off failures. Inhomogeneous current distribution in these simulations appears as the current decay ceases due to impact ionization, in qualitative agreement with a current instability condition proposed by Wachutka [1].

  • 10.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Lutz, J.
    Silber, D.
    On the destruction limit of Si power diodes during reverse recovery with dynamic avalanche2003In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 50, no 2, p. 486-493Article in journal (Refereed)
    Abstract [en]

    The reverse recovery destruction limit of 3.3 kV fast recovery diodes was investigated by measurements and device simulations. Based on a good agreement between the measured destruction limit and current filamentation in simulations, it is proposed that the destruction is triggered by the onset of impact ionization at the nn(+) junction. The proposed destruction mode has large similarities with previously described second breakdown at the static breakdown voltage. An approximate analytical model which was derived indicate that avalanche at the nn(+) junction should become unstable with a time constant on the order of nanoseconds, whereas dynamic avalanche at the pn junction should be stable. Simulations and measurements give at hand that the reverse recovery safe operating area depends on the n-base width. An approximate equation is proposed to determine the minimum n-base width required for a nondestructive reverse recovery with dynamic avalanche as function of the reverse peak voltage.

  • 11. Duan, Ningyuan
    et al.
    Luo, Jun
    Wang, Guilei
    Liu, Jinbiao
    Simoen, Eddy
    Mao, Shujuan
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wang, Xiaolei
    Li, Junfeng
    Wang, Wenwu
    Zhao, Chao
    Ye, Tianchun
    Reduction of NiGe/n- and p-Ge Specific Contact Resistivity by Enhanced Dopant Segregation in the Presence of Carbon During Nickel Germanidation2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4546-4549Article in journal (Refereed)
    Abstract [en]

    This brief explores the specific contact resistivity (rho(c)) of NiGe/n- and p-Ge contacts with and without carbon pregermanidation implantation. It is found that in the presence of carbon, not only the thermal stability of NiGe films is improved, but also the rho(c) of the NiGe/n- and p-Ge contacts is reduced remarkably due to enhanced phosphorus (P) and boron (B) dopant segregation (DS) at the NiGe/Ge interface after nickel germanidation. At 500 degrees C germanidation temperature, the.c values are reduced from 1.1 x 10(-4) Omega-cm(2) and 2.9 x 10(-5) Omega-cm(2) for NiGe/n- and p-Ge contacts without carbon to 7.3 x 10(-5) Omega-cm(2) and 1.4 x 10(-5) Omega-cm(2) for their counterparts with carbon, respectively.

  • 12.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4366-4372Article in journal (Refereed)
    Abstract [en]

    A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H–SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.

  • 13.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, Romain
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schöner, Adolf
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Han, Jisheng
    Dimitrijev, Sima
    Reshanov, Sergey A.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Surface-passivation effects on the performance of 4H-SiC BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, p. 259-265Article in journal (Refereed)
    Abstract [en]

    In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

  • 14.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage (2.8 kV) Implantation-free 4H-SiC BJTs with Long-TermStability of the Current Gain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 8, p. 2665-2669Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC BJTs with high breakdown of 2800 V have been fabricated utilizing acontrolled two-step etched junction termination extension (JTE). The small area devices show a maximum dc current gainof 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4mΩ·cm2. The large area device have a maximum dc current gain of 52 at Ic = 9.36 A (JC=289 A/cm2) and VCESAT = 1.14 Vat Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ·cm2. Also these devices demonstrate a negative temperaturecoefficient of the current gain (β=26 at 200°C) and a positive temperature coefficient of the ON-resistance (RON = 10.2mΩ·cm2 at 200°C). The small area BJT shows no bipolar degradation and low current gain degradation after 150 Hrs stressof the base-emitter diode with current level of 0.2A (JE=500 A/cm2). Also, large area BJT shows a VCE fall time of 18 nsduring turn-on and a VCE rise time of 10 ns during turn-off for 400 V switching characteristics.

  • 15.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 6, p. 1585-1591Article in journal (Refereed)
    Abstract [en]

    The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (rho(c)). For low rho(c), the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted rho(c). In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of rho(c) extraction. This is accomplished by generalized error propagation curves that show the error in rho(c) caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where rho(c) < 5.10(-8) Omega.cm(2) has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to similar to 50% error in the estimation of rho(c).

  • 16.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 500 degrees C 8-b Digital-to-Analog Converter in Silicon Carbide Bipolar Technology2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 9, p. 3445-3450Article in journal (Refereed)
    Abstract [en]

    High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 degrees C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 degrees C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 degrees C are 0.79 and 1.01 LSB, respectively, while at 500 degrees C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 degrees C and 500 degrees C, respectively.

  • 17. Huang, Daming
    et al.
    Liu, Wei
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Liu, Zhiying
    KTH, School of Information and Communication Technology (ICT), Material Physics.
    Liao, C. C.
    Zhang, Li-Fei
    Gan, Zhenghao
    Wong, Waisum
    Li, Ming-Fu
    A Modified Charge-Pumping Method for the Characterization of Interface-Trap Generation in MOSFETs2009In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 2, p. 267-274Article in journal (Refereed)
    Abstract [en]

    A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence (similar to t(n)) of interface-trap generation is observed. The index n. is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics.

  • 18.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH.
    Schröder, Stephan
    KTH.
    Rodriguez, Saul
    KTH.
    Malm, B. Gunnar
    KTH.
    Östling, Mikael
    KTH.
    Rusu, Ana
    KTH.
    An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

  • 19.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pandey, Himadri
    University of Siegen.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    University of Siegen.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Optimization of a Compact I–V Model forGraphene FETs: Extending Parameter Scalability for Circuit Design Exploration2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3870-3875Article in journal (Refereed)
    Abstract [en]

    An optimization of the current-to-voltage transfer characteristic of a graphene FET (GFET) compact model, based on drift-diffusion carrier transport, is presented. The improved accuracy at Dirac point extends the model usability for GFETs when scaling parameters, such as voltage supply, gate length, oxide thickness, and mobility, for circuit design exploration. The model's accuracy is demonstrated through fitting to GFETs processed in-house. The model has been written in a standard behavioral language, and extensively run in an analog circuit simulator for designing basic circuits, such as inverters and cascode cells, demonstrating its robustness.

  • 20. Illarionov, Yury
    et al.
    Smith, Anderson
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mueller, Thomas
    Lemme, Max
    Grasser, Tibor
    Hot-Carrier Degradation and Bias-Temperature Instability in Single-Layer Graphene Field-Effect Transistors: Similarities and Differences2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3876-3881Article in journal (Refereed)
    Abstract [en]

    We present a detailed analysis of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs) and compare those findings with the bias-temperature instability (BTI). Our results show that the HCD in GFETs is recoverable, similar to its BTI counterpart. Moreover, both the degradation mechanisms strongly interact. Particular attention is paid to the dynamics of HCD recovery, which can be well fitted with the capture/emission time (CET) map model and the universal relaxation function for some stress conditions, quite similar to the BTI in both GFETs and Si technologies. The main result of this paper is an extension of our systematic method for benchmarking new graphene technologies for the case of HCD.

  • 21.
    Kargarrazi, Saleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Saggini, Stefano
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    500 degrees C Bipolar SiC Linear Voltage Regulator2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 6, p. 1953-1957Article in journal (Refereed)
    Abstract [en]

    In this paper, we demonstrate a fully integrated linear voltage regulator in silicon carbide NPN bipolar transistor technology, operational from 25 degrees C up to 500 degrees C. For 15-mA load current, this regulator provides a stable output voltage with <2% variation in the temperature range 25 degrees C-500 degrees C. For both line and load regulations, degradation of 50% from 25 degrees C to 300 degrees C and improvement of 50% from 300 degrees C to 500 degrees C are observed. The transient response measurements of the regulator show robust behavior in the temperature range 25 degrees C-500 degrees C.

  • 22. Kassamakova, L
    et al.
    Kakanakov, R D
    Kassamakov, I V
    Nordell, N
    Savage, S
    Hjorvarsson, B
    Svedberg, E B
    Abom, L
    Madsen, L D
    Temperature stable Pd ohmic contacts to p-type 4H-SiC formed at low temperatures1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 3, p. 605-611Article in journal (Refereed)
  • 23.
    Kundozerova, Tatyana V.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Grishin, Alexander M.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Stefanovich, G. B.
    Velichko, A. A.
    Anodic Nb2O5 Nonvolatile RRAM2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 4, p. 1144-1148Article in journal (Refereed)
    Abstract [en]

    We report nonvolatile resistive switching in anodic niobium pentoxide thin-film memory cells. Highly dielectric Nb2O5 films were prepared at room temperature by the anodic oxidation of submicrometer-thick Nb films sputtered onto an Si wafer. After the electroforming process, Au/Nb2O5/Nb/Si sandwich memory cells demonstrate reproducible direct current and pulse mode switching between two resistance states with a resistance ON-OFF ratio around 10(3). Low and high resististive states show ohmic conductivity and field-assisted Poole-Frenkel-type conductivity, respectively. Nonvolatile resistance storage was traced within 40 days to quantify retention characteristics of the Nb2O5 memristor. The low-temperature anodic oxidation of Nb was found to be feasible to fabricate high-density cross-point memory with 3-D stack structures.

  • 24.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 4, p. 1076-1083Article in journal (Refereed)
    Abstract [en]

    Operation up to 300 degrees C of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter-coupled logic is demonstrated. Stable noise margins of about 1 V are reported for a two-input OR-NOR gate operated on - 15 V supply voltage from 27 degrees C up to 300 degrees C. In the same temperature range, an oscillation frequency of about 2 MHz is also reported for a three-stage ring oscillator.

  • 25.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 8, p. 1894-1898Article in journal (Refereed)
    Abstract [en]

    This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 x 1.8 nun (with an active area of 3.24 mm') showed a common emitter current gain 0 of 42, specific on-resistance Rsp ON of 9 mQ - em', and open-base breakdown voltage BVcEO of-1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the p+ regrown layer from the surface of the emitter-base junction. The BJT with p+ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs; with only etched flat-surface JTE.

  • 26.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Low-forward-voltage-drop 4H-SiC BJTs without base contact implantation2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 8, p. 1907-1911Article in journal (Refereed)
    Abstract [en]

    Bipolar junction transistors (BJTs) of 4H-SiC, with a low collector--emitter forward voltage drop YCE, have been fabricated without base contact implantation. A comparison of BJTs on the same wafer with and without base contact implantation shows less than 10% higher VcE for the BJTs without base contact implantation. Omitting the base contact implantation eliminates high concentrations of implantation-induced defects that act as recombination centers. This is advantageous because it allows a shorter distance Wp+ between the emitter edge and the base contact, without affecting the current gain when no base contact implantation is used. The BJTs without contact implantation show a constant current gain as Wp+ was reduced from 3 to I pm, whereas the gain decreased by 45% for the BJTs with base contact implantation for the same reduction of Wp+. A key to the successful fabrication of low-forward-voltage-drop SiC BJTs without base contact implantation is the formation of low-resistivity Ni/Ti/Al ohmic contacts to the base. The contact resistivity on the base region (N-A approximate to 4 x 10(17) cm(-3)) was measured with linear transmission line method structures to PC = 1.9 X 10(-3) Omega cm(2), whereas the contact resistivity with the base contact implantation was PC = 1.3 x 10-4 Omega cm(2), both after rapid thermal processing annealing at 800 degrees C.

  • 27.
    Litta, Eugenio Dentoni
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 934-939Article in journal (Refereed)
    Abstract [en]

    Integration of a high-k interfacial layer (IL) is a promising technological solution to improve the scalability of high-k/metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiOx/HfO2 nFETs (0.7 A/cm(2) at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and -0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO2 stack, i.e., improved channel mobility over SiOx/HfO2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm(2)/Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO2/TiN gate stack is investigated, demonstrating 10-year expected life-times for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.

  • 28.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Dongping
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Qiu, Zhijun
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Lu, Jun
    Department of Physics, Chemistry and Biology, Linköping University.
    Hultman, Lars
    Department of Physics, Chemistry and Biology, Linköping University.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    On Different Process Schemes for MOSFETs With a Controllable NiSi-Based Metallic Source/Drain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 1898-1906Article in journal (Refereed)
    Abstract [en]

    This paper focuses on different silicidation schemes toward a controllable NiSi-based metallic source/drain (MSD) process with restricted lateral encroachment of NiSi. These schemes include thickness control of Ni, Ni-Pt alloying, and two-step annealing. Experimental results show that all the three process schemes can give rise to effective control of lateral encroachment during Ni silicidation. By controlling t(Ni), NiSi-based MSD metal-oxide-semiconductor field-effect transistors (MOSFETs) of gate length L-G = 55 nm are readily realized on ultrathin-body silicon-on-insulator substrates with 20-nm surface Si thickness. With the aid of dopant segregation (DS) to modifying the Schottky barrier heights of NiSi, both n- and p-type MSD MOSFETs show significant performance improvement, compared to reference devices without DS.

  • 29.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Donping
    Qiu, Zhijun
    Lu, Jun
    Hultman, Lars
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    On different process schemes for a controllable NiSi-based metallic source/drainMOSFETs with dopant segregationIn: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646Article in journal (Other academic)
  • 30. Lutz, Josef
    et al.
    Baburske, Roman
    Chen, Min
    Heinze, Birk
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Felsl, Hans-Peter
    Schulze, Hans-Joachim
    The nn(+)-Junction as the Key to Improved Ruggedness and Soft Recovery of Power Diodes2009In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 11, p. 2825-2832Article in journal (Refereed)
    Abstract [en]

    The effects during reverse recovery of pin power diodes are determined by free carriers and their interaction with the electric field. A density of free carriers higher than the background doping will easily occur in space-charge regions during reverse recovery of high-voltage silicon devices. As a result, a high electric-field strength combined with avalanche generation occurs at the p-n junction. However, if a second region with high electric-field strength arises at the nn(+)-junction, the situation can become critical. If the second electric-field peak can be suppressed, it is possible to make diodes that are very rugged and show a significantly improved soft-recovery behavior.

  • 31.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Haralson, E.
    Johansson, T.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Self-heating effects in a BiCMOS on SOI technology for RFIC applications2005In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 52, no 7, p. 1423-1428Article in journal (Refereed)
    Abstract [en]

    Self-heating in a 0.25 mu m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In, the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.

  • 32. Melvås, Patrik
    et al.
    Stemme, Göran
    KTH, Superseded Departments, Signals, Sensors and Systems.
    A diode-based two-wire-solution for temperature-compensated piezoresistive pressure sensors2003In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 50, no 2, p. 503-509Article in journal (Refereed)
    Abstract [en]

    A novel two-wire solution for ultraminiaturized temperature-compensated piezoresistive pressure sensors is presented. The technique makes it possible to measure both pressure and temperature separately by using bias-controlled diodes as switches between the pressure and temperature sensing elements. The pn-junction diodes are, forward-biased or reverse-biased depending on the polarization of the voltage supply. The new diode-based two-wire technique was evaluated using a surface micromachined pressure sensor,where the pressure-sensing element consists of a piezoresistor on an (80 x 40 x 1 mum) double end supported force-transducing beam. The beam is located beneath a (100 x 100 x 2 mum) square polysilicon diaphragm having its ends attached to the diaphragm and to the cavity edge. The thermal compensation piezoresistor is also located in the cavity on a (100 x 40 x 1 mum) beam. Both ends of this beam are attached to the cavity edge and are therefore pressure-insensitive. The new detection solution enables a reduction of conducting leads from three to two in combination with,high pressure sensitivity (0.7 muV/V/mmHg) and environmental isolation compared to a commercialized traditional piezoresistive pressure sensor. Its simplicity and the potential for size reduction due to fewer bonding pads and conducting wires make it ideal for applications such as disposable blood pressure sensor where cost and size are critical parameters.

  • 33.
    Oberhammer, Joachim
    et al.
    KTH, Superseded Departments, Signals, Sensors and Systems.
    Stemme, Göran
    KTH, Superseded Departments, Signals, Sensors and Systems.
    Low-voltage high-isolation DC-to-RF MEMS switch based on an S-shaped film actuator2004In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 51, no 1, p. 149-155Article in journal (Refereed)
    Abstract [en]

    This paper presents a new electrostatically actuated microelectromechanical series switch for switching dc to radio frequency (RF) signals. The device is based on a flexible S-shaped film moving between a top and a bottom electrode in touch-mode actuation. This concept, in contrast to most other microelectrocheinical systems (MEMS) switches, allows a design with a low actuation voltage independent of the off-state gap height. This makes larger nominal switching contact areas for lower insertion loss possible, by obtaining high isolation in the off-state. The actuation voltages of the first prototype switches are 12 V to open, and 15.8 V to close the metal contact. The RF isolation with a gap distance of 14.2 mum is better than -45 dB up to 2 GHz and -30 dB at 15 GHz despite a large nominal switching contact area of 3500 mum(2).

  • 34. Olsen, Sarah H.
    et al.
    Escobedo-Cousin, Enrique
    Varzgar, John B.
    Agaiby, Rimoon
    Seger, Johan
    Dobrosz, Peter
    Chattopadhyay, Sanatan
    Bull, Steve J.
    O'Neill, Anthony G.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Edholm, Jonas
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lyutovich, Klara L.
    Oehme, Michael
    Kasper, Erich
    Control of self-heating in thin virtual substrate strained Si MOSFETs2006In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 53, no 9, p. 2296-2305Article in journal (Refereed)
    Abstract [en]

    This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates,,the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good ON-state performance, OFF-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented.

  • 35. Persson, Stefan
    et al.
    Fjer, Mouhine
    Escobedo-Cousin, Enrique
    Olsen, Sarah H.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wang, Yong-Bin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    O'Neill, Anthony G.
    Strained-Silicon Heterojunction Bipolar Transistor2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 6, p. 1243-1252Article in journal (Refereed)
    Abstract [en]

    Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained Si0.7Ge0.3 base on top of a relaxed Si0.85Ge0.15 collector. By using a Si0.85Ge0.15 virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain beta of 27x over a conventional silicon bipolar transistor and 11x over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level.

  • 36.
    Qiu, Zhijun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 1, p. 396-403Article in journal (Refereed)
    Abstract [en]

    An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SUDS is relatively simple in processing, but the silicidation process is dopant-dependent, leading to local variations of silicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation.

  • 37.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    Rusu, Ana
    Static Nonlinearity in Graphene Field Effect Transistors2014In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 61, no 8, p. 3001-3003Article in journal (Refereed)
    Abstract [en]

    The static linearity performance metrics of the graphene-based field effect transistor (GFET) transconductor are studied and modeled. Closed expressions are proposed for second-and third-order harmonic distortion (HD2, HD3), second-and third-order intermodulation distortion (Delta IM2, Delta IM3), and second-and third-order intercept points (A(IIP2), A(IIP3)). The expressions are validated through large-signal simulations using a GFET VerilogA analytical model and a commercial circuit simulator. The proposed expressions can be used during circuit design to predict the GFET biasing conditions at which linearity requirements are met.

  • 38.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fregonese, Sebastien
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Comprehensive Graphene FET Model for Circuit Design2014In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 61, no 4, p. 1199-1206Article in journal (Refereed)
    Abstract [en]

    During the last years, graphene-based field-effect transistors (GFETs) have shown outstanding RF performance; therefore, they have attracted considerable attention from the electronic devices and circuits communities. At the same time, analytical models that predict the electrical characteristics of GFETs have evolved rapidly. These models, however, have a complexity level that can only be handled with the help of a circuit simulator. On the other hand, analog circuit designers require simple models that enable them to carry out fast hand calculations, i.e., to create circuits using small-signal hybrid-pi models, calculate figures of merit, estimate gains, pole-zero positions, and so on. This paper presents a comprehensive GFET model that is simple enough for being used in hand calculations during circuit design and at the same time, it is accurate enough to capture the electrical characteristics of the devices in the operating regions of interest. Closed analytical expressions are provided for the drain current I-D, small-signal transconductance gain g(m), output resistance r(o), and parasitic capacitances C-gs and C-gd. In addition, figures of merit, such as intrinsic voltage gain A(V), transconductance efficiency g(m)/I-D, and transit frequency f(T) are presented. The proposed model has been compared to a complete analytical model and also to measured data available in current literature. The results show that the proposed model follows closely to both the complete analytical model and the measured data; therefore, it can be successfully applied in the design of GFET analog circuits.

  • 39. Rohner, M.
    et al.
    Willen, Bo G.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jackel, H.
    Sub-f(t) gain resonance of InP/InGaAs-HBTs2002In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 49, no 2, p. 213-220Article in journal (Refereed)
    Abstract [en]

    Advanced npn-InP/InGaAs HBTs are often operated at high current levels for optimum high-speed performance. Because of velocity modulation effects, these transistors may operate in base-pushout although measurements of the cut-off frequency f(t) indicate the opposite. We show that the low mobility of the holes has a strong effect on the transistor operation in this regime, which is only revealed from a dynamic analysis: The unilateral power gain peaks far below f(t) followed by a -40 dB/dec roll-off. The effect was thoroughly analyzed and as a result, we present a simple equivalent circuit model that successfully describes transistors operating in pushout up to very high frequencies.

  • 40. Rohner, M.
    et al.
    Willen, Bo G.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jackel, H.
    Velocity modulation in III/V-HBTs2003In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 50, no 5, p. 1205-1213Article in journal (Refereed)
    Abstract [en]

    Velocity modulation is shown to have a strong impact on the base/collector capacitance and the collector transit-time delay which dominate the high-speed performance of state-of-the-art HBTs. The authors present a theoretical analysis of the velocity modulation effects, which is the base of a method to assess their strength from measured S-parameters. Monte Carlo simulations are in good agreement with the measurements, providing strong support for the theory. As a consequence, the authors find that the carrier velocity is much lower than estimated from transit-time measurements when neglecting velocity modulation and that base-pushout occurs at much lower current levels than commonly expected.

  • 41.
    Roy, Sajib
    et al.
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Rashid, Arman Ur
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Abbasi, Affan
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Murphree, Robert C.
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Hossain, Md Maksudul
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Faruque, Asif
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Metreveli, Alex
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Fraley, John
    Wolfspeed, Fayetteville, AR 72701 USA..
    Sparkman, Brett
    Wolfspeed, Fayetteville, AR 72701 USA..
    Mantooth, H. Alan
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Silicon Carbide Bipolar Analog Circuits for Extreme Temperature Signal Conditioning2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 9, p. 3764-3770Article in journal (Refereed)
    Abstract [en]

    This paper presents functional hightemperature analog circuits in silicon carbide bipolar technology. The circuits will collectively form the analog signal conditioning block for a wireless telemetry system in an extreme environment (above 400 degrees C). The signal conditioningblock is composed of a lowdc gain operational amplifier, a negative voltage charge pump (CP), an RC oscillator, and a voltage regulator. The circuits are tested up to 450 degrees C. The measured open-loop gain for the amplifier at 450 degrees C is 30 dB. The regulator provides approximately 9-V output at 450 degrees C for a fixed load current of up to 18 mA and an applied reference of 4.5 V. The negative voltage CP requires an oscillating signal at its input, which is provided by the RC cross-coupled oscillator. The CP provides about -5 V at 450 degrees C.

  • 42.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Comprehensive Study on the Geometrical Effects in High Power 4H-SiC BJTs2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 3, p. 882-887Article in journal (Refereed)
    Abstract [en]

    Geometrical effects on the forward characteristics of high-power bipolar junction transistors are studied.An implantation-free area optimized junction termination is implemented in order to have a stable breakdown voltage. The effect of varying the emitter-base geometry, i.e., the emitter width (WE), the base width (WB), emitter contact–emitter edge distance (Wn), and base contact–emitter edge (Wp) on the on-state characteristics is studied in the different emitter cell geometries. The emitter size effect shows the highest influence on the current gain (β). It shows a significant effect on the β (single finger design, about 61%; square cell geometry, about 98%;hexagon cell geometry, about 90%). The base size effect also shows a significant improvement on the β of about 23% at a given WE.

  • 43. Sanden, M.
    et al.
    Marinov, O.
    Deen, M. J.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A new model for the low-frequency noise and the noise level variation in polysilicon emitter BJTs2002In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 49, no 3, p. 514-520Article in journal (Refereed)
    Abstract [en]

    This work presents a new, physically-based model for the low-frequency noise in high-speed polysilicon emitter bipolar junction transistors (BJTs). Evidence of the low-frequency noise originating mainly from a superposition of generation-recombination (g-r) centers is presented. Measurements of the equivalent input noise spectral density (S-IB) showed that for BJTs with large emitter areas (A(E)) S-IB, is proportional to 1/f, as expected. In contrast, the noise spectrum for BJTs with submicron AE showed a strong variation from a 1/f-dependence, due to the presence of several g-r centers. However, the average spectrum (SIB) has a frequency dependence proportional to 1/f for BJTs with large as well as small AE. The proposed model, based only on superposition of g-r centers, can predict the frequency-, current-, area-, and variation-dependency of (S,,) with excellent agreement to the measurement results. The SPICE parameter K-F, extracted from (S,,) is found to be proportional to 1/A(E) with the product KF x AE = 4.3 x 10 (-17) cm(2). The relative variation in the noise level is found to be proportional to A(E)(-0.5), resulting in an absolute variation proportional to A (-1.5)(E). The g-r centers are most likely located next to the thin SiO2, interfacial layer between the polysilicon and monosilicon emitter. The areal trap density, responsible for the low-frequency noise within 1-10(4) Hz, is estimated to be n(T) = 3 X 10(9) cm(-2). From temperature measurement of one clearly observed g-r center, the extracted trap energy level and capture cross-section are 0.31 eV and 2 X 10(-19) cm(2), respectively.

  • 44. Sanden, M.
    et al.
    Zhang, Shi-Li
    Grahn, J. V.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A new test structure for extracting extrinsic parameters in double-polysilicon bipolar transistors2000In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 47, no 9, p. 1767-1769Article in journal (Refereed)
    Abstract [en]

    A new test structure for parameter extraction is presented and implemented in a double-polysilicon bipolar junction transistor (BJT) process, The test structure is basically a real BJT, but without the intrinsic base. The test structure allows extraction of the base, collector and emitter impedances, and the extrinsic base-collector capacitance.

  • 45.
    Shah, Umer
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Sterner, Mikael
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Oberhammer, Joachim
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Analysis of Linearity Deterioration in Multidevice RF MEMS Circuits2014In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 61, no 5, p. 1529-1535Article in journal (Refereed)
    Abstract [en]

    This paper presents for the first time an RF nonlinearity analysis of complex multidevice radio frequency microelectromechanical system (RF MEMS) circuits. The IIP3 of different RF MEMS multidevice tunable-circuit concepts including digital MEMS varactor banks, MEMS switched capacitor banks, distributed MEMS phase shifters, and MEMS tunable filters, is investigated. Closed-form analytical formulas for the IIP3 of MEMS multidevice circuit concepts are derived. A nonlinearity analysis, based on measured device parameters, is presented for exemplary circuits of the different concepts using a multidevice nonlinear electromechanical circuit model implemented in Agilent Advanced Design System. The results of the nonlinear electromechanical model are also compared with the calculated IIP3 using derived equations for the digital MEMS varactor bank and MEMS switched capacitor bank. The degradation of the overall circuit linearity with increasing number of device stages is also investigated, with the conclusion that the overall circuit IIP3 is reduced by half when doubling the number of stages, if proper design precautions are not taken. Design rules are presented so that the mechanical parameters and thus the IIP3 of the individual device stages can be optimized to achieve a higher overall IIP3 for the whole circuit. In addition, the nonlinearity of a novel MEMS tunable capacitor concept introduced by the authors, based on an MEMS actuator with discrete tuning steps, is discussed and the IIP3 is calculated using derived analytical formulas.

  • 46.
    Shakir, Muhammad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hou, Shuoben
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Metreveli, Alex
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rashid, Arman Ur
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Mantooth, Homer Alan
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    555-Timer and Comparators Operational at 500 degrees C2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 9, p. 3734-3739Article in journal (Refereed)
    Abstract [en]

    This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 degrees C-500 degrees C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation.

  • 47.
    Smith, Anderson D.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Wagner, Stefan
    Kataria, Satender
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Wafer-Scale Statistical Analysis of Graphene FETs-Part I: Wafer-Scale Fabrication and Yield Analysis2017In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 9, p. 3919-3926Article in journal (Refereed)
    Abstract [en]

    Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing.

  • 48.
    Smith, Anderson D.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Wagner, Stefan
    Kataria, Satender
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Wafer-Scale Statistical Analysis of Graphene Field-Effect Transistors-Part II: Analysis of Device Properties2017In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 9, p. 3927-3933Article in journal (Refereed)
    Abstract [en]

    In Part I, we have established a wafer-scale, CMOS compatible graphene transfer for the back end of the line integration. In Part II of this paper, we analyze statistical data of device properties and draw conclusions about possible causes of device failure. Statistical analysis is performed for device mobility and compared with the yield analysis. To complement this analysis, detailed Raman spectra are employed to analyze strain. In addition, device models developed in Part I are examined and provide further insight. From the analysis, it appears that compressive strain introduced during the graphene transfer process is may be the primary source for device failure. Moreover, we speculate based on the device statistics that the mitigation of compressive strain will improve device mobility, carrier density, and reduce variability. In addition, the presence of residues, tears, and cracks in the graphene may result in some device failure.

  • 49.
    Somjit, Nutapong
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Oberhammer, Joachim
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Power Handling Analysis of High-Power W-Band All-Silicon MEMS Phase Shifters2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 5, p. 1548-1555Article in journal (Refereed)
    Abstract [en]

    This paper analyzes the power handling capability and the thermal characteristics of an all-silicon dielectric-block microelectromechanical-system (MEMS) phase-shifter concept, which is the first MEMS phase-shifter type whose power handling is not limited by the MEMS structures but only by the transmission line itself and by the heat-sink capabilities of the substrate, which enables MEMS phase-shifter technology for future high-power high-reliability applications. The power handling measurements of this concept are performed up to 43 dBm (20W) at 3 GHz with an automatic gain-controlled setup, assisted by a large-signal network analyzer, and the temperature rises of the devices were measured with an infrared microscope camera. The measurement results are extended to 40 dBm at 75 GHz by calibrating electrothermal simulations with the measurements. A comparative study to conventional state-of-the-art MEMS phase-shifter concepts based on thin metallic bridges is carried out. The simulated results show that the all-silicon phase-shifter designs have the maximum temperature rise of only 30 degrees C for 40 dBm at 75 GHz, which is 10-20 times less than conventional MEMS phase shifters of the comparable RF performance.

  • 50.
    Sterner, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Oberhammer, Joachim
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Static Zero-Power-Consumption Coplanar Waveguide Embedded DC-to-RF Metal-Contact MEMS Switches in Two-Port and Three-Port Configuration2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 7, p. 1659-1669Article in journal (Refereed)
    Abstract [en]

    This paper reports on novel electrostatically actuated dc-to-RF metal-contact microelectromechanical systems (MEMS) switches, featuring a minimum transmission line discontinuity since the whole switch mechanism is completely embedded inside the signal line of a low-loss 3-D micromachined coplanar waveguide. Furthermore, the switches are based on a multistable interlocking mechanism resulting in static zero-power consumption, i.e., both the onstate and the offstate are maintained without applying external actuation energy. Additionally, the switches provide with active opening capability, potentially improving the switch reliability, and enabling the usage of soft low-resistivity contact materials. Both two-port single-pole-single-throw (SPST) switches featuring mechanical bistability and three-port single-pole-double-throw (SPDT) T-junction switches with four mechanically stable states are presented. The switches, together with the transmission lines, are fabricated in a single photolithography process. The loss created by the discontinuity of the switch mechanism alone is 0.08 dB at 20 GHz. Including a 500 mu m long transmission line with less than 0.4 dB/mm loss up to 20 GHz, the total insertion loss of the two-port devices is 0.15 and 0.3 dB at 2 and 20 GHz, and the isolation is 45 and 25 dB at 2 and 20 GHz. The three-port switches, including their T-junction transmission line, have an insertion loss of 0.31 and 0.68 dB, and an isolation of 43 and 22 dB, at 1 and 10 GHz, respectively. Actuation voltages are 23-39 V for the two-port switches and 39-89 V for the three-port switches. The microwave propagation in the micromachined transmission line and the influence of the different switch designs were analyzed by finite-element method (FEM) simulations of electromagnetic energy and volume current distributions, proving the design advantages of the proposed concept.

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