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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 3.
    Garidis, Konstantinos
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration2015In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 165-168Conference paper (Refereed)
    Abstract [en]

    We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

  • 4.
    Hamawandi, Bejan
    et al.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Noroozi, Mohammad
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ergül, Adem
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Zahmatkesh, Katayoun
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Toprak, Muhammet S.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Electrical properties of sub-100 nm SiGe nanowires2016In: Journal of semiconductors, Vol. 37, no 10Article in journal (Refereed)
    Abstract [en]

    In this study, the electrical properties of SiGe nanowires in terms of process and fabrication integrity, measurement reliability, width scaling, and doping levels were investigated. Nanowires were fabricated on SiGe-on oxide (SGOI) wafers with thickness of 52 nm and Ge content of 47%. The first group of SiGe wires was initially formed by using conventional I-line lithography and then their size was longitudinally reduced by cutting with a focused ion beam (FIB) to any desired nanometer range down to 60 nm. The other nanowires group was manufactured directly to a chosen nanometer level by using sidewall transfer lithography (STL). It has been shown that the FIB fabrication process allows manipulation of the line width and doping level of nanowires using Ga atoms. The resistance of wires thinned by FIB was 10 times lower than STL wires which shows the possible dependency of electrical behavior on fabrication method.

  • 5.
    Hellström, Per-Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of Silicon Nanowires with CMOS2014In: Beyond CMOS Nanodevices 1, Wiley Blackwell , 2014, p. 65-72Chapter in book (Other academic)
    Abstract [en]

    Silicon nanowires exhibit attractive characteristics that have motivated their use as the sensor element in a biochemical sensor system. An integrated silicon nanowire and complementary metal-oxide-semiconductor (CMOS) circuit chip would allow more design freedom with respect to interaction with the full biochemical sensor system, including interaction with the electrolyte solution. The CMOS fabrication process is divided into two parts, called the front-end-of-line (FEOL) and back-end-of-line (BEOL) processing. A CMOS process that allows the integration of silicon nanowires, as described in this chapter offers a vast amount of design opportunities to enhance the performance of the silicon nanowire-based sensor. The chapter describes a sensor design that allows measurement of the conductance variations of biosensitive silicon nanowires in a serial manner by using on-chip integrated CMOS circuitry. Integration of silicon nanowires can also be achieved by defining the silicon nanowires in the silicon layer of a SOI wafer.

  • 6.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Silicon nanowire based devices for More than Moore Applications2018Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. While the recent research has concentrated predominantly on utilizing single or multiple SiNW for biosensing applications, very few attempts have been made to integrate SiNW with complementary-metal-oxide- semiconductor (CMOS) integration to arrive at a complete lab-on-chip (LOC) sensor. Further, the manufacturing methods reported thus far in the production of SiNW for biosensing applications have not fully exploited both the front-end-of-line (FEOL) as well as back-end-of-line (BEOL) methods in CMOS integration. Neither does the research community address CMOS integration based methods to realize multi and specific target detection that are important attributes for an ideal LOC biosensor.

    Integration of SiNW with CMOS circuitry will facilitate real time detection of the output signal and in addition provide a compact small sized sensor that is fully portable operating at high speed. In order to avail the benefits of CMOS circuits and develop a large scale production friendly LOC sensor, the scheme of SiNW fabrication has to facilitate either the FEOL or BEOL CMOS integration schemes. This thesis work is focused on revealing a novel FEOL as well as BEOL scheme for integration of SiNW with CMOS circuitry. The major part of the FEOL research work is concentrated on developing a high volume SiNW manufacturing method that is suitable for industrial production. Likewise, in the BEOL scheme, predominant focus was to develop a wafer scale scheme to integrate network of nanowires (nanonets) with CMOS circuitry to manufacture a monolithic 3D above-IC LOC biosensor.

    In the FEOL scheme, the SiNWs are fabricated using a revised pattern transfer technique called sidewall transfer lithography (STL). The STL method is identified as one of the efficient methods of fabricating SiNW as it uses CMOS industry grade materials that is fully compatible with the FEOL fabrication scheme. Thanks to the usage of single lithography and controlled selective etching techniques used in the STL process, the line width and aspect ratio of the SiNW can be tailored to suit the requirements for DNA hybridization detection. A fabrication process flow matching standard CMOS process integration flows has been developed to integrate SiNW with HfO2 and TiN metal gate MOSFETS. An emphasis has been placed in the design of a novel pixel matrix based SiNW LOC sensor. Specific and multi-target detection has been kept as top priority in the design of the SiNW LOC sensor. The possibility to monitor the potential of the electrolyte during the detection process using a fluid gate has been accounted in this design. Furthermore, the SiNW pixel design eliminates the intricate microfluidics and eases access to the SiNW test site using a simple photolithography mask and RIE. The SiNW and MOSFETS demonstrate excellent electrical characteristics. For the very first time, the concept to access single as well as multiple array SiNW pixels using a transistor has been successfully demonstrated.

    In the BEOL scheme, the nanonets are fabricated using the bottom-up method and transferred onto a pre-fabricated CMOS wafer supplied by ams foundry. The connection between the nanonets lying above-IC and the underlying CMOS layer was established by employing a thin metal backgate electrode, backgate dielectric and metal source/drain contact pads. Many challenges in the BEOL scheme have been identified and overcome by incorporating efficient device architecture and careful selection of materials. To the first of its kind, a wafer scale process was developed to integrate nanonets with CMOS to form a monolithic 3D IC. The devices exhibit excellent electrical characteristics and lower leakage currents compared to standalone nanonet sensors fabricated on Si/SiN substrate. Further, the FEOL and BEOL integration schemes are compared and the various pro’s and con’s of both approaches for integration of SiNW with CMOS circuits to build a LOC biosensor are discussed in detail.

    Finally, dry environment DNA hybridization detection is demonstrated on the surface of thin HfO2 encapsulated SiNW sensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bio-processes. More specifically, based on a statistical analysis, it is demonstrated that 85% of the tested devices were efficient for DNA hybridization detection. The estimated density of hybridized DNA was in the order of 1010 cm-2. These promising results of realizing a SiNW based lab-on-chip platform through the FEOL and BEOL monolithic integration of SiNW and CMOS circuitry further strengthen the profile of SiNW as a nano biosensor. Indeed, this is expected to pave the way for more than Moore applications of SiNW based devices and integrated circuits.

  • 7.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon Nanowires Integrated in a Fully Depleted CMOS Process for Charge Based Biosensing2013In: ULIS 2013: The 14th International Conference on Ultimate Integration on Silicon, Incorporating the 'Technology Briefing Day', IEEE , 2013, p. 81-84Conference paper (Refereed)
    Abstract [en]

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of 32 by 32 pixel matrix (1024 pixels or test sites) and 8 input-output (I/O) pins. In each pixel single crystalline SiNW with 60 by 20 nm cross-section area is defined using sidewall transfer lithography (STL) in the SOI layer. The key advantage of the design is that 1024 individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  • 8.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon nanowires integrated with CMOS circuits for biosensing application2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 26-31Article in journal (Refereed)
    Abstract [en]

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  • 9.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellstrom, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication and characterization of silicon nanowires using STL for biosensing applications2014In: INT CONF ULTI INTEGR, ISSN 2330-5738, p. 109-112Article in journal (Refereed)
    Abstract [en]

    We present a sidewall transfer lithography (STL) process to fabricate silicon nanowires using the CMOS compatible materials SiO2, SiN and alpha-Si. The STL process is implemented using a single cluster tool for reactive ion etching (RIE) and plasma enhanced chemical vapor deposition (PECVD) with a maximum process temperature of 400 degrees C. Using three lithography masks, single and multiple silicon nanowires connected to contact areas can be defined. By optimizing layer thicknesses, RIE and deposition conformity we demonstrate wafer scale definition of 60 nm wide silicon nanowires using I-line stepper lithography. The silicon nanowires exhibit excellent characteristics for biosensing applications with subthreshold slopes of 75 mV/dec and a high on/off current ratio of more than 10(5).

  • 10.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application2018In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 9, no 11, article id 544Article in journal (Refereed)
    Abstract [en]

    Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (V-G) and backgate voltage (V-BG). The liquid potential can be monitored using the FG. We report the transfer characteristics (I-D-V-G) of N- and P-type SiRi pixels. Further, the I-D-V-G characteristics of the SiRis are studied at different V-BG. The application of V-BG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (V-TH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large V-BG (25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large V-BG to switch ON. Thus, P-type pixels exhibit excellent I-ON/I-OFF 10(6), SS of 70-80 mV/dec and V-TH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

  • 11.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors2019In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 212, p. 13-20Article in journal (Refereed)
    Abstract [en]

    Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.

  • 12.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Legallais, Maxime
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Mouis, Mireille
    Pignot-Paintrand, Isabelle
    Stambouli, Valérie
    Ternon, Céline
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment2019In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 18Article in journal (Refereed)
  • 13.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Legallais, Maxime
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mouis, Mireille
    Stambouli, Valerie
    Ternon, Celine
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication and characterization of high-K dielectric integrated silicon nanowire sensor for DNA sensing application2016In: BIOSENSING AND NANOMEDICINE IX, SPIE - International Society for Optical Engineering, 2016, article id UNSP 99300QConference paper (Refereed)
  • 14.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Pixel-based biosensor for enhanced control: silicon nanowires monolithically integrated with field-effect transistors in fully depleted silicon on insulator technology2019In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 22, article id 225502Article in journal (Refereed)
    Abstract [en]

    Silicon nanowires (SiNWs) are a widely used technology for sensing applications. Complementary metal-oxide-semiconductor (CMOS) integration of SiNWs advances lab-on-chip (LOC) technology and offers opportunities for read-out circuit integration, selective and multiplexed detection. In this work, we propose novel scalable pixel-based biosensors exploiting the integration of SiNWs with CMOS in fully-depleted silicon-on-insulator technology. A detailed description of the wafer-scale fabrication of SiNW pixels using the CMOS compatible sidewall-transfer-lithography as an alternative to widely investigated time inefficient e-beam lithography is presented. Each 60 nm wide SiNWs sensor is monolithically connected to a control transistor and novel on-chip fluid-gate forming an individual pixel that can be operated in two modes: biasing transistor frontgate (V-G) or substrate backgate (V-BG). We also present the first electrical results of single N and P-type SiNW pixels. In frontgate mode, N and P-type SiNW pixels exhibit subthreshold slope (SS) approximate to 70-80 mV/dec and I-on/I-off approximate to 10(5). The N-type and P-type pixels have an average threshold voltage, Vth of -1.7 V and 0.85 V respectively. In the backgate mode, N and P-type SiNW pixels exhibit SS approximate to 100-150 mV/dec and I-on/I-off approximate to 10(6). The N and P-type pixels have an average V-th of 5 V and -2.5 V respectively. Further, the influence of the backgate and frontgate voltage on the switching characteristics of the SiNW pixels is also studied. In the frontgate mode, the Vth of the SiNW pixels can be tuned at 0.2 V for 1 V change in V-BG for N-type or at -0.2 V for -1 V change in V-BG for P-type pixels. In the backgate mode, it is found that for stable operation of the pixels, the V-G of the N and P-type transistors must be in the range 0.5-2.5 V and 0 V to -2.5 V respectively.

  • 15.
    Noroozi, Mohammad
    et al.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Hamawandi, Bejan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Zahmatkesh, Katayoun
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Toprak, Muhammet S.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    A comparison of power factor in n and p-type SiGe nanowires for thermoelectric applications2017In: Journal of Nanoscience and Nanotechnology, ISSN 1533-4880, E-ISSN 1533-4899, Vol. 71, no 3, p. 1622-1626Article in journal (Refereed)
    Abstract [en]

    This work presents the thermoelectric properties of n- and p-type doped SiGe nanowires and shows the potential to generate electricity from heat difference over nanowires. The Si0.74Ge0.26 layers were grown by reduced pressure chemical vapor deposition technique on silicon on insulator and were condensed to the final Si0.53Ge0.47 layer with thickness of 52 nm. The nanowires were formed by using sidewall transfer lithography (STL) technique at a targeted width of 60 nm. A high volume of NWs is produced per wafer in a time efficient manner and with high quality using this technique. The results demonstrate high Seebeck coefficient in both n- and p-types SiGe nanowires. N-type SiGe nanowires show significantly higher Seebeck coefficient and power factor compared to p-type SiGe nanowires near room temperature. These results are promising and the devised STL technique may pave the way to apply a Si compatible process for manufacturing SiGe-based TE modules for industrial applications.

  • 16.
    Noroozi, Mohammad
    et al.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Mensi, Mounir
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Optics and Photonics, OFO.
    Hamawandi, Bejan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Zahmatkesh, Katayoun
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Tafti, Mohsen. Y
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Marcinkevičius, Saulius
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Optics and Photonics, OFO.
    Hultman, Lars
    Ergül, Adem
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Ikonic, Zoran
    Toprak, Muhammet S.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Significant Improvement of Thermoelectric Efficiency in SiGe NanowiresArticle in journal (Refereed)
    Abstract [en]

    The thermoelectric (TE) properties of SiGe nanowires (NWs) with width of 60 nm in a back-gate configuration have been studied experimentally and theoretically. The carrier transport in NWs was modified by biasing voltage to the gate for different temperatures. The original wafers were SiGe-on-oxide (SGOI), which were formed through condensation of SiGe on Si-on-oxide wafers (SOI).  The power factor of SiGe NWs was enhanced by a factor of >2 in comparison with SiGe bulk material over a temperature range of 273 K to 450 K. This enhancement is mainly attributed to the energy filtering of carriers in SiGe NWs which were introduced by the roughness in the shape of NWs, non-uniform SiGe composition and the induced defects during the manufacturing of SGOI wafers or processing of NWs. These defects create potential barriers which may significantly enhance the Seebeck coefficient, while the conductivity can be boosted by tuning the back-gate bias.

  • 17.
    Noroozi, Mohammad
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics. Linköping University, Sverige.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Zahmatkesh, Katayoun
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Lu, J.
    Hultman, L.
    Mensi, Mounir
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Marcinkevicius, Saulius
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Hamawandi, Bejan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Yakhshi Tafti, Mohsen
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Ergül, Adem
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Ikonic, Z.
    Toprak, Muhammet
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Unprecedented thermoelectric power factor in SiGe nanowires field-effect transistors2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 9, p. Q114-Q119Article in journal (Refereed)
    Abstract [en]

    In this work, a novel CMOS compatible process for Si-based materials has been presented to form SiGe nanowires (NWs) on SiGe On Insulator (SGOI) wafers with unprecedented thermoelectric (TE) power factor (PF). The TE properties of SiGe NWs were characterized in a back-gate configuration and a physical model was applied to explain the experimental data. The carrier transport in NWs was modified by biasing voltage to the gate at different temperatures. The PF of SiGe NWs was enhanced by a factor of >2 in comparison with bulk SiGe over the temperature range of 273 K to 450 K. This enhancement is mainly attributed to the energy filtering of carriers in SiGe NWs, which were introduced by imperfections and defects created during condensation process to form SiGe layer or in NWs during the processing of NWs.

  • 18. Wang, G.
    et al.
    Luo, J.
    Qin, C.
    Cui, H.
    Liu, J.
    Jia, K.
    Li, J.
    Yang, T.
    Yin, H.
    Zhao, C.
    Ye, T.
    Yang, P.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of selective epitaxial growth of SiGe/Ge layers in 14nm node FinFETs2016In: ECS Transactions, Electrochemical Society Inc. , 2016, no 8, p. 273-279Conference paper (Refereed)
    Abstract [en]

    In this study, the process integration of SiGe selective epitaxy on source/drain and SiGe/Ge bilayers selectively epitaxy on replacement Si channel regions for 14 nm node FinFETs has been presented. The epi-quality, layer profile and strain amount of the selectively grown SiGe and Ge layers were also investigated by means of various characterization tools. A series of prebaking experiments were performed for different temperatures in order to in-situ clean the Si fins prior to the SiGe S/D epitaxy. It was also found that a SiGe layer with graded Ge content was deposited as the strain relaxed buffer (SRB) layer in the channel trench prior to the Ge layer filling in the small trenches to make the void defect free.

1 - 18 of 18
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