Ändra sökning
Avgränsa sökresultatet
1 - 14 av 14
RefereraExporteraLänk till träfflistan
Permanent länk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Träffar per sida
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sortering
  • Standard (Relevans)
  • Författare A-Ö
  • Författare Ö-A
  • Titel A-Ö
  • Titel Ö-A
  • Publikationstyp A-Ö
  • Publikationstyp Ö-A
  • Äldst först
  • Nyast först
  • Skapad (Äldst först)
  • Skapad (Nyast först)
  • Senast uppdaterad (Äldst först)
  • Senast uppdaterad (Nyast först)
  • Disputationsdatum (tidigaste först)
  • Disputationsdatum (senaste först)
  • Standard (Relevans)
  • Författare A-Ö
  • Författare Ö-A
  • Titel A-Ö
  • Titel Ö-A
  • Publikationstyp A-Ö
  • Publikationstyp Ö-A
  • Äldst först
  • Nyast först
  • Skapad (Äldst först)
  • Skapad (Nyast först)
  • Senast uppdaterad (Äldst först)
  • Senast uppdaterad (Nyast först)
  • Disputationsdatum (tidigaste först)
  • Disputationsdatum (senaste först)
Markera
Maxantalet träffar du kan exportera från sökgränssnittet är 250. Vid större uttag använd dig av utsökningar.
  • 1.
    Kumar, Shashi
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Soininen, Juha-Pekka
    Forsell, Martti
    Millberg, Mikael
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tiensyrja, Kari
    Hemani, Ahmed
    A network on chip architecture and design methodology2002Ingår i: VLSI 2002: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI - NEW PARADIGMS FOR VLSI SYSTEMS DESIGN, IEEE conference proceedings, 2002, s. 105-112Konferensbidrag (Refereegranskat)
    Abstract [en]

    We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m x n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (LP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multiprocessors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.

  • 2.
    Lu, Zhonghai
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Millberg, Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Bruce, Alistair
    van der Wolf, Pieter
    Henriksson, Tomas
    Flow Regulation for On-Chip Communication2009Ingår i: DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, 2009, s. 578-581Konferensbidrag (Refereegranskat)
    Abstract [en]

    We propose (sigma, rho)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where sigma bounds the traffic burstiness and rho the traffic rate. This regulation changes the burstiness and timing of traffic flows, and can be used to decrease delay and reduce buffer requirements in the SoC infrastructure. In this paper, we define and analyze the regulation spectrum, which bounds the upper and lower limits of regulation. Experiments on a Network-on-Chip (NoC) with guaranteed service demonstrate the benefits of regulation We conclude that flow regulation may exert significant positive impact on communication performance and buffer requirements.

  • 3.
    Lu, Zhonghai
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Thid, Rikard
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Millberg, Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Nilsson, Erland
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    NNSE: Nostrum Network-on-Chip Simulation Environment2005Ingår i: Proceedings of Swedish System-on-Chip Conference, Stockholm, Sweden, April 2005., 2005Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    A main challenge for Network-on-Chip (NoC) design isto select a network architecture that suits a particular application.NNSE enables to analyze the performance impactof NoC configuration parameters. It allows one to(1) configure a network with respect to topology, flow controland routing algorithm etc.; (2) configure various regularand application specific traffic patterns; (3) evaluatethe network with the traffic patterns in terms of latency and throughput.

  • 4.
    Millberg, Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Architectural Techniques for Improving Performance in Networks on Chip2011Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    The main aim of this thesis is to propose enhancing techniques for the performance in Networks on Chips. In addition, a concrete proposal for a protocol stack within our NoC platform Nostrum is presented. Nostrum inherently supports both Best Effort as well as Guaranteed Throughput traffic delivery. It employs a deflective routing scheme for best effort traffic delivery that gives a small footprint of the switches in combination with robustness to disturbances in the network. For the traffic delivery with hard guarantees a TDMA based scheme is used. During the transmission process in a NoC several stages are involved. In the papers included, I propose a set of strategies to enhance the performance in several of these stages. The strategies are summarised as follows

    Temporally Disjoint Networks is that a physical network, potentially, can be seen to contain a set of separate networks that a packet can enter dependenton when it enters the physical network. This has the consequence that wecould have different traffic types in the different networks.

    Looped containers provide means to set up virtual circuits in networksusing deflective routing. High priority container packets are inserted intothe network to follow a predefined, closed, route between source and destination.At sender side the packets are loaded and sent to the destination where it is unloaded and sent back.

    Proximity Congestion Awareness reduces the load of the network by diverting packets away from congested areas. It can increase the maximum trafficload by a factor of 20.

    Dual Packet Exit increases the exit bandwidth of the network leading to a50 percent reduction in worst-case latency and a 30 percent reduction inaverage latency as well as a lowered buffer usage.

    Priority Based Forced Requeue prematurely lifts out low priority packetsfrom the network to be requeued. Packets that have not yet entered the network compete with packets inside the network which gives tighter boundson admission with a reduction of worst case latencies by 50 percent.

    Furthermore, Operational Efficiency is proposed as a measure to quantifyhow effective a network is and is defined as the throughput per buffers used in the system. An increase of the injection of packets into the network to increase the system throughput will have a cost associated to it and can be optimised to save energy.

  • 5.
    Millberg, Mikael
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A study of NoC Exit Strategies2007Ingår i: NOCS 2007: First International Symposium on Networks-on-Chip, Proceedings, 2007, s. 217-217Konferensbidrag (Refereegranskat)
    Abstract [en]

    The throughput of a network is limited due to several interacting components. Analysing simulation results made it clear that the component that was worth attacking was the exit bandwidth between the network and the connected resources. The obvious approach is to increase this bandwidth; the benefit is a higher throughput of the network and a significant lowering of the buffer requirements at the entry points of the network this because worst case scenarios now happens at a higher injection rate. The result we present shows significant differences in throughput as well as in average and worst case latency.

  • 6.
    Millberg, Mikael
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Improvements of Performance and Use of Buffers in NoCs using Dual Packet Exit2007Konferensbidrag (Refereegranskat)
  • 7.
    Millberg, Mikael
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Increasing NoC performance and utilisation using a Dual Packet Exit strategy2007Ingår i: DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS / [ed] Kubatova, H, LOS ALAMITOS: IEEE COMPUTER SOC , 2007, s. 511-518Konferensbidrag (Refereegranskat)
    Abstract [en]

    When designing a network the use of buffers is inevitable. Buffers are used at the entry point, inside and at the exits of the network. The usage of these buffers significantly changes the performance of the system. as a whole. In order to enhance the buffer utilisation the concept of letting more than one packet exit the network at every switch each clock cycle is introduced - Dual Packet Exit (DPE). The approach is tried on a 4x4 and a 6x6 mesh. We demonstrate the buffers used in combination with different routing strategies for best effort performance. The result we present shows a 50% reduction in terms of worst case latency and a 30% reduction in terms of average latency as well as an increased throughput both from a system and network perspective. We define the term Operational Efficiency as a measure of the network efficiency and show that it increases by roughly 20 % with the DPE technique.

  • 8.
    Millberg, Mikael
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Priority Based Forced Requeue to Reduce Worst-Case Latencies for Bursty Traffic2009Ingår i: DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, 2009, s. 1070-1075Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper we introduce Priority Based Forced Requeue to decrease worst-case latencies in NoCs offering best effort services. Forced Requeue is to prematurely lift out low priority packets from the network and requeue them outside using priority queues. The first benefit of this approach, applicable to any NoC offering best effort services, is that packets that have not yet entered the network now compete with packets inside the network and hence tighter bounds on admission times can be given. The second benefit - which is more specific to deflective routing as in the Nostrum NoC - is that packet "reshuffling" dramatically reduces the latency inside the network for bursty traffic due to a lowered risk of collisions at the exit of the network. This paper studies the Forced Requeuing on a mesh with varying burst sizes and traffic scenarios. The experimental results show a 50% reduction in worst-case latency from a system perspective thanks to a reshaped latency distribution whilst keeping the average latency the same.

  • 9.
    Millberg, Mikael
    et al.
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Nilsson, Erland
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Thid, Rikard
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip2004Ingår i: Design, Automation And Test In Europe Conference And Exhibition, Vols 1 And 2, Proceedings / [ed] Gielen G, Figueras J, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, s. 890-895Konferensbidrag (Refereegranskat)
    Abstract [en]

    In today's emerging Network-on-Chips, there is a need for different traffic classes with different Quality-of-Service guarantees. Within our NoC architecture Nostrum, we have implemented a service of Guaranteed Bandwidth (GB), and latency, in addition to the already existing service of Best-Effort (BE) packet delivery. The guaranteed bandwidth is accessed via Virtual Circuits (VC). The vcs are implemented using a combination of two concepts that we call 'Looped Containers' and 'Temporally Disjoint Networks'. The Looped Containers are used to guarantee access to the network - independently of the current network load without dropping packets; and the TDNS are used in order to achieve several VCs, plus ordinary BE traffic, in the network. The TDNS are a consequence of the deflective routing policy used, and gives rise to an explicit time-division-multiplexing within the network. To prove our concept an HDL implementation has been synthesised and simulated. The cost in terms of additional hardware needed, as well as additional bandwidth is very low - less than 2 percent in both cases! Simulations showed that ordinary BE traffic is practically unaffected by the VCs.

  • 10.
    Millberg, Mikael
    et al.
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Nilsson, Erland
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Thid, Rikard
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Kumar, S.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    The Nostrum Backbone: a Communication Protocol Stack for Networks Chip2004Ingår i: 17th International Conference On Vlsi Design, Proceedings - Design Methodologies For The Gigascale Era, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, s. 693-696Konferensbidrag (Refereegranskat)
    Abstract [en]

    We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for describing the individual layers' interfaces and service definitions of the layers in the protocol stack is suggested,and used. The concept includes support for best effort traffic packet delivery as well as support for guaranteed bandwidth traffic, using virtual circuits. Furthermore an application to NoC adapter is defined, as part of the Resource to Network Interface, and is used to communicate between the Nostrum protocol stack and the application. An industrial example has been implemented, simulated, and the results justifies the suggested layered approach.

  • 11.
    Nilsson, Erland
    et al.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Millberg, Mikael
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Öberg, Johnny
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Jantsch, Axel
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Load Distribution with the Proximity Congestion Awareness in a Network on Chip2003Ingår i: Design, Automation And Test In Europe Conference And Exhibition, Proceedings , LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2003, s. 1126-1127Konferensbidrag (Refereegranskat)
    Abstract [en]

    In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch. In case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a Proximity Congestion Awareness, PCA, technique, where switches use load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20.

  • 12.
    Pamunuwa, Dinesh
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Millberg, Mikael
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime2004Ingår i: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 38, nr 1, s. 3-17Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

  • 13.
    Thid, Rikard
    et al.
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Millberg, Mikael
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Evaluating NoC communication backbones with simulation2003Ingår i: Proceedings of the 21th NorChip Conference, IEEE conference proceedings, 2003, s. 27-30Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper describes a Network on Chip simulatorthat was developed to evaluate our NoC architecture Nostrum.It is shown how SystemC’s features for communicationrefinement is used to make a highly flexible simulator.The simulator is reconfigurable so that it is possibleto try different NoC platforms and different mappingsof workloads. In addition to the modeling of our Nostrumarchitecture, a bus-based architecture is modeled aswell, and the performance for a simple workload modelis compared.

  • 14. Wolf, Pieter van der
    et al.
    Henriksson, Tomas
    Bruce, Alistair
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Millberg, Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Lu, Zhonghai
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Clouard, Alain
    Definition of Device Level Interface with QoS: Draft Specification2007Rapport (Övrigt vetenskapligt)
    Abstract [en]

    The extensions to standard IP communication interfaces proposed in SPRINT WP3document D3.1 are defined.

    Flow identification signals are added to the DLI signal level interface so transactionscan indicate the services they require. These services are specified as Contracts thatdefine the flow characteristics required for correct operation. These characteristics arethe main input to an analysis method to validate that a SoC design achieves its performance targets.

    DLI-Guard units are defined that enforce Contracts by regulating an IP module’s identified flows. Monitoring of flow characteristics, such as latency, is also optionally provided. A configuration API for DLI-Guards is outlined together with example code toillustrate its use.

    This specification is successfully applied to AMBA AXI, the prime example DLI

1 - 14 av 14
RefereraExporteraLänk till träfflistan
Permanent länk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf