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  • 1.
    Kargarrazi, Saleh
    et al.
    Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Saggini, Stefano
    DIEGM Univ Udine, I-33100 Udine, Italy..
    Senesky, Debbie
    Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    500 degrees C SiC PWM Integrated Circuit2019In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 34, no 3, p. 1997-2001Article in journal (Refereed)
    Abstract [en]

    This letter reports on a high-temperature pulsewidth modulation (PWM) integrated circuit microfabricated in 4H-SiC bipolar process technology that features an on-chip integrated ramp generator. The circuit has been characterized and shown to be operational in a wide temperature range from 25 to 500 degrees C. The operating frequency of the PWM varies in the range of 160 to 210 kHz and the duty cycle varies less than 17% over the entire temperature range. The proposed PWM is suggested to efficiently and reliably control power converters in extreme environments.

  • 2.
    Shakir, Muhammad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hou, Shuoben
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Metreveli, Alex
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rashid, Arman Ur
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Mantooth, Homer Alan
    Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA..
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    555-Timer and Comparators Operational at 500 degrees C2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 9, p. 3734-3739Article in journal (Refereed)
    Abstract [en]

    This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 degrees C-500 degrees C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation.

  • 3.
    Shakir, Muhammad
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Metreveli, Alexy
    Ur Rashid, Arman
    Mantooth, Alan
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    555-Timer IC Operational at 500 °C2019In: Bipolar SiC 555-timer IC, High Temperature ICs, TTL Comparator, SiC Integrated CircuitsArticle in journal (Other academic)
    Abstract [en]

    This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. The paper demonstrates the 555-timer ICs characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 to 500°C. Nonmonotonictemperature dependence was observed for the 555-timer IC frequency, rise-time, fall-time, and power dissipation.

  • 4.
    Li, Yuchao
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Automatic Control. KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.).
    Feng, Lei
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.).
    Wang, Yu
    KTH, School of Electrical Engineering and Computer Science (EECS), Automatic Control. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    A cascade control approach to active suspension using pneumatic actuators2019In: Asian journal of control, ISSN 1561-8625, E-ISSN 1561-8625, p. 1-19Article in journal (Refereed)
    Abstract [en]

    Operators of forest machinery suffer from intensive whole body vibrations, which are big threats to their health. Therefore, it is important to investigate effective seat undercarriages and control methods for vibration reduction. This paper addresses the control problem of a novel seat undercarriage with pneu-matic actuators customized for forest machinery. A two-layer cascade controlstructure is developed, where the top layer consists of a group of proportional controllers to regulate the position of pneumatic actuators and the bottom layeris a sliding mode controller for force and stiffness tracking. The advantage ofthe sliding mode control is to achieve robust control performance with coarse system models. The paper demonstrates that the proposed control structure is better than a traditional PID controller. The robust stability of the sliding mode controller is proved by the Lyapunov's method. Experiments show its capability of reducing at least 20% amplitude of seat vibrations from 0.5 to 1 Hz.

  • 5.
    Aslam, Bilal
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Azam, Muhammad A.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Loo, Jonathan
    Middlesex Univ, Sch Engn & Informat Sci, Dept Comp Sci, London, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A high capacity tunable retransmission type frequency coded chipless radio frequency identification system2019In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 29, no 9, article id e21855Article in journal (Refereed)
    Abstract [en]

    This article presents a 12-bit frequency coded chipless RFID system in the frequency range of 3 to 6 GHz. The system consists of a fully printable chipless tag and a pair of high-gain reader antennas. The tag also incorporates its own antennas to improve the read range. Information is encoded into frequency spectrum using a multi-resonant circuit. The circuit consists of multiple microstrip U and L-shaped open stub resonators patterned in a unique configuration. The proposed configuration aids in capturing more data in a reduced space as well as tunable frequency operation. Tag and reader antennas utilize techniques such as stepped impedance feeding line, defective partial ground plane, and stair-step patch structure to achieve wide-band impedance bandwidth in miniature size. The results of the wireless measurements in the non-anechoic environment show that the proposed system has a reading range of more than 20 cm. The presented system possesses great potential for low-cost short-range inventory tracking.

  • 6.
    Aslam, Bilal
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan..
    Kashif, Muhammad
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.;Beijing Univ Aeronaut & Astronaut, Beijing, Peoples R China..
    Azam, Muhammad Awais
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan..
    Amin, Yasar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.
    Loo, Jonathan
    Univ West London, Sch Comp & Commun Engn, Dept Comp Sci, London, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Turku, Dept Informat Technol, TUCS, Turku, Finland..
    A low profile miniature RFID tag antenna dedicated to IoT applications2019In: Electromagnetics, ISSN 0272-6343, E-ISSN 1532-527X, Vol. 39, no 6, p. 393-406Article in journal (Refereed)
    Abstract [en]

    RFID tag antennas with stable performance on the diverse electromagnetic mounting platforms are an integral part of the ubiquitous RFID systems. This research article presents a novel tag antenna design that facilitates the said objective. The proposed antenna consists of a modified H-shaped slot structure that ensures considerable robustness from the application environment through confining the surface current density within the antenna structure. The antenna offers a tunable bandwidth of 40 MHz within the microwave band of (2.4-2.5) GHz. The proposed tag antenna exhibits excellent response on metallic platforms of different sizes and thicknesses with an effective gain of almost four times of that in free space. Furthermore, the designed tag antenna performs adequately well on low-medium permittivity dielectrics (glass, paper, and plastic) and RF absorbers (water). The free space and on-metal performance of the proposed tag antenna are verified by testing a prototype realized on the FR4 substrate.

  • 7.
    Khan, Tayyaba
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, Taxila 47050, Pakistan..
    Rahman, MuhibUr
    Polytech Montreal, Dept Elect Engn, Montreal, PQ H3T 1J4, Canada..
    Akram, Adeel
    Univ Engn & Technol, Dept Telecommun Engn, Taxila 47050, Pakistan..
    Amin, Yasar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Engn & Technol, Dept Telecommun Engn, Taxila 47050, Pakistan..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    A Low-Cost CPW-Fed Multiband Frequency Reconfigurable Antenna for Wireless Applications2019In: ELECTRONICS, ISSN 2079-9292, Vol. 8, no 8, article id 900Article in journal (Refereed)
    Abstract [en]

    A novel, cedar-shaped, coplanar waveguide-fed frequency reconfigurable antenna is proposed. The presented antenna uses low-cost FR4 substrate with a thickness of 1.6 mm. Four PIN diodes are inserted on the antenna surface to variate the current distribution and alter the resonant frequencies with different combinations of switches. The proposed antenna is fabricated and measured for all states, and a good agreement is seen between measured and simulated results. This antenna resonates within the range of 2 GHz to 10 GHz, covering the major wireless applications of aviation service, wireless local area network (WLAN), worldwide interoperability for microwave access (WiMAX), long distance radio telecommunications, and X-band satellite communication. The proposed antenna works resourcefully with reasonable gain, significant bandwidth, directivity, and reflection coefficient. The proposed multiband reconfigurable antenna will pave the way for future wireless communications including WLAN, WiMAX, and possibly fifth-generation (5G) communication.

  • 8.
    Shakir, Muhammad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    Hou, Shuoben
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A Monolithic 500 °C D-flip flop Realized in Bipolar 4H-SiC TTL technology2019Conference paper (Other academic)
  • 9. Naqvi, S. I.
    et al.
    Khan, A.
    Azam, M. A.
    Amin, Y.
    Loo, J.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A planar flexible quad-band antenna for WLAN/WiMAX/LTE applications2019In: 2019 2nd International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2019, Institute of Electrical and Electronics Engineers Inc. , 2019Conference paper (Refereed)
    Abstract [en]

    In this work a quad-band, planar, low-profile and compact antenna envisioned for incorporation into portable wireless devices is presented. The antenna is modeled on flexible Rogers RT/Duroid 5880 substrate of 0.127mm thickness. The proposed antenna structure consists of symmetrically placed F-shaped slits and a curved rectangular shaped ground plane with a CPW feed line. The four bands obtained for the radiator operates at the resonant frequencies 2.8, 3.9, 5.45 and 6.2 GHz with impedance bandwidths of 14%, 14.5%, 5.7%, and 5% respectively. Thus the proposed antenna supports WLAN, LTE, WiMAX, and C-band applications. The peak gain achieved for the antenna is 3.4 dB.

  • 10.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Zumbro, John E.
    University of Arkansas.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)
    Abstract [en]

    This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

  • 11. Mohamed, S. A. S.
    et al.
    Haghbayan, M. -H
    Westerlund, T.
    Heikkonen, J.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Department of Future Technologies, University of Turku (UTU), Turku, 20500, Finland.
    Plosila, J.
    A Survey on Odometry for Autonomous Navigation Systems2019In: IEEE Access, E-ISSN 2169-3536, Vol. 7, p. 97466-97486, article id 8764393Article in journal (Refereed)
    Abstract [en]

    The development of a navigation system is one of the major challenges in building a fully autonomous platform. Full autonomy requires a dependable navigation capability not only in a perfect situation with clear GPS signals but also in situations, where the GPS is unreliable. Therefore, self-contained odometry systems have attracted much attention recently. This paper provides a general and comprehensive overview of the state of the art in the field of self-contained, i.e., GPS denied odometry systems, and identifies the out-coming challenges that demand further research in future. Self-contained odometry methods are categorized into five main types, i.e., wheel, inertial, laser, radar, and visual, where such categorization is based on the type of the sensor data being used for the odometry. Most of the research in the field is focused on analyzing the sensor data exhaustively or partially to extract the vehicle pose. Different combinations and fusions of sensor data in a tightly/loosely coupled manner and with filtering or optimizing fusion method have been investigated. We analyze the advantages and weaknesses of each approach in terms of different evaluation metrics, such as performance, response time, energy efficiency, and accuracy, which can be a useful guideline for researchers and engineers in the field. In the end, some future research challenges in the field are discussed.

  • 12.
    Qin, Zidi
    et al.
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China..
    Zhu, Di
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China..
    Zhu, Xingwei
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China..
    Chen, Xuan
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China..
    Shi, Yinghuan
    Nanjing Univ, State Key Lab Novel Software Technol, Nanjing 210023, Jiangsu, Peoples R China..
    Gao, Yang
    Nanjing Univ, State Key Lab Novel Software Technol, Nanjing 210023, Jiangsu, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Shen, Qinghong
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China..
    Li, Li
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China..
    Pan, Hongbing
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China..
    Accelerating Deep Neural Networks by Combining Block-Circulant Matrices and Low-Precision Weights2019In: ELECTRONICS, ISSN 2079-9292, Vol. 8, no 1, article id 78Article in journal (Refereed)
    Abstract [en]

    As a key ingredient of deep neural networks (DNNs), fully-connected (FC) layers are widely used in various artificial intelligence applications. However, there are many parameters in FC layers, so the efficient process of FC layers is restricted by memory bandwidth. In this paper, we propose a compression approach combining block-circulant matrix-based weight representation and power-of-two quantization. Applying block-circulant matrices in FC layers can reduce the storage complexity from <mml:semantics>O(k2)</mml:semantics> to <mml:semantics>O(k)</mml:semantics>. By quantizing the weights into integer powers of two, the multiplications in the reference can be replaced by shift and add operations. The memory usages of models for MNIST, CIFAR-10 and ImageNet can be compressed by <mml:semantics>171x</mml:semantics>, <mml:semantics>2731x</mml:semantics> and <mml:semantics>128x</mml:semantics> with minimal accuracy loss, respectively. A configurable parallel hardware architecture is then proposed for processing the compressed FC layers efficiently. Without multipliers, a block matrix-vector multiplication module (B-MV) is used as the computing kernel. The architecture is flexible to support FC layers of various compression ratios with small footprint. Simultaneously, the memory access can be significantly reduced by using the configurable architecture. Measurement results show that the accelerator has a processing power of 409.6 GOPS, and achieves 5.3 TOPS/W energy efficiency at 800 MHz.

  • 13.
    Chen, Qinyu
    et al.
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Fu, Yuxiang
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Song, Wenqing
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Cheng, Kaifeng
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zhang, Chuan
    Southeast Univ, Natl Mobile Commun Res Lab, Nanjing 210096, Jiangsu, Peoples R China..
    Li, Li
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    An Efficient Streaming Accelerator for Low Bit-Width Convolutional Neural Networks2019In: ELECTRONICS, ISSN 2079-9292, Vol. 8, no 4, article id 371Article in journal (Refereed)
    Abstract [en]

    Convolutional Neural Networks (CNNs) have been widely applied in various fields, such as image recognition, speech processing, as well as in many big-data analysis tasks. However, their large size and intensive computation hinder their deployment in hardware, especially on the embedded systems with stringent latency, power, and area requirements. To address this issue, low bit-width CNNs are proposed as a highly competitive candidate. In this paper, we propose an efficient, scalable accelerator for low bit-width CNNs based on a parallel streaming architecture. With a novel coarse grain task partitioning (CGTP) strategy, the proposed accelerator with heterogeneous computing units, supporting multi-pattern dataflows, can nearly double the throughput for various CNN models on average. Besides, a hardware-friendly algorithm is proposed to simplify the activation and quantification process, which can reduce the power dissipation and area overhead. Based on the optimized algorithm, an efficient reconfigurable three-stage activation-quantification-pooling (AQP) unit with the low power staged blocking strategy is developed, which can process activation, quantification, and max-pooling operations simultaneously. Moreover, an interleaving memory scheduling scheme is proposed to well support the streaming architecture. The accelerator is implemented with TSMC 40 nm technology with a core size of . It can achieve TOPS/W energy efficiency and area efficiency at 100.1mW, which makes it a promising design for the embedded devices.

  • 14. Tian, K.
    et al.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Qi, J.
    Ma, S.
    Fei, X.
    Zhang, A.
    Liu, W.
    An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 5, p. 2307-2313, article id 8681267Article in journal (Refereed)
    Abstract [en]

    In this paper, an improved 4H-SiC U-shaped trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (R ON ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (V BR ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM = V BR 2 /R ON ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (T ON ) and turn-off time (T OFF ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (E SW ). © 2019 IEEE.

  • 15. Tian, Kai
    et al.
    Hallén, Anders
    KTH, Superseded Departments (pre-2005), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Qi, Jinwei
    Ma, Shenhui
    Fei, Xinxing
    Zhang, Anping
    Liu, Weihua
    An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 5, p. 2307-2313Article in journal (Refereed)
    Abstract [en]

    In this paper, an improved 4H-SiC U-shaped trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (R-ON) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (V-BR). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM = V-BR(2)/R-ON) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (T-ON) and turn-off time (T-OFF) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (E-SW).

  • 16.
    Naqvi, Syeda, I
    et al.
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Naqvi, Aqeel H.
    Chung Ang Univ, Sch Elect & Elect Engn, Seoul 06974, South Korea..
    Arshad, Farzana
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Riaz, Muhammad A.
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Azam, Muhammad A.
    Univ Engn & Technol, Dept Comp Engn, Taxila 47050, Pakistan..
    Khan, Mansoor S.
    COMSATS Univ Islamabad, Math Dept, Islamabad 45550, Pakistan..
    Amin, Yasar
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Loo, Jonathan
    Univ West London, Sch Comp & Engn, London W5 5RF, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Turku, TUCS, Dept Informat Technol, FIN-20520 Turku, Finland..
    An Integrated Antenna System for 4G and Millimeter-Wave 5G Future Handheld Devices2019In: IEEE Access, E-ISSN 2169-3536, Vol. 7, p. 116555-116566Article in journal (Refereed)
    Abstract [en]

    In this work, an integrated antenna system with Defected Ground Structure (DGS) is presented for Fourth Generation (4G) and millimeter (mm)-wave Fifth Generation (5G) wireless applications and handheld devices. The proposed design with overall dimensions of 110 mm x 75 mm is modeled on 0.508 mm thick Rogers RT/Duroid 5880 substrate. Radiating structure consists of antenna arrays excited by the T-shape 1 x 2 power divider/combiner. Dual bands for 4G centered at 3.8 GHz and 5.5 GHz are attained, whereas the 10-dB impedance bandwidth of 24.4 - 29.3 GHz is achieved for the 5G antenna array. In addition, a peak gain of 5.41 dBi is demonstrated across the operating bandwidth of the 4G antenna array. Similarly, for the 5G mm-wave configuration the attained peak gain is 10.29 dBi. Moreover, significant isolation is obtained between the two antenna modules ensuring efficient dual-frequency band operation using a single integrated solution. To endorse the concept, antenna prototype is fabricated and far-field measurements are procured. Simulated and measured results exhibit coherence. Also the proposed design is investigated for the beam steering capability of the mm-wave 5G antenna array using CST(R)MWS(R). The demonstrated structure offers various advantages including compactness, wide bandwidth, high gain, and planar configuration. Hence, the attained radiation characteristics prove the suitability of the proposed design for the current and future wireless handheld devices.

  • 17.
    Wang, Boqian
    et al.
    KTH. Natl Univ Def Technol, Changsha, Hunan, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Chen, Shenggang
    Natl Univ Def Technol, Changsha, Hunan, Peoples R China..
    ANN Based Admission Control for On-Chip Networks2019In: PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), ASSOC COMPUTING MACHINERY , 2019Conference paper (Refereed)
    Abstract [en]

    We propose an admission control method in Network-on-Chip (NoC) with a centralized Artificial Neural Network (ANN) admission controller, which can improve system performance by predicting the most appropriate injection rate of each node via the network performance information. In the online control process, a data preprocessing unit is applied to simplify the ANN architecture and make the prediction results more accurate. Based on the preprocessed information, the ANN predictor determines the control strategy and broadcasts it to each node where the admission control will be applied. Compared to the previous work, our method builds up a high-fidelity model between the network status and the injection rate regulation. The full-system simulation results show that our proposed method can enhance application performance by 17.8% on average and up to 23.8%.

  • 18.
    Zhang, Wenhui
    et al.
    Huazhong Univ Sci & Technol, Sch Comp Sci & Technol, Wuhan Natl Lab Optoelect, Key Lab Informat Storage Syst,Minist Educ, Wuhan 430074, Hubei, Peoples R China..
    Cao, Qiang
    Huazhong Univ Sci & Technol, Sch Comp Sci & Technol, Wuhan Natl Lab Optoelect, Key Lab Informat Storage Syst,Minist Educ, Wuhan 430074, Hubei, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Bit-Flipping Schemes Upon MLC Flash: Investigation, Implementation, and Evaluation2019In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 38, no 4, p. 780-784Article in journal (Refereed)
    Abstract [en]

    Multilevel cell (MLC) stales with lower threshold voltage endure less cell damage, lower retention error, and less current consumption. Based on these characteristics, it is opportunistic to strengthen MLC flash by introducing hit-flipping that reshapes state proportions on MLC pages. In this paper. we present a holistic study of bit-flipping schemes upon MLC flash in theory and practice. Specifically, we systematically investigate effective bit-flipping schemes and propose four new schemes on manipulating MLC states. We further design a generic implementation framework, named MLC bit-flipping framework, to implement bit-flipping schemes within solid state drives controllers, nicely integrating with existing system-level optimizations to further improve overall performance. The experimental results demonstrate that our proposed bit-flipping schemes standalone can reduce up to 28% cell damages and 53% retention errors. Our circuit-level simulation manifests that the bit-flipping latency on a page is less than 4 mu s when using 8K logic gates.

  • 19.
    Shabbir, Ghulam
    et al.
    Univ Engn & Technol Taxila, Taxila 47050, Pakistan..
    Ahmad, Jamil
    Univ Engn & Technol Taxila, Taxila 47050, Pakistan..
    Raza, Waseem
    Univ Lahore, Lahore 54000, Pakistan..
    Amin, Yasar
    Univ Engn & Technol Taxila, Taxila 47050, Pakistan..
    Akram, Adeel
    Univ Engn & Technol Taxila, Taxila 47050, Pakistan..
    Loo, Jonathan
    Univ West London, London W5 5RF, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Buffer-Aided Successive Relay Selection Scheme for Energy Harvesting IoT Networks2019In: IEEE Access, E-ISSN 2169-3536, Vol. 7, p. 36246-36258Article in journal (Refereed)
    Abstract [en]

    In this paper, we analyze the impact of buffer-aided full-duplex successive relay selection schemes with energy harvesting capability of relay nodes in amplifying and forward (AF) and decode and forward (DF) relaying environments for the Internet of Things networks. We propose to select a relay pair based on the energy harvested and signal strength at relay and destination to receive and transmit in the same time slot, respectively. Contrary to the previous relay pair selection schemes which are based on the signal strength only and cause the relay overuse problem, the proposed scheme ensures the balanced use of energy of relay nodes. The proposed relay selection scheme is implemented with the time switching (TS) and power splitting (PS)-based energy harvesting models in AF and DF relaying environments separately. Furthermore, we derive the closed-form expression of the outage probability and average throughput for both the TS and PS approaches in the DF and AF relaying modes. We compare the proposed relay selection scheme with the S-MMRS scheme and prove that the proposed scheme significantly reduces the outage probability and improves the average throughput. Furthermore, the analytical findings are reinforced with the extensive Monte Carlo simulations.

  • 20.
    Reuterskiöld-Hedlund, Carl
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Liu, Shih-Chia
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Zhao, Deyin
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Zhou, Weidong
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Hammar, Mattias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Buried-Tunnel Junction Current Injection for InP-Based Nanomembrane Photonic Crystal Surface Emitting Lasers on Silicon2019In: Physica Status Solidi (a) applications and materials science, ISSN 1862-6300, E-ISSN 1862-6319, article id 1900527Article in journal (Refereed)
    Abstract [en]

    Herein, the design, metal-organic vapor-phase epitaxial growth, fabrication, and characterization of buried-tunnel junction (BTJ) current injection structures for InP/Si hybrid nanomembrane photonic crystal surface emitting lasers (PCSELs) are reported. Corresponding BTJ-light-emitting diodes on InP substrate show low series resistance and uniform carrier injection over square-shaped device areas with side length ranging from 15 up to 250 mu m, whereas BTJ-PCSEL structures with similar current injection configuration fabricated on photonic-crystal silicon-on-insulator substrate using transfer print technology show significant linewidth narrowing at low current density.

  • 21.
    Ivanisevic, Nikola
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Implantable neural interfaces are microelectronic systems, which have the potential to enable a wide range of applications, such as diagnosis and treatment of neurological disorders. These applications depend on neural interfaces to accurately record electrical activity from the surface of the brain, referred to as electrocorticography (ECoG), and provide controlled electrical stimulation as feedback. Since the electrical activity in the brain is caused by ionic currents in neurons, the bridge between living tissue and inorganic electronics is achieved via microelectrode arrays. The conversion of the ionic charge into freely moving electrons creates a built-in electrode potential that is several orders of magnitude larger than the ECoG signal, which increases the dynamic range, resolution, and power consumption requirements of neural interfaces. Also, the small surface area of microelectrodes implies a high-impedance contact, which can attenuate the ECoG signal. Moreover, the applied electrical stimulation can also interfere with the recording and ultimately cause irreversible damages to the electrodes or change their impedance. This thesis is devoted to resolving the challenges of high-resolution recording and monitoring the electrode impedance in implantable neural interfaces.

    The first part of this thesis investigates the state-of-the-art neural interfaces for ECoG and identifies their limitations. As a result of the investigation, a high-resolution ADC is proposed and implemented based on a ΔΣ modulator. In order to enhance performance, dynamic biasing and area-efficient switched-capacitor circuits were proposed. The ΔΣ modulator is combined with the analog front-end to provide a complete readout solution for high-resolution ECoG recording. The corresponding chip prototype was fabricated in a 180 nm CMOS process, and the measurement results showed a 14-ENOB over a 300-Hz bandwidth while dissipating 54-μW.

    The second part of this thesis expands upon the well-known methods for impedance measurements and proposes an alternative digital method for monitoring the electrode-tissue interface impedance. The proposed method is based on the system identification technique from adaptive digital filtering, and it is compatible with existing circuitry for neural stimulation. The method is simple to implement and performs wide-band measurements. The system identification was first verified through behavioral simulations and then tested with a board-level prototype in order to validate the functionality under real conditions. The measurement results showed successful identification of the electrode-electrolyte and electrode-skin impedance magnitudes.

  • 22.
    Queralta, Jorge Pena
    et al.
    Univ Turku, Dept Future Technol, Turku, Finland..
    Gia, Tuan Nguyen
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Westerlund, Tomi
    Univ Turku, Dept Future Technol, Turku, Finland..
    Collaborative Mapping with IoE-based Heterogeneous Vehicles for Enhanced Situational Awareness2019In: 2019 IEEE SENSORS APPLICATIONS SYMPOSIUM (SAS), IEEE , 2019Conference paper (Refereed)
    Abstract [en]

    The development of autonomous vehicles or advanced driving assistance platforms has had a great leap forward to get closer to human daily life over the last decade. Nevertheless, it is still challenging to achieve an efficient and fully autonomous vehicle or driving assistance platform due to many strict requirements and complex situations or unknown environments. One of the main remaining challenges is a robust situation awareness in autonomous vehicles when the environment is unknoen. An autonomous system with a poor situation awareness due to low quantity or quality of data may directly or indirectly cause serious consequences. For instance, a person's life might be at risk due to a delay caused by a long or incorrect path planning of an autonomous ambulance. Internet of Everything (IoE) is currently becoming a prominent technology for many applications such as automation. In this paper, we propose an IoE-based architecture consisting of a heterogeneous team of cars and drones for enhancing situational awareness in autonomous cars, especially when dealing with critical cases of natural disasters. In particular, we show how an autonomous car can plan in advance the possible paths to a given destination, and send orders to other vehicles. These, in turn, perform terrain reconnaissance for avoiding obstacles and dealing with difficult situations. Together with a map merging algorithm deployed into the team autonomous vehicles, the proposed architecture can help to save traveling distance and time significantly in case of complex scenarios.

  • 23.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zahedinejad, Mohammad
    Department of Physics, University of Gothenburg.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, University of Gothenburg.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators2019In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed)
    Abstract [en]

    Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

  • 24.
    Fu, Yuxiang
    et al.
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Chen, Qinyu
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    He, Guoqiang
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Chen, Kai
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zhang, Chuan
    Southeast Univ, Natl Mobile Commun Res Lab, Nanjing, Jiangsu, Peoples R China..
    Li, Li
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs2019In: 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2019Conference paper (Refereed)
    Abstract [en]

    The combination of Network-on-Chips (NoCs) and 3D IC technology, 3D NoCs, has been proven to be able to achieve a great improvement in both network performance and power consumption compared to 2D NoCs. In the traditional 3D NoC, all routers are vertically connected. Due to the large overhead of Through-Silicon-Via (TSV, e.g., low fabrication yield and the occupied silicon area), the partially connected 3D NoC has emerged. The assignment method determines the traffic loads of the vertical links (elevators), thus has a great impact on 3D-NoCs' performance. In this paper, we propose a congestion-aware dynamic elevator assignment (CDA) scheme, which takes both the distance factors and network congestion information into account. Experiments show that the performance of the proposed CDA scheme is improved by 67% to 87% compared to the random selection scheme, 8% to 25% compared to SelByDis-1, and 13% to 18% compared to SelByDis-2.

  • 25.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Näslund, Oskar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Degen, Bernhard
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Gawell, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Yu, Yang
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction2019In: 2019 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW), IEEE conference proceedings, 2019, p. 264-271-Conference paper (Refereed)
    Abstract [en]

    Adversarial machine learning is an emerging threat to security of Machine Learning (ML)-based systems. However, we can potentially use it as a weapon against ML-based attacks. In this paper, we focus on protecting Physical Unclonable Functions (PUFs) against ML-based modeling attacks. PUFs are an important cryptographic primitive for secret key generation and challenge-response authentication. However, none of the existing PUF constructions are both ML attack resistant and sufficiently lightweight to fit low-end embedded devices. We present a lightweight PUF construction, CRC-PUF, in which input challenges are de-synchronized from output responses to make a PUF model difficult to learn. The de-synchronization is done by an input transformation based on a Cyclic Redundancy Check (CRC). By changing the CRC generator polynomial for each new response, we assure that success probability of recovering the transformed

  • 26.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Kelati, Amleset
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Nkonoki, Emma
    Kondoro, Aron
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rwegasira, Diana
    KTH.
    Ben Dhaou, Imed
    Taajamaa, Ville
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Creation of CERID: Challenge, Education, Research, Innovation, and Deployment: in the context of smart MicroGrid2019Conference paper (Refereed)
    Abstract [en]

    The iGrid project deals with the design and implementation of a solar-powered smart microgrid to supply electric power to small rural communities. In this paper, we discuss the roadmap of the iGrid project, which forms by merging the roadmaps of KIC (knowledge and Innovation Community) and CDE (Challenge-Driven Education). We introduce and explain a five-gear chain as Challenge, Education, Research, Innovation, and Deployment, called CERID, to reach the main goals of this project. We investigate the full chain in the iGrid project, which is established between KTH Royal Institute of Technology (Sweden) and University of Dar es Salam (Tanzania). We introduce the key stakeholders and explain how CERID goals can be accomplished in higher educations and through scientific research. Challenges are discussed, some innovative ideas are introduced and deployment solutions are recommended.

  • 27.
    Azarov, Alexander
    et al.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.;Natl Ctr Nucl Res, A Soltana 7, PL-05400 Otwock, Poland..
    Aarseth, Bjorn L.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Vines, Lasse
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Monakhov, Edouard
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Kuznetsov, Andrej
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Defect annealing kinetics in ZnO implanted with Zn substituting elements: Zn interstitials and Li redistribution2019In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 125, no 7, article id 075703Article in journal (Refereed)
    Abstract [en]

    It is known that the behavior of residual Li in ion implanted ZnO depends on the preferential localization of the implants, in particular, forming characteristic Li depleted or Li pile-up regions for Zn or O sublattice occupation of the implants due to the corresponding excess generation of Zn and O interstitials in accordance with the so-called "+1 model." However, the present study reveals that conditions for the radiation damage annealing introduce additional complexity into the interpretation of the Li redistribution trends. Specifically, four implants residing predominantly in the Zn-sublattice, but exhibiting different lattice recovery routes, were considered. Analyzing Li redistribution trends in these samples, it is clearly shown that Li behavior depends on the defect annealing kinetics which is a strong function of the implanted fluence and ion species. Thus, Li depleted and Li pile-up regions (or even combinations of the two) were observed and correlated with the defect evolution in the samples. It is discussed how the observed Li redistribution trends can be used for better understanding a thermal evolution of point defects in ZnO and, in particular, energetics and migration properties of Zn interstitials.

  • 28.
    Wang, Junshi
    et al.
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China.;Beijing Zhaoxin Elect Technol Co Ltd, Beijing 100084, Peoples R China..
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Huang, Letian
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Xie, Xuan
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Li, Qiang
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Li, Guangjun
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Jantsch, Axel
    Tech Univ Wien, A-1040 Vienna, Austria..
    Efficient Design-for-Test Approach for Networks-on-Chip2019In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 68, no 2, p. 198-213Article in journal (Refereed)
    Abstract [en]

    To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BISTcauses significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.

  • 29.
    Chen, Xiaowen
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Efficient Memory Access and Synchronization in NoC-based Many-core Processors2019Doctoral thesis, monograph (Other academic)
    Abstract [en]

    In NoC-based many-core processors, memory subsystem and synchronization mechanism are always the two important design aspects, since mining parallelism and pursuing higher performance require not only optimized memory management but also efficient synchronization mechanism. Therefore, we are motivated to research on efficient memory access and synchronization in three topics, namely, efficient on-chip memory organization, fair shared memory access, and efficient many-core synchronization.

    One major way of optimizing the memory performance is constructing a suitable and efficient memory organization. A distributed memory organization is more suitable to NoC-based many-core processors, since it features good scalability. We envision that it is essential to support Distributed Shared Memory (DSM) because of the huge amount of legacy code and easy programming. Therefore, we first adopt the microcoded approach to address DSM issues, aiming for hardware performance but maintaining the flexibility of programs. Second, we further optimize the DSM performance by reducing the virtual-to-physical address translation overhead. In addition to the general-purpose memory organization such as DSM, there exists special-purpose memory organization to optimize the performance of application-specific memory access. We choose Fast Fourier Transform (FFT) as the target application, and propose a multi-bank data memory specialized for FFT computation.

    In 3D NoC-based many-core processors, because processor cores and memories reside in different locations (center, corner, edge, etc.) of different layers, memory accesses behave differently due to their different communication distances. As the network size increases, the communication distance difference of memory accesses becomes larger, resulting in unfair memory access performance among different processor cores. This unfair memory access phenomenon may lead to high latencies of some memory accesses, thus negatively affecting the overall system performance. Therefore, we are motivated to study on-chip memory and DRAM access fairness in 3D NoC-based many-core processors through narrowing the round-trip latency difference of memory accesses as well as reducing the maximum memory access latency.

    Barrier synchronization is used to synchronize the execution of parallel processor cores. Conventional barrier synchronization approaches such as master-slave, all-to-all, tree-based, and butterfly are algorithm oriented. As many processor cores are networked on a single chip, contended synchronization requests may cause large performance penalty. Motivated by this, different from the algorithm-based approaches, we choose another direction (i.e., exploiting efficient communication) to address the barrier synchronization problem. We propose cooperative communication as a means and combine it with the master-slave algorithm and the all-to-all algorithm to achieve efficient many-core barrier synchronization. Besides, a multi-FPGA implementation case study of fast many-core barrier synchronization is conducted.

  • 30. Fakih, M.
    et al.
    Grüttner, K.
    Schreiner, S.
    Seyyedi, R.
    Azkarate-Askasua, M.
    Onaindia, P.
    Poggi, T.
    Romero, N. G.
    Gonzalez, E. Q.
    Sundström, T.
    Frasquet, S. P.
    Balbastre, P.
    Mohammadat, T.
    Öberg, Johnny
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Bebawy, Y.
    Obermaisser, R.
    Maleki, A.
    Lenz, A.
    Graham, D.
    Experimental evaluation of SAFEPOWER architecture for safe and power-efficient mixed-criticality systems2019In: Journal of Low Power Electronics and Applications, Vol. 9, no 1, article id 12Article in journal (Refereed)
    Abstract [en]

    With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication. 

  • 31.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Fact or Fiction? – Citation Categories and their Use Cases in Thesis Bibliographies at KTH2019In: This work was presented at KTH Scholarship of teaching and learning (SoTL) March 29, 2019, 2019Conference paper (Refereed)
    Abstract [en]

    Background and purpose

     

    Since the first level (bachelor) thesis was introduced at KTH in the degree programs students are exposed to scientific writing at an early stage in their education. A key element of scientific writing is an efficient use of citations i.e. references to published work in the area. From a teacher perspective many first level thesis reports showed poor quality in this respect. In order to be able to study this observation, from a quantitative or empirical point of view, development a well-defined scientific method was highly motivated.

     

    Work done

     

    In my work a method, based on so called content analysis, was proposed and used to study student behavior in first level thesis reports, regarding their use of citations. The objective was to look at categories of in-text citations and to find evidence, supporting a hypothesis, that student use of citations show distinct patterns. These patterns could reflect that they rely too much on facts and show too little evidence of learning, regarding synthesis from reliable and valid scientific sources, in their respective technical domain. The citation category method, proposed by me, starts from an a priori set of “use cases” or “in-text citation categories”. Based on these categories all citations could be coded for further statistical analysis.

     

     

    Observations

     

    The empirical results were based on nine first level (BS) reports. These were selected to represent programs at the different schools at KTH. A full search was done in DiVA for the time span June 2013- June 2015 and the selected reports are a random sampling of the 1300 reports, found in the in the database.

    The results clearly points towards a use of citations, where “presenting a fact” is emphasized over most other use cases. The use of a citation to “introduce or discuss contrasting views” or “in support of an argument” is seldom observed. On the other hand, the bulk of the in-text citations are used to shape the background survey. In extreme cases the whole thesis structure is based on the ideas, found in the studied literature. Finally, it is found that the reliability and validity of sources is sometimes commented upon by the thesis authors.

     

    Take-home message

     

    As students are exposed to scientific writing for the first time they display a pattern of using citations mainly to present facts. They have not yet learned that citations have many other valid use cases such as introducing or discussing contrasting views. Students need training and exposure to scientific writing in order to develop and broaden their use of citations. A natural extension of my study would be at the second level since these students have more training in scientific writing.

     

     

     

  • 32.
    Marranghello, Felipe
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Callegaro, V.
    Reis, A. I.
    Ribas, R. P.
    Four-level forms for memristive material implication logic2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 5, p. 1228-1232, article id 8621037Article in journal (Refereed)
    Abstract [en]

    This brief proposes the use of four-level forms in the memristive material implication (M-IMP) logic. M-IMP is a promising approach to perform stateful logic in memristive nonvolatile memories. In such a design technique, a given Boolean function is evaluated as a sequence of instructions, making logic synthesis methods necessary to attain the shortest sequence. In comparison to previous work, experimental results have shown an average reduction of 40% when evaluating the tradeoff between the numbers of instructions and memristive devices.

  • 33.
    Delekta, Szymon Sollami
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Adolfsson, Karin H.
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Fibre- and Polymer Technology.
    Benyahia Erdal, Nejla
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Fibre- and Polymer Technology.
    Hakkarainen, Minna
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Fibre- and Polymer Technology, Polymer Technology.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Li, Jiantong
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Fully inkjet printed ultrathin microsupercapacitors based on graphene electrodes and a nano-graphene oxide electrolyte2019In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 11, no 21, p. 10172-10177Article in journal (Refereed)
    Abstract [en]

    The advance of miniaturized and low-power electronics has a striking impact on the development of energy storage devices with constantly tougher constraints in terms of form factor and performance. Microsupercapacitors (MSCs) are considered a potential solution to this problem, thanks to their compact device structure. Great efforts have been made to maximize their performance with new materials like graphene and to minimize their production cost with scalable fabrication processes. In this regard, we developed a full inkjet printing process for the production of all-graphene microsupercapacitors with electrodes based on electrochemically exfoliated graphene and an ultrathin solid-state electrolyte based on nano-graphene oxide. The devices exploit the high ionic conductivity of nano-graphene oxide coupled with the high electrical conductivity of graphene films, yielding areal capacitances of up to 313 mu F cm-2 at 5 mV s-1 and high power densities of up to 4 mW cm-3 with an overall device thickness of only 1 mu m.

  • 34.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Fredrik, Forsberg
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Senseair AB.
    Wagner, Stefan
    AMO GmbH.
    Rödjegård, Henrik
    Senseair AB.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB, Järfälla, Sweden.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. RWTH Aachen University ; AMO GmbH.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Graphene ribbons with suspended masses as transducers in ultra-small nanoelectromechanical accelerometers2019In: Nature Electronics, ISSN 2520-1131, Vol. 2, no 9, p. 394-404Article in journal (Refereed)
    Abstract [eo]

    Nanoelectromechanical system (NEMS) sensors and actuators could be of use in the development of next-generation mobile, wearable and implantable devices. However, these NEMS devices require transducers that are ultra-small, sensitive and can be fabricated at low cost. Here, we show that suspended double-layer graphene ribbons with attached silicon proof masses can be used as combined spring–mass and piezoresistive transducers. The transducers, which are created using processes that are compatible with large-scale semiconductor manufacturing technologies, can yield NEMS accelerometers that occupy at least two orders of magnitude smaller die area than conventional state-of-the-art silicon accelerometers. With our devices, we also extract the Young’s modulus values of double-layer graphene and show that the graphene ribbons have significant built-in stresses.

  • 35.
    Hou, Shuoben
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    High Temperature High Current Gain IC Compatible 4H-SiC Phototransistor2019Conference paper (Refereed)
    Abstract [en]

    This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 ºC. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 ºC. The βFmax drops to 51 at 400 ºC and remains the same at 500 ºC. The photo current gain of the phototransistor is 3.9 at 25 ºC and increases to 14 at 500 ºC under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4HSiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics onchip integration.

  • 36.
    Majdi, S.
    et al.
    Uppsala Univ, Div Elect, Dept Engn Sci, Box 534, S-75121 Uppsala, Sweden..
    Gabrysch, M.
    Uppsala Univ, Div Elect, Dept Engn Sci, Box 534, S-75121 Uppsala, Sweden..
    Suntornwipat, N.
    Uppsala Univ, Div Elect, Dept Engn Sci, Box 534, S-75121 Uppsala, Sweden..
    Burmeister, F.
    Uppsala Univ, Div Elect, Dept Engn Sci, Box 534, S-75121 Uppsala, Sweden..
    Jonsson, R.
    Uppsala Univ, Div Elect, Dept Engn Sci, Box 534, S-75121 Uppsala, Sweden..
    Kovi, K. K.
    Uppsala Univ, Div Elect, Dept Engn Sci, Box 534, S-75121 Uppsala, Sweden.;Argonne Natl Lab, Ctr Nanoscale Mat, 9700 S Cass Ave, Argonne, IL 60439 USA..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    High-temperature deep-level transient spectroscopy system for defect studies in wide-bandgap semiconductors2019In: Review of Scientific Instruments, ISSN 0034-6748, E-ISSN 1089-7623, Vol. 90, no 6, article id 063903Article in journal (Refereed)
    Abstract [en]

    Full investigation of deep defect states and impurities in wide-bandgap materials by employing commercial transient capacitance spectroscopy is a challenge, demanding very high temperatures. Therefore, a high-temperature deep-level transient spectroscopy (HT-DLTS) system was developed for measurements up to 1100 K. The upper limit of the temperature range allows for the study of deep defects and trap centers in the bandgap, deeper than previously reported by DLTS characterization in any material. Performance of the system was tested by carrying out measurements on the well-known intrinsic defects in n-type 4H-SiC in the temperature range 300-950 K. Experimental observations performed on 4H-SiC Schottky diodes were in good agreement with the literature. However, the DLTS measurements were restricted by the operation and quality of the electrodes.

  • 37.
    Ekström, Mattias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators2019In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 5, p. 670-673Article in journal (Refereed)
    Abstract [en]

    Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

  • 38.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance Spectroscopy Based on Linear System Identification2019In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed)
    Abstract [en]

    Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

  • 39.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 40.
    Sollami Delekta, Szymon
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Inkjet Printing of Graphene-based Microsupercapacitors for Miniaturized Energy Storage Applications2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Printing technologies are becoming increasingly popular because they enable the large-scale and low-cost production of functional devices with various designs, functions, mechanical properties and materials. Among these technologies, inkjet printing is promising thanks to its direct (mask-free) patterning, non-contact nature, low material waste, resolution down to 10 µm, and compatibility with a broad range of materials and substrates. As a result, inkjet printing has applications in several fields like wearables, opto-electronics, thin-film transistors, displays, photovoltaic devices, and in energy storage. It's in energy storage that the technique shows its full potential by allowing the production of miniaturized devices with a compact form factor, high power density and long cycle life, called microsupercapacitors (MSCs). To this end, graphene has a number of remarkable properties like high electrical conductivity, large surface area, elasticity and transparency, making it a top candidate as an electrode material for MSCs.

    Some key drawbacks limit the use of inkjet printing for the production of graphene-based MSCs. This thesis aims at improving its scalability by producing fully inkjet printed devices, and extending its applications through the integration of inkjet printing with other fabrication techniques.

    MSCs typically rely on the deposition by hand of gel electrolyte that is not printable or by submerging the whole structure into liquid electrolyte. Because of this, so far large-scale production of more than 10 interconnected devices has not been attempted. In this thesis, a printable gel electrolyte ink based on poly(4-styrene sulfonic acid) was developed, allowing the production of large arrays of more than 100 fully inkjet printed devices connected in series and parallel that can be reliably charged up to 12 V. Also, a second electrolyte ink based on nano-graphene oxide, a solid-state material with high ionic conductivity, was formulated to optimize the volumetric performance of these devices. The resulting MSCs were also fully inkjet printed and exhibited an overall device thickness of around 1 µm, yielding a power density of 80 mW cm-3.

    Next, the use of inkjet printing of graphene was explored for the fabrication of transparent MSCs. This application is typically hindered by the so-called coffee-ring effect, which creates dark deposits on the edges of the drying patterns and depletes material from the inside area. In light of this issue, inkjet printing was combined with etching to remove the dark deposits thus leaving uniform and thin films of graphene with vertical sidewalls. The resulting devices showed a transmittance of up to 90%.

    Finally, the issue of the substrate compatibility of inkjet printed graphene was addressed. Although inkjet printing is considered to have broad substrate versatility, it is unreliable on hydrophilic or porous substrates and most inks (including graphene inks) require thermal annealing that damages substrates that are not resistant to heat. Accordingly, a technique based on inkjet printing and wet transfer was developed to reliably deposit graphene-based MSCs on a number of substrates, including flat, 3D, porous, plastics and biological (plants and fruits) with adverse surfaces.

    The contributions of this thesis have the potential to boost the use of inkjet printed MSCs in applications requiring scalability and resolution (e.g. on-chip integration) as well as applications requiring conformability and versatility (e.g. wearable electronics).

  • 41.
    Woerle, Judith
    et al.
    Swiss Fed Inst Technol, Adv Power Semicond Lab, CH-8092 Zurich, Switzerland.;Paul Scherrrer Inst, Lab Micro & Nanotechnol, CH-5232 Villigen, Switzerland..
    Prokscha, Thomas
    Paul Scherrer Inst, Lab Muon Spin Spect, CH-5232 Villigen, Switzerland..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Grossner, Ulrike
    Swiss Fed Inst Technol, Adv Power Semicond Lab, CH-8092 Zurich, Switzerland..
    Interaction of low-energy muons with defect profiles in proton-irradiated Si and 4H-SiC2019In: Physical Review B, ISSN 2469-9950, E-ISSN 2469-9969, Vol. 100, no 11, article id 115202Article in journal (Refereed)
    Abstract [en]

    Muon spin rotation (mu SR) with low-energy muons is a powerful nuclear method where electrical and magnetic properties of thin films can be investigated in a depth-resolved manner. Here, we present a study on proton-irradiated Si and 4H-SiC where the formation of the hydrogen-like muonium (Mu) is analyzed as a function of the proton dose. While the Mu formation is strongly suppressed in the highly defective region of the shallow proton stopping profile, the Mu signal quickly recovers for higher muon energies where the muons reach the untreated semiconductor bulk. A lower sensitivity limit of low-energy mu SR to crystal defects of around 10(17) to 10(18) cm(-3) is estimated. Our results demonstrate the high potential of this technique to nondestructively probe near-surface regions without the need for electronic device fabrication and to provide valuable complementary information when investigating defects in semiconductors.

  • 42.
    Ekström, Mattias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Ferrario, Andrea
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide2019In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 48, no 4, p. 2509-2516Article in journal (Refereed)
    Abstract [en]

    Previous studies showed that cobalt silicide can form ohmic contacts to p-type 6H-SiC by directly reacting cobalt with 6H-SiC. Similar results can be achieved on 4H-SiC, given the similarities between the different silicon carbide polytypes. However, previous studies using multilayer deposition of silicon/cobalt on 4H-SiC gave ohmic contacts to n-type. In this study, we investigated the cobalt silicide/4H-SiC system to answer two research questions. Can cobalt contacts be self-aligned to contact holes to 4H-SiC? Are the self-aligned contacts ohmic to n-type, p-type, both or neither? Using x-ray diffraction, it was found that a mixture of silicides (Co2Si and CoSi) was reliably formed at 800°C using rapid thermal processing. The cobalt silicide mixture becomes ohmic to epitaxially grown n-type (1×1019cm-3) if annealed at 1000°C, while it shows rectifying properties to epitaxially grown p-type (1×1019cm-3) for all tested anneal temperatures in the range 800–1000°C. The specific contact resistivity (ρC) to n-type was 4.3×10-4 Ω cm2. This work opens the possibility to investigate other self-aligned contacts to silicon carbide.

  • 43.
    Kelati, Amleset
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. University of Turku, Finland .
    DHAOU, Imed BEN
    Unaizah College of Engineering, Qassim University, Saudi Arabia; University of Monastir, Tunisia .
    Kondoro, Aron
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. University of Dar es Salaam, Tanzania .
    Rwegasira, Diana
    KTH. University of Dar es Salaam, Tanzania .
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. University of Turku, Finland .
    IoT based Appliances Identification Techniques with FogComputing for e-Health2019In: 2019 IST-Africa Week Conference (IST-Africa, Narobi, Kenya: IEEE, 2019Conference paper (Refereed)
    Abstract [en]

    To improve the living standard of urban communities and to render the healthcare services sustainable and efficient, e-health system is experiencing a paradigm shift. Patients with cognitive discrepancies can be monitored and observed through the analyses of power consumption of home appliances. This paper surveys recent trends in home-based e-health services using metered energy consumption data. It also analyses and summarizes the constant impedance, constant current and constant power (ZIP) approaches for load modelling. The analysis briefly recaptures both non-intrusive and intrusive techniques. The work reports an architecture using IoT technologies for the design of a smart-meter, and fog-computing paradigm for raw processing of energy dataset. Finally, the paper describes the implementation platform based on GirdLAB-D simulation to construct accurate models of household appliances and test the machine-learning algorithm for the detection of abnormal behaviour.

  • 44.
    Malm, B. Gunnar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Eklund, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Dvornik, Mykola
    Gothenburg University, Department of Physics .
    Micromagnetic Modeling of Telegraphic Mode Jumping in Microwave Spin Torque Oscillators2019Conference paper (Other academic)
    Abstract [en]

    The time domain stability of microwave spin torque oscillators (STOs) has been investigated by systematic micromagnetic simulations. A model based on internal spin wave reflection at grain boundaries with reduced exchange coupling was implemented and used to study the oscillator under quasi-stable operating conditions. Telegraphic mode jumping between two operating frequencies (23.3 and 24.1 GHz) was observed in the time domain with characteristic dwell times in the range of 10-100 ns. The oscillating volume was shown to have a different shape at the distinct operating frequencies. The shape difference is governed by spin wave reflections at the grain boundaries. The resulting non-linear behavior of the oscillator was shown to be a collective effect of spin wave scattering at different locations within a few spin wavelengths from the nano-contact.

  • 45.
    Javed, Aqsa
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.
    Ejaz, Asma
    ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan.
    Mehak, Sumrin
    ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan.
    Amin, Yasar
    KTH. ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Department of Information Technology, TUCS, University of Turku, Turku, 20520, Finland.
    Miniaturized cross-lines rectangular ring-shaped flexible multiband antenna2019In: Applied Computational Electromagnetics Society Journal, ISSN 1054-4887, Vol. 34, no 5, p. 625-630Article in journal (Refereed)
    Abstract [en]

    A compact, flexible antenna for wireless applications, i.e., WLAN/WiMAX/Wi-Fi, UMTS2100, C-Band, and DSRC is presented. The quad-band antenna is designed and analyzed in terms of efficiency, gain, radiation pattern, return loss, and VSWR. The optimized design consists of a CPW fed rectangular ring patch with the semi-circular ground. The cross-lines and the semicircular ground is investigated to ascertain the multiband effect. A concept of inset feed mechanism is also interpolated to enhance impedance matching. The framed antenna is examined under the bent condition as well. The reported work is an apt candidate for the proposed applications because of its high efficiency of 95% with a peak gain of 3.22 dBi along with VSWR less than 2. With stable radiation pattern and bandwidth, there is a justified concurrence between simulated and measured results.

  • 46. Chen, Kun-Chih (Jimmy)
    et al.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Wang, Ting-Yi
    Yang, Yuch-Chi
    NoC-based DNN Accelerator: A Future Design Paradigm2019Conference paper (Refereed)
    Abstract [en]

    Deep Neural Networks (DNN) have shown significant advantagesin many domains such as pattern recognition, prediction, and controloptimization. The edge computing demand in the Internet-of-Things era has motivated many kinds of computing platforms toaccelerate the DNN operations. The most common platforms areCPU, GPU, ASIC, and FPGA. However, these platforms suffer fromlow performance (i.e., CPU and GPU), large power consumption(i.e., CPU, GPU, ASIC, and FPGA), or low computational flexibilityat runtime (i.e., FPGA and ASIC). In this paper, we suggest theNoC-based DNN platform as a new accelerator design paradigm.The NoC-based designs can reduce the off-chip memory accessesthrough a flexible interconnect that facilitates data exchange betweenprocessing elements on the chip. We first comprehensivelyinvestigate conventional platforms and methodologies used in DNNcomputing. Then we study and analyze different design parametersto implement the NoC-based DNN accelerator. The presentedaccelerator is based on mesh topology, neuron clustering, randommapping, and XY-routing. The experimental results on LeNet, MobileNet,and VGG-16 models show the benefits of the NoC-basedDNN accelerator in reducing off-chip memory accesses and improvingruntime computational flexibility.

  • 47.
    Zhou, Weidong
    et al.
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Liu, Shih-Chia
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Ge, Xiaochen
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Zhao, Deyin
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Yang, Hongjun
    Univ Texas Arlington, Dept Elect Engn, Arlington, TX 76019 USA..
    Reuterskiöld-Hedlund, Carl
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Hammar, Mattias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    On-Chip Photonic Crystal Surface-Emitting Membrane Lasers2019In: IEEE Journal of Selected Topics in Quantum Electronics, ISSN 1077-260X, E-ISSN 1558-4542, Vol. 25, no 3, article id 4900211Article in journal (Refereed)
    Abstract [en]

    Photonic crystal lasers can be realized either based on photonic bandgap defect mode or defect-free bandedge mode, while the bandgap is not essential for the latter. We review here defect-free bandedge mode based photonic crystal surface-emitting lasers (PCSELs) for on-chip integration. We first discuss ultra-thin membrane reflector vertical-cavity surface-emitting lasers (MR-VCSELs), where single layer photonic crystal slabs can be designed as a broadband membrane reflector. Later, we discuss another type of defect-free PCSELs where the lasing cavity is formed based on evanescent coupling of gain medium with the photonic crystal bandedge mode near bandedge. Cavity designs were carried out for the optimal modal overlap and high confinement factors. Lateral cavity size scaling was also investigated both theoretically and experimentally in PCSELs. Buried tunnel junction based InGaAsP quantum well heterostructures were also designed and incorporated into electrically injected PCSELs. Finally, discussions are given toward energy efficient lasers.

  • 48.
    Zhan, Junkai
    et al.
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Huang, Letian
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Wang, Junshi
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Li, Qiang
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Online Path-based Test Method for Network-on-Chip2019In: 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2019Conference paper (Refereed)
    Abstract [en]

    A considerable amount of routers and links remains idle after each mapping application onto the Network-on-Chip based many-core systems. Online path-based test method is a kind of self-test for these idle components. In this paper, a path-based fabric for NoC is firstly proposed. A path serves as the basic component, covering one link and its associated control logic in the routers. One possibility is to apply fault detection on the idle paths, while the other paths continue to operate normally. Moreover, this paper details the hardware implementation, targeting the stuck-at and bridging faults. It suggests a good trade-off between fault coverage, hardware overhead and test time. Experimental results show that the approach achieves 93% of the stuck-at faults in control unit and cover 100% of the stuck-at and bridging faults on the global link within 256 clock cycles.

  • 49.
    Tariq, Nimra
    et al.
    Univ Engn & Technol Taxila, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Riaz, Muhammad Ali
    Univ Engn & Technol Taxila, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Shahid, Humayun
    Univ Engn & Technol Taxila, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Khan, Muhammad Jamil
    Univ Engn & Technol Taxila, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Khan, Mansoor Shaukat
    COMSATS Univ Islamabad, Math Dept, Islamabad 45550, Pakistan..
    Amin, Yasar
    Univ Engn & Technol Taxila, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Loo, Jonathan
    Univ West London, Sch Comp & Engn, London W5 5RF, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Turku, Dept Informat Technol, TUCS, FIN-20520 Turku, Finland..
    Orientation Independent Chipless RFID Tag Using Novel Trefoil Resonators2019In: IEEE Access, E-ISSN 2169-3536, Vol. 7, p. 122398-122407Article in journal (Refereed)
    Abstract [en]

    In this paper, a compact and fully passive bit encoding circuit, capable of operating as a chipless radio frequency identification (RFID) tag is presented. The structure consists of novel concentric trefoil-shaped slot resonators realized using Rogers RT/duroid (R) 5880 laminate, occupying a physical footprint of 13.55 x 13.55 mm(2). Each resonating element is associated with a particular data bit, having a 1:1 resonator-to-bit correspondence. Bit sequences are configured through introducing modifications in the geometric structure either by addition or exclusion of each nested slot resonator. Such changes manifest directly in the electromagnetic signature of the tag as presence or absence of corresponding resonant peaks. The proposed 10-bit tag offers minimized inter-resonator mutual coupling and insensitivity to changes in polarization and incident angles thereby demonstrating orientation independent functionality. Moreover, error-free encoding is achieved through stabilizing the shift in resonant frequencies for a variety of different geometric configurations and orientation of the structure. The tag operates within the license-free ultrawideband ranging from 5.4 to 10.4 GHz, providing spectral bit capacity and bit density of 2 bits/GHz and 5.44 bits/cm(2) respectively.

  • 50. Ahmad, S. A.
    et al.
    Naqvi, S. I.
    Khalid, M.
    Amin, Y.
    Loo, J.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Penta-band antenna with defected ground structure for wireless communication applications2019In: 2019 2nd International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2019, Institute of Electrical and Electronics Engineers Inc. , 2019Conference paper (Refereed)
    Abstract [en]

    This work proposes a compact, penta-band, slotted antenna with Defected Ground Structure (DGS). The proposed multiband resonator is intended for integration into microwave circuits and portable RF portable devices. The prototype with spurlines and DGS is designed on thin Rogers RT Duroid 5880 substrate having thickness 0.508 mm. The presented radiator is capable to cover the frequency bands 2.46-2.59 GHz, 2.99-3.78 GHz, 5.17-5.89 GHz, 6.86-7.36 GHz, 9.38-11 GHz. The impedance bandwidths of 5.24%, 23.68%, 12.8%, 7.24% and 16.08% is obtained for the covered frequency bands respectively. The antenna proposed in this work thus supports WLAN, WiMAX, ISM, LTE, Bluetooth, C-band and X-band applications. The radiator attains 4.2 dB peak gain. It is apparent from the radiation performance of the prototype, that it is an effective candidate for current and forthcoming multiband wireless applications.

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