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  • 101.
    Mou, Duan
    KTH, Superseded Departments, Electronic Systems Design.
    Complex oxide films for memory and detector applications1998Doctoral thesis, comprehensive summary (Other scientific)
  • 102.
    Mouroux, Aliette
    KTH, Superseded Departments, Electronic Systems Design.
    The reactive formation of TiSi<SUB>2</SUB>in the presence of refractory metals1999Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Titanium disilicide (TiSi2) has been the favoured material for contactmetallisation in recent Si devices. The formation of TiSi2usually begins with the high resistivity C49 phaseas a result of the Ti-Si interaction at about 300-550 °Cand finishes with the low resistivity C54 phase through theC49-C54 phase transformation at about 700 °C. The C49-C54transformation becomes increasingly difficult as the devicedimensions are scaled down and remains a technologicalchallenge for dimensions below 0.5 µm. In this thesis, athin layer of Mo deposited between Ti film and Si substrate isused to promote the formation of the C54 phase at temperature100 °C lower than for the C49-C54 transformation. Onnarrow Si lines down to 0.25 µm width, the influence of Moon the formation of TiSi2is even more pronounced than on blanketsubstrates; lower sheet resistance with smaller scatter isobtained in the presence of Mo than without. The enhancement inthe formation of the C54 phase is interpreted as a consequenceof epitaxial effects where the formation of C40 (Mo,Ti)Si2plays a key role. The validity of the template mechanism isverified by replacing Mo with Ta and Nb. The idea of using Taand Nb comes from the fact that TaSi2and NbSi2have the same crystallographic structure andcomparable lattice parameters as (Mo,Ti)Si2. The epitaxial mechanism is confirmed by latticeimaging with a high-resolution microscope. In order to gain aninsight into the thermodynamics of the ternary systems, thepseudo binary phase diagram of TiSi2-NbSi2is studied. Three phase domains are identified,i.e. 1) C54 (Ti,Nb)Si2with Nb varying from 0 to 10 % at the metal sites,2) a mixture of C54 and C40 (Ti,Nb)Si2with Nb being 10 to 25 % at the metal sites, and3) C40 (Ti,Nb)Si2with Nb varying from 25 to 100 % at the metalsites. The resistivity of (Ti,Nb)Si2C54 increases by 1.2 µΩ cm per at. % Nbwhen the Nb concentration varies from 0 to 10 % at the metalsites. The presence of the refractory metals (Ta, Nb or Mo) atthe Si/Ti interface modifies the energetic factors for theformation of C54 TiSi2. The formation of C49 TiSi2is hindered and that of C54 is enhanced. With a Moor Nb interposed layer, the phase of C54 TiSi2can be obtained at temperatures as low as 450°C. Moreover, if a continuous silicide layer in the C40structure is formed at the Si/TiSi2interface, it is the Si diffusion through thisinterfaced layer that is the controlling factor for the C54TiSi2growth. Furthermore, the use of an interposedlayer of Mo, Ta or Nb generally improves the surface morphologyand morphological stability: the TiSi2 formed has a smoothersurface and interface and is more resistant toagglomeration.

    Key words: Titanium disilicide TiSi2, contact metallisation, phase formation,refractory metals, sub-micron technology, template growth, verylarge scale integration, VLSI, interconnection.

  • 103.
    Nilsson, Hans-Erik
    KTH, Superseded Departments, Electronic Systems Design.
    Theoretical and experimental study of vertical MESFETs in Si and SiC1997Doctoral thesis, comprehensive summary (Other scientific)
  • 104. Nurmi, T.
    et al.
    Pamunuwa, Dinesh
    KTH, Superseded Departments, Electronic Systems Design.
    Ahonen, T.
    Zheng, Lirong
    KTH, Superseded Departments, Electronic Systems Design.
    Isoaho, J.
    Global interconnect analysis towards networks-on-a-chipundefined: undefined2004In: Interconnect-centric design for advanced SOC and NOCundefined: undefined / [ed] J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch, Springer-Verlag New York, 2004, 1, p. 55-84Chapter in book (Other academic)
  • 105. Nurmi, Tero
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Nurmi, Jari
    Isoaho, Jouni
    Physical Performance Modelling for Platform-based SoC Design2002In:  , 2002Conference paper (Refereed)
  • 106.
    Oelmann, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Asynchronous and mixed synchronous/asynchronous design techniques for low power2000Doctoral thesis, comprehensive summary (Other scientific)
  • 107. Ofner, Erwin
    et al.
    Nurmi, J.
    Madsen, J.
    Isoaho, J.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    SoC-Mobinet, R&D and Education in System-on-Chip Design2004In: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi, J; Takala, J; Hamalainen, TD, 2004, p. 77-80Conference paper (Refereed)
    Abstract [en]

    With fabrication technologies enabling the integration of a billion transistors and allowing gigahertz frequencies, complex systems (System-on-Chip, SoC) can be realized on a single die. The design of such systems provides tremendous challenges to industry and academia. Universities need to invest a huge effort to restructure their related engineering curricula, which is only possible in close co-operations with industry and other Universities. This paper describes a project, co-funded by the European Commission and by industry, where in a joint effort related research results are turned into course contents for SoC-curricula and industry training activities.

  • 108.
    Olson, Henrik
    KTH, Superseded Departments, Electronic Systems Design.
    ASIC implementable synchronization - and detection methods for direct sequence spread spectrum wideband radio receivers1997Licentiate thesis, monograph (Other scientific)
  • 109. Olson, Henrik
    et al.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Floating- to Fixed-Point Refinement in Matlab with an Object-Oriented Library1999In:  , 1999Conference paper (Refereed)
  • 110.
    O'Nils, Mattias
    KTH, Superseded Departments, Electronic Systems Design.
    Specification, synthesis and validation of hardware/software interfaces1999Doctoral thesis, comprehensive summary (Other scientific)
  • 111.
    O’Nils, Mattias
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Interactive Hardware-Software Partitioning and Memory Allocation Based on Data Transfer Profiling1995In: Proceeding of International Conference on Recent Advances in Mechatronics, 1995Conference paper (Refereed)
  • 112. O’Nils, Mattias
    et al.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Interactive Hardware-Software Partitioning and Memory Allocation Based on Data Transfer Profiling1995In:  , 1995Conference paper (Refereed)
  • 113.
    O’Nils, Mattias
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tammemäe, Kalle
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Design of D-AMPS Channel Decoder with Codesign Methodologies1996In: Proceedings of the Baltic Electronics Conference, 1996, p. 397-400Conference paper (Refereed)
  • 114.
    O’Nils, Mattias
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tammemäe, Kalle
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Experiences using Akka: A Hardware-Software Codesign Tool Kit in design of Telecommunication systems1995Conference paper (Refereed)
  • 115.
    O'Nils, Mattias
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    Jantsch, Axel
    Grammar Based Modelling and Synthesis of Device Drivers and Bus Inter­faces1998In: EuroMicro, 1998, p. 55-58Conference paper (Refereed)
  • 116. Pamunuwa, D.
    et al.
    Öberg, J.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Millberg, M.
    Jantsch, A.
    Tenhunen, H.
    KTH, Superseded Departments, Electronic Systems Design.
    Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures2003In:  , 2003Conference paper (Refereed)
  • 117.
    Pamunuwa, Dinesh
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Millberg, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime2004In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 38, no 1, p. 3-17Article in journal (Refereed)
    Abstract [en]

    On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

  • 118.
    Rapp, Stefan
    KTH, Superseded Departments, Electronic Systems Design.
    Long-wavelength vertical-cavity lasers based on InP/GaInAsp bragg reflectors1999Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Vertical-cavity surface-emitting lasers (VCSELs) operatingat long wavelength (1.3-1.55µm) are of great interest asinexpensive, high-performance light sources for opticalcommunication systems. The vertical geometry and the smalldimensions of the laser cavity are advantageous for on-chiptesting, packaging, effective fibre coupling and potentiallow-cost fabrication. Operation at long wavelength isfavourable for applications in fibre-optical communication dueto the superior transmission characteristics in standard silicafibres. However, in contrast to GaAs-based VCSELs operating atwavelengths below 1µm, which have seen a tremendousdevelopment in recent years, the progress for thelong-wavelength devices has been much slower. This is mainlydue to intrinsic material problems in the GaInAsP alloy system.The limited refractive index contrast between InP and GaInAsPis of specific importance, impeding the fabrication of anall-epitaxial device structure with two monolithicallyintegrated semiconductor distributed Bragg reflectors (DBRs) asit is common for GaAs-based VCSELs. Instead, the mostsuccessful designs have relied on the combination of anInP-based active region with DBRs from different materialsystems. To date, the best performing VCSELs for longwavelength employ two GaAs-based mirrors, requiring twowafer-fusion steps and three substrates; hence leavingquestions for a strategy toward reliability, full wafer scaleprocessing and cost management. For this reason, there is astrong interest in monolithic devices, i.e., devices that canbe grown entirely on InP-substrate in a more inexpensiveprocess. However, only very recently there are designs reportedin literature operating continuous-wave at room temperatureemploying a monolithically integrated mirror.

    In this thesis, long-wavelength VCSELs based on integratedInP/GaInAsP Bragg reflectors grown by metal-organicvapour-phase epitaxy are presented and analysed. The firstchapter gives an introduction to long-wavelength VCSELs,including a review of the state-of-the-art devices as well as adiscussion of material and design related issues. The secondchapter of the thesis goes into detail with DBR design, devicedesign, fabrication technology as well as the characterisationand analysis of the lasers. Two structures based on anInP/GaInAsP bottom mirror are presented: a semi-insulatingInP:Fe regrown laser structure and a single-wafer-fusedstructure. The regrown laser employs a dielectric top mirrorand operates continuous-wave up to -9°C and pulsed up to45°C.The single-wafer-fused laser makes use of a GaAs/AlGaAs top mirror and shows an improved performance. This wasthe first device based on an integrated InP/GaInAsP mirrorreported to operate continuous-wave near room temperature (at17°C), and it operates pulsed up to temperatures as highas 101°C. The advantages and drawbacks of both designs arediscussed. A third VCSEL structure discussed in this thesis isbased on a so-called air-gap mirror. Herein, every second layerin an InP/GaInAs stack has been removed, resulting in a veryhigh-index contrast Bragg reflector. This VCSEL, which isoptically pumped, was the first of its kind ever reported forlong wavelength.

  • 119.
    Raudvere, Tarvo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Sander, Ingo
    KTH, Superseded Departments, Electronic Systems Design.
    Singh, Ashish Kumar
    KTH, Superseded Departments, Electronic Systems Design.
    Gurov, Dilian
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    The ForSyDe semantics2002In: Proceedings of Swedish System-on-Chip Conference, 2002Conference paper (Refereed)
  • 120.
    Raudvere, Tarvo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Sander, Ingo
    KTH, Superseded Departments, Electronic Systems Design.
    Singh, Ashish Kumar
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Verification of Design Decisions in ForSyDe2003In: Proceedings of the CODES-ISSS Conference, 2003Conference paper (Refereed)
  • 121.
    Raudvere, Tarvo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Singh, Ashish Kumar
    KTH, Superseded Departments, Electronic Systems Design.
    Sander, Ingo
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Polynomial abstraction for verification of sequentially implemented combinational circuits2004In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS / [ed] Gielen, G; Figueras, J, LOS ALAMITOS: IEEE COMPUTER SOC , 2004, p. 690-691Conference paper (Refereed)
    Abstract [en]

    Todays integrated circuits with increasing complexity cause the well known state space explosion problem in verification tools. In order to handle this problem a much simpler abstract model of the design has to be created for verification. We introduce the polynomial abstraction technique, which efficiently simplifies the verification task of sequential design blocks whose functionality can be expressed as a polynomial. Through our technique, the domains of possible values of data input signals can be reduced. This is done in such a way that the abstract model is still valid for model checking of the design functionality in terms of the system's control and data properties. We incorporate polynomial abstraction into the ForSyDe methodology, for the verification of clock domain design refinements.

  • 122.
    Rodríguez Messmer, Egbert
    KTH, Superseded Departments, Electronic Systems Design.
    Selective epitaxy and in-situ etching studies on III-V semiconductor surfaces2000Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Semiconductor lasers are widely used in e.g. opticalcommunication networks or data storage and retrieval in CDs orDVDs. As the applications of this type of lasers grow, thedemands on low power consumption, high operating speed, orsmall device size are becoming more important. Theserequirements can be met in certain cases by improvedfabrication and processing techniques. In turn, to be able toimprove these techniques, a good understanding is necessary.This thesis emerged from the need to gain such an understandingwith the view to improve device performance.

    A Hydride Vapour Phase Epitaxy (HVPE) reactor is used inthis thesis to carry out selective epitaxy and in-situ mesaetching on III-V semiconductor surfaces. Morphologicalevolution during selective epitaxy on non-planar substrates asa function of crystallographic orientation, growth temperatureand V/III ratio is analysed and modelled semi-quantitatively.The analysis is based on the net change of dangling bonds dueto indium addition in a phosphine rich ambient. The evolutionof growth is explained and the repercussion on dopantincorporation is discussed. Knowledge gained from such ananalysis is successfully implemented in the fabrication ofburied heterostructure vertical cavitysurface emitting lasers(VCSELs). The gained knowledge is also applied to the formationof InP templates on FIB (focussed ion beam) patterned GaAssubstrates. These templates can be used for fabricatingmicrostructures and nanostructues or to integrate InP baseddevices with GaAs based ones

    In-situ mesa etching is also studied as a function of thepartial pressure of the active gases, (HCl, PH3and InCl), stripe orientation and etchingtemperature. Four major etching mechanisms are proposed whichqualitatively explain the resulting mesa shapes as well asvertical and lateral etching rates. The experimental resultsshow that the depth and the undercut of the mesas can be etchedindependently. Technological importance of combining in-situmesa etching and immediate selective epitaxy of semi-insulatingmaterials is demonstrated through the realisation of buriedheterostructure in-plane lasers (BH-IPL).

    Keywords:InP, selective epitaxy, regrowth, in-situ mesaetching, buried heterostructures

  • 123.
    Rusu, Ana
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Borodenkov, Alexei
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Design of a power/performance efficient single-loop sigma-delta modulator for wireless receivers2004In: INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION / [ed] Macii, E; Paliouras, V; Koufopavlou, O, BERLIN: SPRINGER , 2004, Vol. 3254, p. 564-573Conference paper (Refereed)
    Abstract [en]

    In order to design high performance sigma-delta A/D converters, it is essential to estimate the Figure-Of-Merit in the design process. This paper describes the design of a power/performance efficient single-loop multibit sigma-delta modulator for wireless applications. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. A 3(rd) order 4-bit Sigma-Delta modulator with feedforward path is designed in 0.18um CMOS process operating from 1.8V supply voltage. The modulator dissipates 8.6 mW and achieves a dynamic range of 84/95 dB over a bandwidth of 2000/100 kHz.

  • 124.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Formal Design Based on the Synchronous Approach, Functional Models and Skeletons1999In: Proceedings of the Twelfth International Conference on VLSI Design, 1999Conference paper (Refereed)
  • 125.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    System modeling and transformational design refinement in ForSyDe2004In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 23, no 1, p. 17-32Article in journal (Refereed)
    Abstract [en]

    The scope, of the Formal System Design (ForSyDe) methodology is high-level modeling and refinement of systems-on-a-chip and embedded systems. Starting with a formal specification model, that captures the functionality of the system at a high abstraction level, it provides formal design-transformation methods for a transparent refinement process of the system model into an implementation model that is optimized for synthesis. The main contribution of this paper is the ForSyDe modeling technique and the formal treatment of transformational design refinement. We introduce process constructors, that cleanly separate the computation part of a process from the synchronization and communication part. We develop the characteristic function for each process type and use it to define semantic preserving and design decision transformations. These transformations are characterized by name, the format of the original process network, the transformed process network, and a design implication. The implication expresses the relation between original and transformed process network by means of the characteristic function. The objective of the refinement process is a model that can be implemented cost efficiently. To this end, process constructors and processes have a hardware and software interpretation which shall facilitate accurate performance and cost estimations. In a study of a digital equalizer example, we illustrate the modeling and refinement process and focus in particular on refinement of the clock domain, communication refinement, and resource sharing.

  • 126.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    System Synthesis Based on a Formal Computational Model and Skeletons1999In: Proceedings of the IEEE Computer Society Annual Workshop on VLSI, 1999Conference paper (Refereed)
  • 127.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    System Synthesis Utilizing a Layered Functional Model1999In: Proceedings of the 7th International Workshop on Hardware/Software Codesign, 1999, p. 136-141Conference paper (Refereed)
  • 128.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Transformation Based Communication and Clock Domain Refinement for System Design2002In: Proceedings of Design Automation Conference, 2002Conference paper (Refereed)
  • 129.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Lu, Zhonghai
    KTH, Superseded Departments, Electronic Systems Design.
    Development and application of design transformations in ForSyDe2003In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 150, no 5, p. 313-320Article in journal (Refereed)
    Abstract [en]

    The formal system design (ForSyDe) methodology has been developed for system level design. Starting with a formal specification model, which captures the functionality of the system at a high level of abstraction, it provides formal design transformation methods for a transparent refinement process of the specification model into an implementation model which is optimised for synthesis. The formal treatment of transformational design refinement is the central contribution of this article. Using the formal semantics of ForSyDe processes we introduce the term characteristic function to be able to define and classify transformations as either semantic preserving or design decision. We also illustrate how we can incorporate classical synthesis techniques that have traditionally been used with control/data-flow graphs as ForSyDe transformations. This approach avoids discontinuities as it moves design refinement into the domain of the specification model.

  • 130.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Lu, Zhonghai
    KTH, Superseded Departments, Electronic Systems Design.
    The Development and Application of Formal Design Transformations in ForSyDe2003In: Proceedings of the Design Automation and Test Europe (DATE), 2003Conference paper (Refereed)
  • 131.
    Sander, Ingo
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    The Platform as Interface in a SoC Design Curriculum2004In: Microelectronics Education: Proceedings of the 5th European Worksop on Microelectronics Education, 2004Conference paper (Refereed)
  • 132.
    Sandén, Martin
    KTH, Superseded Departments, Electronic Systems Design.
    Electrical characterization of high-frequency silicon bipolar transistors1999Licentiate thesis, comprehensive summary (Other scientific)
  • 133.
    Schuppener, Gerd
    KTH, Superseded Departments, Electronic Systems Design.
    High-frequency integrated circuits for fiber-optic and wireless communication links1999Doctoral thesis, comprehensive summary (Other scientific)
  • 134.
    Shen, Meigen
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Liu, Jian
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Chip-package co-design for high performance and reliability off-chip communications2004In: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), NEW YORK: IEEE , 2004, p. 31-36Conference paper (Refereed)
    Abstract [en]

    Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design methodology is presented. We address high performance and reliability enhancement for off-chip communications under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, it is shown that the system-level performances such as signal integrity, bandwidth, and reliability are significantly improved through this co-design methodology.

  • 135. Shen, Meigen
    et al.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip2003In:  , 2003, Vol. 5Conference paper (Refereed)
  • 136.
    Shen, Meigen
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Robustness enhancement through chip-package co-design for high-speed electronics2004In: ISQED 2004:  , LOS ALAMITOS: IEEE COMPUTER SOC , 2004, p. 184-189Conference paper (Other academic)
    Abstract [en]

    Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design flow is presented. We address robustness enhancement under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, co-design can reduce signal integrity problem, enhance its bandwidth, and improve high-speed electronic systems robustness.

  • 137.
    Silfvenius, Christofer
    KTH, Superseded Departments, Electronic Systems Design.
    Design and fabrication of multiple quantum well structures for long wavelength laser diodes1999Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    InGaAsP multiple quantum well (MQW) structures emitting at1300 nm have been designed, fabricated with metal organicvapour phase epitaxy (MOVPE) and evaluated by x-ray diffraction(XRD), photoluminescence (PL) and by laser characterisation. Inaddition the structures were subject to scanning probemicroscopy (STM/AFM) and direct carrier transport measurements.The design goal was to fabricate MQWs with a large number ofperiods, more than a typical 4-5, which is essential forhigh-modulation-speed lasers and vertical cavity surfaceemitting lasers (VCSELs). The demand for temperature-stableproperties has commonly resulted in MQW designs with highbarrier bandgaps for achieving a high electron confinement.This work has shown by laser-simulations that the consequenceof high barriers is a slow hole-transport, which accumulatesthe holes and consequently also the electrons due toCoulomb-attraction in the wells closest to the p-side. Themajor effect of the non-uniform carrier distribution is highnon-radiative carrier losses, degrading the laser performance.The simulations show that by reducing the barrier heights, amore uniform carrier distribution can be achieved andconsequently reduced non-radiative losses. Directhole-transport measurements over a MQW showed a cleardependence of the hole-transfer time over the MQW on thehole-confinement energy. The device performance of lasers wasimproved considerably in terms of lower threshold currents,higher optical power outputs and higher temperature-stabilitywhen optimised barrier bandgaps were used, even if theelectron-confinement is reduced. Another conclusion from thisstudy was that for MQW-structures emitting at 1300 nm, aconstant fraction of Ga in both wells and barriers results inexcellent materials characteristics compared to constant-As orInAsP (wells)-InGaAsP (barriers) alternatives.

    Keywords:InGaAsP, multiple quantum well, materialsfabrication, semiconductor laser, carrier transport,characteristic temperature, 1300 nm.

  • 138.
    Strak, Adam
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Gothenberg, Andreas
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Analysis of clock jitter effects in wideband sigma-delta modulators for RF-applications2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, no 03-feb, p. 223-236Article in journal (Refereed)
    Abstract [en]

    This paper presents a theoretical overview and analysis of clock jitter in a switched capacitor (SC) Sigma-Delta (SigmaDelta) Analog-to-Digital Converter ( ADC). We start by defining three different types of jitter effects and proceed to analyze their impact, both mathematically and by simulations. The main jitter assumption throughout this analysis is that it is stochastic white Gaussian noise. Using this assumption, the SigmaDelta performance is characterized in terms of Signal-to-Jitter-Noise-Ratio (SJNR) for each jitter effect. Non-uniform sampling effects have, to some extent, been characterized in litterature ( S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Converters - Theory, Design and Simulation, IEEE Press, NewJersey, 1997). However, varying phase-length effects are also a main focus in this work since they can have a significant impact on the total ADC performance depending on settling accuracy and characteristic. Furthermore, because SC circuits usually operate on a two-phase clock, jitter may give rise to a secondary effect, phase overlap, which does not appear when dealing with a single-phase clock. This effect severely degrades the resolution of a SigmaDelta and therefore a thorough understanding of the interaction of jitter on the two phases is necessary.

  • 139.
    Strak, Adam
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Suppression of jitter effects in A/D converters through sigma-delta sampling2004In: VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS / [ed] Smailagic, A; Bayoumi, M, LOS ALAMITOS: IEEE COMPUTER SOC , 2004, p. 121-126Conference paper (Refereed)
    Abstract [en]

    This paper describes a new sampling circuit topology that shapes clock jitter induced sampling noise in much the same way a SigmaDelta Analog-to-Digital Converter (ADC) shapes quantization noise. The sampling circuit consists of a continuous-time (CT) integrator followed by two switches. One for the output and one for the feedback. Its intended use is as a front-end for ADCs where jitter is a concern, e.g. wideband or bandpass SigmaDelta ADCs. The main benefit of this converter is that its sampling noise due to jitter is, to a large extent, independent of the signal frequency. This means that as the signal frequency increases, and traditional sampling circuits' performance deteriorates, the proposed SigmaDelta sampler offers a maintained high sampling accuracy. Calculations and simulations in this paper show that the SigmaDelta sampler has higher performance than a traditional sampling circuit (circuit noise not included), if the main part of the signal power is in the upper portion of the frequency band. The maximum benefit, assuming the input is a single sinusoidal tone, is approximately 4.75 dB in signal-to-jitter-noise ratio (SJNR).

  • 140.
    Svantesson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Dynamic process management in SDL to VHDL synthesis2000Licentiate thesis, monograph (Other scientific)
  • 141.
    Svantesson, Bengt
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Postula, Adam
    Department of CSEE, University of Queensland.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts1996In: : VLSI in Mobile Communication, 1996, p. 23-28Conference paper (Refereed)
    Abstract [en]

    Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: Characterise CMISTs from the synthesis viewpoint; Contend that the synthesis demands of CMISTs can be met within the framework of a general purpose High-level synthesis tool, by making parts of it adaptive to the input, rather than develop a complete tool for a particular type of application; Present an allocation strategy that automatically adapts for CMISTs; Present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; Present the results of applying the synthesis methodology to the OAM as a test case. The results are compared with the result from two commercial High-level synthesis tool; Prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our obtained by designing manually at register-transfer level; The results is also compared with the results from two commercial HLS tools.

  • 142.
    Svantesson, Bengt
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Postula, Adam
    Dept. of Electrical and Computer Engineering, University of Queensland.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Modeling and Synthesis of Operational and Management System (OAM) of ATM Switch Fabrics1995Conference paper (Refereed)
  • 143.
    Svantesson, Bengt
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    Ellervee, Peeter
    Postula, Adam
    Univ. of Queensland.
    Öberg, Johnny
    Jantsch, Axel
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Modelling and Syn­thesis of Operational and Management System (OAM) of ATM Switch Fabrics1995Conference paper (Refereed)
  • 144.
    Svantesson, Bengt
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Shashi
    Indian Institute of Technology.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    A methodology and algorithms for efficient interprocess communication synthesis from system description in SDL1998In: VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on, 1998, p. 78-84Conference paper (Refereed)
    Abstract [en]

    This paper discusses a methodology and algorithms for efficient hardware synthesis of inter-process communication in systems described in SDL. The basic idea of our approach is to implement an SDL process by two hardware blocks, namely Computation Block and Communication Block. The Computation Block implements the data computation functions of the process as an Extended FSM (EFSM). The Communication Block implements the communication of the process with other processes. We give an algorithm to classify the communication requirements of the process and have an efficient implementation for it. Our scheme also has a supervisor block for every SDL block to manage interprocess communication. Our methodology supports multiple instances of the processes and dynamic processes. In our scheme, a single copy of hardware (Compute block) is shared among multiple copies of a process within a block which leads to efficient hardware implementation

  • 145.
    Svantesson, Bengt
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Shashi
    Indian Institute of Technology.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL1998In: Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998Conference paper (Refereed)
  • 146.
    Svantesson, Bengt
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Shashi
    Indian Institute of Technology.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    An Efficient Scheme for Hardware Implementation of Processes with Multiple Active Instances1997In: Proc. of IEEE NORCHIP, 1997Conference paper (Refereed)
  • 147.
    Söderström, David
    KTH, Superseded Departments, Electronic Systems Design.
    Epitaxy, analysis and application of semi-insulating III-V materials2001Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Semi-insulating (SI) III-V materials can provide electricalisolation for integration and capacitance minimisation for highspeed operation. Compared to the polyimides, these can offerbetter thermal conduction. Ever since the fabrication of thefirst SI III-V materials, transition metals have been utilisedas deep impurities to impart SI properties. Despite the longevolution of certain SI materials, several material propertiesare not entirely established, particularly when 3d-transitionmetals are used as deep impurities. Among all the SI III-Vmaterials, InP:Fe is widely employed in research laboratoriesand industrial production, although it suffers from diffusionof Fe and deficient hole blocking characteristics. Theobjective of this thesis is to gain more insight into materialproperties of SI materials in general and InP:Fe in particularand to exploit them in device fabrication. Attempts have beenmade to grow Ru doped InP using low-pressure hydride vapourphase epitaxy (LP-HVPE). The superior thermal stability andhole blocking capacity of Ru with respect to Fe motivates theinvestigation of InP:Ru. Superior regrowth capability ofLP-HVPE with respect to other techniques motivates its use. Itwas found that InP:Ru was close to the SI behaviour probablybecause of insufficient activation of Ru. To overcome theproblem of low activation, codoped InP:Ru,Fe was grown andfound to yield excellent current blocking behaviour under bothelectron and hole current injection. The codoped structure isalso superior to InP:Fe as regards Fe/Zn interdiffusion.

    A very direct method, time-resolved photoluminescence hasbeen used to study carrier trapping, which enabled theextraction of capture cross sections of Fe in InP:Fe andGaInP:Fe. The dependence of carrier trapping times on Feconcentration is found to be in very good agreement withresistivity measurements.

    Modelling of carrier injection in n/SI/n and p/SI/pconfigurations has been carried out. Our modelling indicatesthat deep acceptor concentration and its energy level have adefinite influence on the resistivity of n/SI/n and p/SI/pstructures, in agreement with the observed experimental resultson InP:Fe, InP:Ru and InP:Ru,Fe. Simulated results for InPcodoped with Fe and Ti are also in agreement with the publishedresults available in the literature.

    To demonstrate the application of SI-InP, buriedheterostructure lasers with good performance have been realisedusing HVPE regrowth of InP:Fe.

    Keywords: InP, GaInP, semi-insulating materials, irondoping, ruthenium doping, HVPE, diffusion, deep levels, capturecross sections, resistivity analysis, buried heterostructurelaser

  • 148.
    Tammemäe, Kalle
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    O’Nils, Mattias
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems1996In: Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 1996, p. 193-199Conference paper (Refereed)
  • 149.
    Tammemäe, Kalle
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    O’Nils, Mattias
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    AKKA : A Codesgn Environment1995Conference paper (Refereed)
  • 150.
    Tammemäe, Kalle
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    O’Nils, Mattias
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    AKKA: a tool-kit for cosynthesis and prototyping1996In: Hardware-Software Cosynthesis for Reconfigurable Systems (Digest No 1996/036), IEE Colloquium on:  , 1996, p. 8-1Conference paper (Refereed)
    Abstract [en]

    Shortened design and lifetime of embedded systems has motivated active research in HW/SW co-design area, together with evolution of relatively long-life of reconfigurable HW. In this paper we present AKKA-a set of tools for design space exploration, co-simulation and co-synthesis with two industrial examples from the telecommunication field-Maintenance functionality of the ATM protocol and Channel decoder functionality of a D-AMPS base station. For fast prototyping we have selected Xilinx XC4013 FPGA based board from Virtual Computer Corporation. The board is connected to the system bus (SBus) of the host computer

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