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  • 101.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effect of Be segregation on NiSi/Si Schottky barrier heights2011In: Solid-State Device Research Conference (ESSDERC), 2011Conference paper (Refereed)
    Abstract [en]

    The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process. The SBH modulation was found to be strongly dependent on the silicidation temperature, with a minimum barrier to the valence band Φbp=0.28±0.02 eV, for diodes formed at 600 °C. SIMS analysis show the Be dose left at the interface is very low. With such a low dose, modulation cannot be caused by an interface dipole. However, the results can be explained assuming a thin (~4-5 nm) layer of activated Be close to the interface.

  • 102.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 6, p. 1585-1591Article in journal (Refereed)
    Abstract [en]

    The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (rho(c)). For low rho(c), the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted rho(c). In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of rho(c) extraction. This is accomplished by generalized error propagation curves that show the error in rho(c) caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where rho(c) < 5.10(-8) Omega.cm(2) has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to similar to 50% error in the estimation of rho(c).

  • 103.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Palestri, P.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Selmi, L.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simulation of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo model2013In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 79, p. 172-178Article in journal (Refereed)
    Abstract [en]

    We present a simple and efficient approach to implement Schottky barrier contacts in a Multi-subband Monte Carlo simulator by using the subband smoothening technique to mimic tunneling at the Schottky junction. In the absence of scattering, simulation results for Schottky barrier MOSFETs are in agreement with ballistic Non-Equilibrium Green's Functions calculations. We then include the most relevant scattering mechanisms, and apply the model to the study of double gate Schottky barrier MOSFETs representative of the ITRS 2015 high performance device. Results show that a Schottky barrier height of less than approximately 0.15 eV is required to outperform the doped source/drain structure.

  • 104.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Palestri, Pierpaolo
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Selmi, Luca
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Investigation of the performance of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo modelArticle in journal (Other academic)
  • 105.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Palestri, Pierpaolo
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Selmi, Luca
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Multi-subband Monte Carlo simulation of fully-depleted silicon-on-insulator Schottky barrier MOSFETs2010In: 11th International Conference on Ultimate Integration of Silicon (ULIS), 2010, 2010Conference paper (Refereed)
  • 106.
    Hallén, Anders
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Nawaz, Muhammad
    Zaring, Carina
    Usman, Muhammad
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Low-Temperature Annealing of Radiation-Induced Degradation in 4H-SiC Bipolar Junction Transistors2010In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 31, no 7, p. 707-709Article in journal (Refereed)
    Abstract [en]

    Radiation hardness is tested for 4H-SiC n-p-n bipolar junction transistors designed for 1200-V breakdown voltage by implanting MeV protons and carbon ions at different doses and energies. The current gain is found to be a very sensitive parameter, and a fluence as low as 1 x 107 cm(-2) of 10 MeV C-12 can be clearly detected in the forward-output characteristics, I-C(V-CE). At this low dose, no influence of ion radiation is seen in the open-collector characteristics, I-B(V-EB), or the reverse bias leakage and breakdown properties. Moreover, by annealing the implanted devices at 420 degrees C for 30 min, a complete recovery of the electrical characteristics is accomplished.

  • 107.
    Haralson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Johansson, T
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Influence of self heating in a BiCMOS on SOI technology2004In: ESSCIRC 2004: Proceedings of the 34th European Solid-State Device Research Conference, NEW YORK: IEEE , 2004, p. 337-340Conference paper (Refereed)
    Abstract [en]

    Self heating in a 0.25mum BiCMOS technology with different isolation structures is characterized. Thermal resistance values for single- and multiple-emitter devices are extracted and reported. The dependence of the thermal resistance on the emitter aspect ratio is critical to take into consideration when determining the isolation scheme for devices. 2-D electro-thermal simulations are performed and compared to experimental results. The impact of metallization on the self-heating in the device is examined through simulations.

  • 108.
    Haralson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Device design for a raised extrinsic base SiGe bipolar technology2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 11-okt, p. 1927-1931Article in journal (Refereed)
    Abstract [en]

    The impact of emitter, inside spacer, and SIC lateral scaling on the AC and DC performance of a raised extrinsic base SiGe HBT has been investigated using the ISE TCAD simulation package and design of experiments methods. Strong first order effects for all three variables were observed while the interactions of the variables had a weaker effect. It was found that as the emitter size shrinks towards 0.1 mum the impact of changes to inside spacer and SIC width on the current gain increased. The response surface design led to an optimized simulated transistor featuring f(T) and f(MAX) values of 214 and 332 GHz, respectively.

  • 109.
    Haralson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sibaja-Hernandez, Arturo
    Xu, Mingwei
    Malm, Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    HRXRD analysis of SiGeC layers for BiCMOS applications2004Conference paper (Refereed)
    Abstract [en]

    The use of HRXRD for the monitoring of the dopant activation anneal through the detection of carbon outdiffusion has been demonstrated. The advantages of HRXRD over other measurement techniques for in-line epi-growth monitoring are also discussed. HRXRD reciprocal space mapping was used to study the SiGe layer stability as a function of carbon concentration for vertically scaled layers designed for high performance BiCMOS applications. It was found that as the carbon concentration is increased there is a reduction of boron cluster formation, but an increase in defect density is also observed.

  • 110.
    Haralson, Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Suvar, E.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    NiSi integration in a non-selective base SiGeCHBT process2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 03-jan, p. 245-248Article in journal (Refereed)
    Abstract [en]

    A self-aligned nickel silicide (salicide) process is integrated into a non-selective base SiGeC HBT process. The device features a unique, fully silicided base region that grows laterally under the emitter pedestal. This Ni(SiGe) formed in this base region was found to have a resistivity of 23-24 muOmega cm. A difference in the silicide thickness between the boron-doped SiGeC extrinsic base region and the in situ phosphorous-doped emitter region is observed and further analyzed and confirmed with a blanket wafer silicide study. The silicided device exhibited a current gain of 64 and HF device performance of 39 and 32 GHz for f(t) and f(MAX), respectively.

  • 111.
    Haralson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    The effect of C on emitter-base design for a single-polysilicon SiGe: C HBT with an IDP emitter2004In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Vol. 224, no 1-4, p. 330-335Article in journal (Refereed)
    Abstract [en]

    A differential epitaxy SiGe:C heterojunction bipolar junction transistor (HBT) design is reported and used to study the effect of carbon on junction formation as well as the effect of lateral design parameters on ac and dc performance. The device exhibits a high current gain (beta) of 1700 and a BVCEO of 1.8 V. The peak cutoff frequency (f(T)) and maximum oscillation frequency (f(MAX)) are 73 and 17 GHz, respectively. The effect of emitter overlap on f(T) was minimal, but it had a strong impact on dc performance. LOCOS opening size strongly impacted both ac and dc performance. In addition, the effect of carbon, base cap thickness, and rapid thermal anneal (RTA) temperature on the emitter-base (E-B) junction formation was studied.

  • 112.
    Hellström, Per-Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interfacial layer engineering using thulium silicate/germanate for high-k/metal gate MOSFETs2014In: ECS Transactions: Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, Electrochemical Society, 2014, no 6, p. 249-260Conference paper (Refereed)
    Abstract [en]

    Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO2/TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ∼20% higher electron and hole mobility than literature data on optimized SiOx/HfO2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.

  • 113.
    Hellström, Per-Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Edholm, J.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Olsen, S.
    O'Neill, A.
    Lyutovich, K.
    Oehme, M.
    Kasper, E.
    Strained-Si NMOSFETs on thin 200 nm virtual substrates2005Conference paper (Refereed)
  • 114.
    Hellström, Per-Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of Silicon Nanowires with CMOS2014In: Beyond CMOS Nanodevices 1, Wiley Blackwell , 2014, p. 65-72Chapter in book (Other academic)
    Abstract [en]

    Silicon nanowires exhibit attractive characteristics that have motivated their use as the sensor element in a biochemical sensor system. An integrated silicon nanowire and complementary metal-oxide-semiconductor (CMOS) circuit chip would allow more design freedom with respect to interaction with the full biochemical sensor system, including interaction with the electrolyte solution. The CMOS fabrication process is divided into two parts, called the front-end-of-line (FEOL) and back-end-of-line (BEOL) processing. A CMOS process that allows the integration of silicon nanowires, as described in this chapter offers a vast amount of design opportunities to enhance the performance of the silicon nanowire-based sensor. The chapter describes a sensor design that allows measurement of the conductance variations of biosensitive silicon nanowires in a serial manner by using on-chip integrated CMOS circuitry. Integration of silicon nanowires can also be achieved by defining the silicon nanowires in the silicon layer of a SOI wafer.

  • 115.
    Henkel, Christoph
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bethge, O.
    Stöger-Pollach, M.
    Bertagnolli, E.
    Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks2011In: European Solid-State Device Res. Conf., 2011, p. 75-78Conference paper (Refereed)
    Abstract [en]

    The current work is discussing the surface passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition for use in Ge-based MOSFET devices. The improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing agencies in presence of thin Pt cap layers are investigated. The results suggest the formation of thin intermixed La xGeyOz interfacial layers with thicknesses controllable by oxidation time. An additional reduction treatment further improves the electrical properties of the gate dielectrics in contact to the Ge substrate. The scaling potential of the respective layered gate dielectrics used in MOS-based device structures is discussed. As a result low interface trap densities of the ALD deposited La2O3/ZrO2 layers on (100) Ge down to 3·1011 eV-1 cm -2 are demonstrated. A trade-off between improved interface trap density and equivalent oxide thickness is found.

  • 116.
    Henkel, Christoph
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Stoeger-Pollach, Michael
    Bethge, Ole
    Bertagnolli, Emmerich
    Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 7-12Article in journal (Refereed)
    Abstract [en]

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

  • 117. Hong, J.
    et al.
    Shul, R. J.
    Zhang, L.
    Lester, L. F.
    Cho, H.
    Hahn, Y. B.
    Hays, D. C.
    Jung, K. B.
    Pearton, S. J.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Plasma chemistries for high density plasma etching of SiC1999In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 28, no 3, p. 196-201Article in journal (Refereed)
    Abstract [en]

    A variety of different plasma chemistries, including SF6, Cl2, ICI, and IBr, have been examined for dry etching of 6H-SiC in high ion density plasma tools (inductively coupled plasma and electron cyclotron resonance). Rates up to 4500 angstroms·min-1 were obtained for SF6 plasmas, while much lower rates (≀800 angstroms·min-1) were achieved with Cl2, ICI, and IBr. The F2-based chemistries have poor selectivity for SiC over photoresist masks (typically 0.4-0.5), but Ni masks are more robust, and allow etch depths ≥10 Όm in the SiC. A micromachining process (sequential etch/deposition steps) designed for Si produces relatively low etch rates (&lt;2,000 angstroms·min-1) for SiC.

  • 118.
    Hou, Shuoben
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    4H-SiC PIN diode as high temperature multifunction sensor2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Ltd , 2017, p. 630-633Conference paper (Refereed)
    Abstract [en]

    An in-house fabricated 4H-SiC PIN diode that has both optical sensing and temperature sensing functions from room temperature (RT) to 550 ºC is presented. The two sensing functions can be simply converted from one to the other by switching the bias voltage on the diode. The optical responsivity of the diode at 365 nm is 31.8 mA/W at 550 ºC. The temperature sensitivity of the diode is 2.7 mV/ºC at the forward current of 1 μA.

  • 119.
    Hou, Shuoben
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    550 degrees C 4H-SiC p-i-n Photodiode Array With Two-Layer Metallization2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 37, no 12, p. 1594-1596Article in journal (Refereed)
    Abstract [en]

    The p-i-n ultraviolet (UV) photodiodes based on 4H-SiC have been fabricated and characterized from room temperature (RT) to 550 degrees C. Due to bandgap narrowing at higher temperatures, the photocurrent of the photodiode increases by 9 times at 365 nm and reduces by 2.6 times at 275 nm from RT to 550 degrees C. Moreover, a 4H-SiC p-i-n photodiode array has been fabricated. Each column and row of the array is separately connected by two-layer metallization.

  • 120.
    Hou, Shuoben
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode2019In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 1, p. 51-54Article in journal (Refereed)
    Abstract [en]

    This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

  • 121.
    Hou, Shuoben
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Scaling and modeling of high temperature 4H-SiC p-i-n photodiodes2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 139-145, article id 8240922Article in journal (Refereed)
    Abstract [en]

    4H-SiC p-i-n photodiodes with various mesa areas (40,000μm2, 2500μm2, 1600μm2, and 400μm2) have been fabricated. Both C-V and I-V characteristics of the photodiodes have been measured at room temperature, 200 °C, 400 °C, and 500 °C. The capacitance and photo current (at 365 nm) of the photodiodes are directly proportional to the area. However, the dark current density increases as the device is scaled down due to the perimeter surface recombination effect. The photo to dark current ratio at the full depletion voltage of the intrinsic layer (-2.7 V) of the photodiode at 500 °C decreases 7 times as the size of the photodiode scales down 100 times. The static and dynamic behavior of the photodiodes are modeled with SPICE parameters at the four temperatures.

  • 122.
    Hou, Shuoben
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Shakir, Muhammad
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits2019In: Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019, IEEE, 2019Conference paper (Refereed)
  • 123. Huang, J.
    et al.
    Wang, L.
    Wen, J.
    Wang, Y.
    Lin, C.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Growth of SiC thin films on (100) and (111) silicon by pulsed laser deposition combined with a vacuum annealing process1999In: Materials Research Society Symposium - Proceedings, San Francisco, CA, USA, 1999, Vol. 572, no Warrendale, PA, United States, p. 207-212Conference paper (Refereed)
    Abstract [en]

    Crystalline 3C-SiC thin films were successfully grown on (100) and (111) Si substrates by using ArF pulsed laser ablation from a SiC ceramic target combined with a vacuum annealing process. X-ray diffraction (XRD) and Fourier transform infrared spectroscopy (FTIR) were employed to study the effect of annealing on the structure of thin films deposited at 800°C. It was demonstrated that vacuum annealing could transform the amorphous SiC films into crystalline phase and that the crystallinity was strongly dependent on the annealing temperature. For the samples deposited on (100) and (111) Si, the optimum annealing temperatures were 980 and 920°C, respectively. Scanning electron microscope (SEM) micrographs exhibited different characteristic microstructure for the (100) and (111) Si cases, similar to that observed for the carbonization layer initially formed in chemical vapor deposition of SiC films on Si. This also showed the presence of the epitaxial relationship of 3C-SiC[100]//Si[100] and 3C-SiC[111]//Si[111] in the direction of growth.

  • 124.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Edholm, Jonas
    Lu, J.
    Uppsala University, Ångström Laboratory.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A robust spacer gate process for deca-nanometer high-frequency MOSFETs2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 3, p. 434-439Article in journal (Refereed)
    Abstract [en]

    This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

  • 125.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Baubinas, R.
    Matukas, J.
    Palenskis, V.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Application of selective epitaxy for formation of ultra shallow SiGe-based junctions2004In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 114-115, no SPEC. ISS, p. 180-183Article in journal (Refereed)
    Abstract [en]

    Selective epitaxial growth (SEG) of B-, P- and As-doped Si1-xGex (0.12 < x < 0.26) layers on patterned substrates, aimed for source/drain ultra shallow junctions was investigated. The SiGe layers were deposited selectively on Si surface that is either unprocessed or previously in situ etched by HCl in the same run in a reduced pressure chemical vapor deposition reactor. In these investigations selectivity mode, pattern dependency (loading effect), defect generation and dopant incorporation in SiGe layers have been discussed. It was demonstrated that the growth rate increased in presence of B in SiGe while it decreased for P- and As-doped layers. The amount of Ge was constant for B-doped samples while it increased for As- and P-doped SiGe layers. The epitaxial quality was dependent on the Ge amount, growth rate and dopant concentration. The selectivity mode of the growth was dependent on B partial pressure, however, no effect was observed for P- or As-doping in SiGe layers. A resistivity value of similar to10(-3) Omega cm was obtained for B- and P-doped SiGe layers with optimized growth parameters.

  • 126.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Oehme, M.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Werner, J.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Lyutovich, K.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Kasper, E.
    Institut für Halbleitertechnik Universität, Stuttgart, Germany.
    Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates2007In: ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference 2008, 2007, p. 319-322Conference paper (Refereed)
    Abstract [en]

    We present a comprehensive study of biaxially strained (up to similar to 3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage for the relaxed SiGe substrates compared to conventional implantation. The source to drain leakage in 80 nm devices was effectively reduced by increment of channel doping and rotation of the channel direction.

  • 127.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Parent, A.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Incorporation of boron in SiGe(C) epitaxial layers grown by reduced pressure chemical vapor deposition2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 03-jan, p. 97-101Article in journal (Refereed)
    Abstract [en]

    In this paper the strain and electrical properties of epitaxial in situ B-doped (10(18)-10(21) cm(-3)) SiGeC layers (23, 28% Ge and 0, 0.5% C) has been investigated. The growth rate was shown to have a significant increase at 3 x 10(-2) mTorr diborane partial pressure. This point coincides with an enhancement in boron incorporation, which was explained by the strain compensation effect of boron in the highly strained SiGeC layers. In these samples, the total Ge and C content was shown to remain constant with increasing diborane partial pressure. The substitutional/active dopant concentration in SiGe layers was obtained by high-resolution X-ray diffraction by measuring the strain compensation effect of boron. The interaction between C and B in SiGe matrix was also investigated. This was compared with the active dopant concentration obtained from Hall measurements in order to achieve a Hall scattering factor of 0.3-0.7 for dopant concentrations between 3 x 10(18) and 5 x 10(21) cm(-3). The resistivity values of these layers were in the range 2 x 10(-2) -4 x 10(-4) Omega cm. Finally, it was shown that boron atoms in SiGeC layers locate preferably at substitutional sites in contrary to carbon atoms at both substitutional and interstitial sites.

  • 128.
    Hållstedt, Julius.
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Parent, Arnaud
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Strain and electrical characterization of boron-doped SiGeC layers grown by chemical vapor deposition2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 31-33Article in journal (Refereed)
    Abstract [en]

    Incorporation, induced strain and electrical properties of boron and carbon in Si1-x-yGexCy epitaxial layers (x = 0.23 and 0.28 with y = 0 and 0.005) grown by chemical vapour deposition (CVD) have been studied. The boron concentration in the epitaxial layers was in the range of 3 x 10(18)-1 x 10(21) cm(-3). The growth rate enhanced weakly by increasing boron partial pressure up to 0.002 mtorr ( corresponding to 2 x 10(19) cm(-3)) where a significant increase in deposition rate was observed. In SiGeC layers, the active boron concentration was obtained from the strain compensation amount. It was also found that the boron atoms have a tendency to locate at substitutional sites more preferentially compared to carbon. The incorporation of boron in SiGeC layers was clearly improved in the range 2 x 10(19)-3 x 10(20) cm(-3). These investigations also enabled an estimation of the Hall scattering factor of the SiGeC layers. A comparison between our results with the previous theoretical calculations showed a good agreement. This created the possibility to evaluate the drift mobility in our samples.

  • 129.
    Hållstedt, Julius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Menon, Cyril
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Methods to reduce the loading effect in selective and non-selective epitaxial growth of sigec layers2004In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 109, no 03-jan, p. 122-126Article in journal (Refereed)
    Abstract [en]

    Various methods to reduce both global and local loading effect during non-selective and selective epitaxial growth of Si1-x-yGexCy (0.09 less than or equal to x less than or equal to 0.28 and 0 less than or equal to y less than or equal to 0.01) layers have been proposed. Evaluation of the proposed solutions for issues such as defect generation and the possibility for integration in device structures have been performed. The key point in these methods is based on reduction of surface diffusion of the adsorbed species on the oxide. In non-selective epitaxy, this was achieved by introducing a thin silicon polycrystalline seed layer on the oxide prior to Si1-x-yGexCy deposition. The thickness of this seed layer had a crucial role on both the global and local loading effect, and also on the epitaxial quality. Higher carbon content (y greater than or equal to 0.006) in Si1-x-yGexCy layers had no noticeable influence on the loading effect, however, the defect density was clearly increased in these layers. In selective epitaxy case, introducing square polycrystalline Si stripes around the oxide openings acting as diffusion barriers have reduced the loading effect effectively. Meanwhile, using Si nitride stripes showed no visible effect on Si1-x-yGexCy layer profile. Further decrease in loading effect can be performed by increasing the HCl partial pressure during epitaxy. Chemical-mechanical polishing (CMP) was performed to remove the polycrystalline stripe on the oxide.

  • 130.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels2006In: ECS Transactions, ISSN 1938-5862, E-ISSN 1938-6737, Vol. 3, no 7, p. 67-72Article in journal (Refereed)
    Abstract [en]

    State of the art bulk and fully depleted SOI Si and SiGe channel pMOSFET devices with gate lengths ranging from 0.1 to 200 μm were fabricated and analyzed in terms of drain current drivability, mobility and noise performance. In general the SOI devices demonstrated superior mobility and significantly reduced I/f noise compared to bulk devices maintaining a well controlled short channel effects due to the ultra thin body.

  • 131.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels2006In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 6, p. 466-468Article in journal (Refereed)
    Abstract [en]

    The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

  • 132. Illarionov, Y.
    et al.
    Waltl, M.
    Smith, AD
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, M.
    Grasser, T.
    Interplay between hot carrier and bias stress components in single-layer double-gated graphene field-effect transistors2015In: European Solid-State Device Research Conference, IEEE , 2015, p. 172-175Conference paper (Refereed)
    Abstract [en]

    We examine the interplay between the degradations associated with the bias-temperature instability (BTI) and hot carrier degradation (HCD) in single-layer double-gated graphene field-effect transistors (GFETs). Depending on the polarity of the applied BTI stress, the HCD component acting in conjuction can either accelerate or compensate the degradation. The related phenomena are studied in detail at different temperatures. Our results show that the variations of the charged trap density and carrier mobility induced by both contributions are correlated. Moreover, the electron/hole mobility behaviour agrees with the previously reported attractive/repulsive scattering asymmetry. © 2015 IEEE.

  • 133. Illarionov, Yu Yu
    et al.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, S.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mueller, T.
    Lemme, M. C.
    Grasser, T.
    Bias-temperature instability in single-layer graphene field-effect transistors2014In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 105, no 14, p. 143507-Article in journal (Refereed)
    Abstract [en]

    We present a detailed analysis of the bias-temperature instability (BTI) of single-layer graphene field-effect transistors. Both negative BTI and positive BTI can be benchmarked using models developed for Si technologies. In particular, recovery follows the universal relaxation trend and can be described using the established capture/emission time map approach. We thereby propose a general methodology for assessing the reliability of graphene/dielectric interfaces, which are essential building blocks of graphene devices. (C) 2014 AIP Publishing LLC.

  • 134. Illarionov, Yury
    et al.
    Smith, Anderson
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mueller, Thomas
    Lemme, Max
    Grasser, Tibor
    Hot-Carrier Degradation and Bias-Temperature Instability in Single-Layer Graphene Field-Effect Transistors: Similarities and Differences2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3876-3881Article in journal (Refereed)
    Abstract [en]

    We present a detailed analysis of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs) and compare those findings with the bias-temperature instability (BTI). Our results show that the HCD in GFETs is recoverable, similar to its BTI counterpart. Moreover, both the degradation mechanisms strongly interact. Particular attention is paid to the dynamics of HCD recovery, which can be well fitted with the capture/emission time (CET) map model and the universal relaxation function for some stress conditions, quite similar to the BTI in both GFETs and Si technologies. The main result of this paper is an extension of our systematic method for benchmarking new graphene technologies for the case of HCD.

  • 135. Illarionov, Yu.Yu.
    et al.
    Smith, Anderson David
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mueller, T.
    Lemme, M. C.
    Grasser, T.
    Bias-temperature instability in single-layer graphene field-effect transistors: A reliability challenge2014In: 2014 Silicon Nanoelectronics Workshop, SNW 2014, Institute of Electrical and Electronics Engineers (IEEE), 2014Conference paper (Refereed)
    Abstract [en]

    We present a detailed analysis of the bias-temperature instability (BTI) of single-layer graphene field-effect transistors (GFETs). We demonstrate that the dynamics can be systematically studied when the degradation is expressed in terms of a Dirac point voltage shift. Under these prerequisites it is possible to understand and benchmark both NBTI and PBTI using models previously developed for Si technologies. In particular, we show that the capture/emission time (CET) map approach can be also applied to GFETs and that recovery in GFETs follows the same universal relaxation trend as their Si counterparts. While the measured defect densities can still be considerably larger than those known from Si technology, the dynamics of BTI are in general comparable, allowing for quantitative benchmarking of the graphene/dielectric interface quality.

  • 136. Illarionov, Yu.Yu.
    et al.
    Waltl, M.
    Smith, A. D.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mueller, T.
    Lemme, M. C.
    Grasser, T.
    Hot-carrier degradation in single-layer double-gated graphene field-effect transistors2015In: IEEE International Reliability Physics Symposium Proceedings, IEEE conference proceedings, 2015, p. XT21-XT26Conference paper (Refereed)
    Abstract [en]

    We report a first study of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs). Our results show that HCD in GFETs is recoverable, similarly to the bias-temperature instability (BTI). Depending on the top gate bias polarity, the presence of HCD may either accelerate or suppress BTI. Contrary to BTI, which mainly results in a change of the charged trap density in the oxide, HCD also leads to a mobility degradation which strongly correlates with the magnitude of the applied stress.

  • 137. Illarionov, Yu.Yu.
    et al.
    Waltl, M.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, M. C.
    Crasser, T.
    Impact of hot carrier stress on the defect density and mobility in double-gated graphene field-effect transistors2015In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 81-84Conference paper (Refereed)
    Abstract [en]

    We study the impact of hot-carrier degradation (HCD) on the performance of graphene field-effect transistors (GFETs) for different polarities of HC and bias stress. Our results show that the impact of HCD consists in a change of both charged defect density and carrier mobility. At the same time, the mobility degradation agrees with an attractive/repulsive scattering asymmetry and can be understood based on the analysis of the defect density variation.

  • 138. Illarionov, Y.Yu.
    et al.
    Waltl, M.
    Smith, Anderson David
    KTH, School of Information and Communication Technology (ICT).
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, M. C.
    Grasser, T.
    Bias-temperature instability on the back gate of single-layer double-gated graphene field-effect transistors2016In: Japanese Journal of Applied Physics, ISSN 0021-4922, E-ISSN 1347-4065, Vol. 55, no 4, article id 04EP03Article in journal (Refereed)
    Abstract [en]

    We study the positive and negative bias-temperature instabilities (PBTI and NBTI) on the back gate of single-layer double-gated graphene fieldeffect transistors (GFETs). By analyzing the resulting degradation at different stress times and oxide fields we show that there is a significant asymmetry between PBTI and NBTI with respect to their dependences on these parameters. Finally, we compare the results obtained on the high-k top gate and SiO2 back gate of the same device and show that SiO2 gate is more stable with respect to BTI.

  • 139.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    MOSFETs with recessed SiGe Source/Drain junctions formed by selective etching and growth2004In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775, Vol. 7, no 4, p. G53-G55Article in journal (Refereed)
    Abstract [en]

    A source/drain extension process that uses HCl etching followed by selective growth of in situ B-doped SiGe is demonstrated. The two key process steps, etching and growth, are integrated by performing them consecutively in the same chemical vapor deposition reactor. The technique has the potential to solve end-of-the-roadmap requirements on junction depth, junction abruptness, and active doping concentration.

  • 140.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Selective Si etching using HCl vapor2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 107-109Article in journal (Refereed)
    Abstract [en]

    Selective Si etching using HCl in a reduced pressure chemical vapor deposition reactor in the temperature range 800-1000 degrees C is investigated. At 900 degrees C, the etch process is anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. This behavior indicates that the etch process is limited by surface reaction, since the etch rate in the directions with higher atomic concentration is lower. When the temperature is decreased to 800 degrees C, etch pits occur. A more isotropic etch is obtained at 1000 degrees C, however at this temperature the masking oxide is attacked and the etch surface is rough. Thus the temperature has to be confined to a narrow window to yield desirable properties under the present process conditions.

  • 141.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Process integration of a new method for formation of shallow junctions in MOSFET structures using recessed and selectively regrown Si1-xGex2004Conference paper (Refereed)
    Abstract [en]

    Process integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The proposed concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. Nitride residues and surface damage originating from RIE are shown to be detrimental for the epitaxial quality.

  • 142.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Recessed and epitaxially regrown SiGe(B) source/drain junctions with Ni salicide contacts2004In: Silicon Front-End Junction Formation-Physics And Technology / [ed] Pichler, P; Claverie, A; Lindsay, R; Orlowski, M; Windl, W, 2004, Vol. 810, p. 49-54Conference paper (Refereed)
    Abstract [en]

    Integration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1-xGex are presented. The concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. When integrated in the PMOS process flow, the resulting Si1-xGex layer is very rough. Several possible causes for low quality epitaxy are discussed and improvements are proposed. It is suggested that the dopant type and/or concentration in the silicon substrate can have an effect on the process.

  • 143.
    Isheden, Christian
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    pMOSFETs with recessed and selectively regrown Si1-xGex source/drain junctions2005In: Materials Science in Semiconductor Processing, ISSN 1369-8001, E-ISSN 1873-4081, Vol. 8, no 1-3, p. 359-362Article in journal (Refereed)
    Abstract [en]

    A new source/drain formation concept based on selective Si etching followed by selective regrowth of in situ B-doped Si(1-x)Ge(x)is presented. Both process steps are performed in the same reactor to preserve the gate oxide. Well-behaved transistors are demonstrated with a negligibly low gate-to-substrate leakage current.

  • 144.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Suvar, Erdal
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Formation of shallow junctions by HCl-based Si etch followed by selective epitaxy of B-doped Si1-xGex in RPCVD2004In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 151, no 6, p. C365-C368Article in journal (Refereed)
    Abstract [en]

    Formation of shallow source/drain junctions by using HCl-based Si etch followed by selective deposition of in situ heavily B-doped SiGe in a reduced pressure chemical vapor deposition reactor is presented. The etching parameters were optimized to obtain a smooth surface prior to deposition of the SiGe layers. In the epitaxy process, SiGe layers with a resistivity of 5 x 10(-4) Omega cm were obtained by tuning the partial pressure of the B and Ge precursors. A problem with selectivity in the epitaxy step was encountered when combing the etch and growth processes, but a practical solution is presented. Integration issues such as loading effect, pile-up, and defect generation have also been investigated.

  • 145.
    Isheden, Christian
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Seger, Johan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Formation of Ni mono-germanosilicide on heavily B-doped epitaxial SiGe for ultra-shallow source/drain contacts2003In: Materials Research Society Symposium Proceedings, ISSN 0272-9172, E-ISSN 1946-4274, Vol. 745, p. 117-122Article in journal (Refereed)
    Abstract [en]

    The formation of Ni germanosilicides during solid-state interaction between Ni and heavily B-doped strained epitaxial Si1-xGex films with x=0.18, 0.32 and 0.37 is studied. No NiSi2 is found in these samples even after annealing at 850 degreesC, which can be compared to the formation of NiSi2 at 750 T on Si(I 00). Resistance and diffraction studies for the Si0.82Ge0.18 sample indicate that NiSi0.82Ge0.18 forms and the NiSi0.82Ge0.18/Si0.82Ge0.18 structure is stable from 400 to 700 degreesC. For the NiSi1-uGeu formed in all Si1-xGex samples, where u can be different from x, a strong film texturing is observed. When the Ge fraction is increased from 18 at.% to 32-37 at.%, the morphological stability of the film is degraded and a substantial increase in sheet resistance occurs already at 600 degreesC. The contact resistivity for the NiSi0.8Ge0.2/Si0.8Ge0.2 interface formed at 550 T is determined as 1.2x10(-7) Omegacm(2), which satisfies the ITRS contact resistivity requirement for the 70 nm technology node.

  • 146.
    Jamshidi, Asghar
    et al.
    KTH.
    Noroozi, Mohammad
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Moeen, M.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hamawandi, Bejan
    KTH.
    Lu, J.
    Hultman, L.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Growth of GeSnSiC layers for photonic applications2013In: Surface & Coatings Technology, ISSN 0257-8972, E-ISSN 1879-3347, Vol. 230, p. 106-110Article in journal (Refereed)
    Abstract [en]

    This work presents epitaxial growth of intrinsic and doped GeSnSiC layers using Ge2H6, SnCl4, CH3SiH3, B2H6, PH3 and Si2H6 deposited at 290-380 degrees C on strain relaxed Ge buffer layer or Si substrate by using reduced pressure chemical vapor deposition (RPCVD) technique. The GeSnSi layers were compressively strained on Ge buffer layer and strain relaxed on Si substrate. It was demonstrated that the quality of epitaxial layers is dependent on the growth parameters and that the Sn content in epi-layers could be tailored by growth temperature. The Sn segregation caused surface roughness which was decreased by introducing Si and Si-C into Ge layer. The Sn content in GeSn was carefully determined from the mismatch, both parallel and perpendicular, to the growth direction when the Poisson ratio was calculated for a certain Ge-Sn composition. The X-ray results were excellently consistent with Rutherford Backscattered Spectroscopy (RBS). Strain relaxed GeSn layers were also used as virtual substrate to grow tensile-strained Ge layers. The Ge cap layer had low defect density and smooth surface which makes it a viable candidate material for future photonic applications.

  • 147.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon Nanowires Integrated in a Fully Depleted CMOS Process for Charge Based Biosensing2013In: ULIS 2013: The 14th International Conference on Ultimate Integration on Silicon, Incorporating the 'Technology Briefing Day', IEEE , 2013, p. 81-84Conference paper (Refereed)
    Abstract [en]

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of 32 by 32 pixel matrix (1024 pixels or test sites) and 8 input-output (I/O) pins. In each pixel single crystalline SiNW with 60 by 20 nm cross-section area is defined using sidewall transfer lithography (STL) in the SOI layer. The key advantage of the design is that 1024 individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  • 148.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon nanowires integrated with CMOS circuits for biosensing application2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 26-31Article in journal (Refereed)
    Abstract [en]

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  • 149.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellstrom, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication and characterization of silicon nanowires using STL for biosensing applications2014In: INT CONF ULTI INTEGR, ISSN 2330-5738, p. 109-112Article in journal (Refereed)
    Abstract [en]

    We present a sidewall transfer lithography (STL) process to fabricate silicon nanowires using the CMOS compatible materials SiO2, SiN and alpha-Si. The STL process is implemented using a single cluster tool for reactive ion etching (RIE) and plasma enhanced chemical vapor deposition (PECVD) with a maximum process temperature of 400 degrees C. Using three lithography masks, single and multiple silicon nanowires connected to contact areas can be defined. By optimizing layer thicknesses, RIE and deposition conformity we demonstrate wafer scale definition of 60 nm wide silicon nanowires using I-line stepper lithography. The silicon nanowires exhibit excellent characteristics for biosensing applications with subthreshold slopes of 75 mV/dec and a high on/off current ratio of more than 10(5).

  • 150.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application2018In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 9, no 11, article id 544Article in journal (Refereed)
    Abstract [en]

    Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (V-G) and backgate voltage (V-BG). The liquid potential can be monitored using the FG. We report the transfer characteristics (I-D-V-G) of N- and P-type SiRi pixels. Further, the I-D-V-G characteristics of the SiRis are studied at different V-BG. The application of V-BG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (V-TH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large V-BG (25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large V-BG to switch ON. Thus, P-type pixels exhibit excellent I-ON/I-OFF 10(6), SS of 70-80 mV/dec and V-TH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

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