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  • 101.
    Rusu, Ana
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Sigma-delta solutions for future wireless handhelds2006Inngår i: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, s. 58-61Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper addresses the different issues in the design of ADCs for future wireless handhelds. It reviews the constraints imposed on the receiver design by the low-power specifications in handhelds. The sigma-delta ADC architectures that can potentially be used for implementing future wireless handhelds are discussed in the perspective of a CMOS implementation. Finally, a 4(th) order 4bit continuous-time bandpass sigma-delta modulator capable of digitizing a WiMAX (20MHz) signal band centered at an IF of 75 MHz is presented. The simulation results shown that the proposed sigma-delta modulator can provide a SNDR of 50.1 dB and a DR of 56 dB at a sampling frequency of 500 MHz.

  • 102.
    Rusu, Ana
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A modified cascaded sigma-delta modulator with improved linearity2005Inngår i: IEEE Computer Society Annual Symposium on VLSI, Proceedings: NEW FRONTIERS IN VLSI DESIGN / [ed] Smailagic, A; Ranganathan, N, 2005, s. 77-82Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10 MHz. The proposed modulator architecture employs the 2(nd) order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A Data-Weighted-Averaging technique eliminates tones generated by the multibit digital-to-analog converter (DAC) nonlinearity improving the spurious free dynamic range (SFDR) and intermodulation distortion performance. The modulator is designed in 0.18um CMOS process and operates at 1.8V supply voltage. It achieves 62.86 dB signal-to-noise plus distortion ratio (SNDR) in the 10MHz signal bandwidth, a SFDR of 82.2dB and IMD3 of -77.5dB.

  • 103.
    Rusu, Ana
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Rodríguez de Llera González, Delia
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Ismail, Mohammed
    The Ohio State University, Columbus.
    Reconfigurable ADCs enable smart radios for 4G wireless connectivity2006Inngår i: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, nr 3, s. 6-11Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A reconfigurable analog-to-digital converter (ADC) based on a 2-2 modified cascaded sigma-delta (Σ-Δ) modulator designed for a GSM/WCDMA/WLAN/WiMax zero-IF receiver is now available. Employing the second-order feedforward Σ-Δ modulator in a 2-2 modified cascaded configuration, a high linearity over 100 kHz/2 MHz/10 MHz signal bandwidth can be achieved. Application of the P-DWA technique in the first feedback 4-b DAC eliminates the spurious tones associated with the multibit DAC nonlinearity in the WLAN/WiMAX modes.

  • 104.
    Rusu, Ana
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rodríguez de Llera González, Delia
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    The design of a low-distortion sigma-delta ADC for WLAN standards2005Inngår i: ISSCS 2005: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, Proceedings, 2005, s. 151-154Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A low-distortion sigma-delta analog-to-digital converter (ADC) for Wireless Local Area Network (WLAN) standards is presented. The proposed sigma-delta modulator architecture employs the 4-bit 2(nd) order sigma-delta modulator with swing suppression in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). The modulator is designed in 0.18um CMOS process and operates at 1.8V supply voltage. It achieves a dynamic range of 69.1dB and a spurious free dynamic range (SFDR) of 82.2dB for a 10MHz signal bandwidth, and an oversampling ratio of 8.

  • 105.
    Rusu, Ana
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Roslind Jose, Babita
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Linearity enhancement in a configurable sigma-delta modulator2005Inngår i: IEEE-NEWCAS Conference, 2005. The 3rd International / [ed] IEEE, IEEE conference proceedings, 2005, s. 59-62Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A highly linear sigma-delta modulator for dual-standard receivers is presented. The modulator makes use of low-distortion sigma-delta modulator architecture to attain high linearity over a wide bandwidth. The dual-band modulator employs a 2nd order single-bit sigma-delta modulator with feedforward path for GSM mode and a 4th order modified cascaded modulator with single-bit in the first stage and 4-bit in the second for WCDMA mode. The modulator is designed in TSMC 0.18μm CMOS technology and operates at 1.8 supply voltage. It achieves in GSM/WCDMA mode a peak SNDR of 83/75dB, a 96/84dB SFDR and an IMD3 of -93/-82dB for an OSR of 160/16.

  • 106.
    Sleiman, Sleiman Bou
    et al.
    Ohio State Univ, Analog VLSI Lab.
    Atallah, Jad G.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Elnaggar, Mohammed Ismail
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Optimal Sigma Delta Modulator Architectures for Fractional-N Frequency Synthesis2010Inngår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 18, nr 2, s. 194-200Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a comparative study of Sigma Delta modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

  • 107.
    Sleiman, Sleiman Bou
    et al.
    Ohio State Univ, Analog VLSI Lab.
    Atallah, Jad G.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Elnaggar, Mohammed Ismail
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Wide-Division-Range High-Speed Fully Programmable Frequency Divider2008Inngår i: 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, NEW YORK: IEEE , 2008, s. 17-20Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mu m - and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.

  • 108.
    Srinivasar, Sandeep Kowlgi
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ultra-low power 2.4 GHz CMOS receiver front-end for sensor nodes2007Inngår i: 2007 European Conference On Circuit Theory And Design: Vols 1-3, 2007, s. 595-598Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a fully integrated receiver front-end for a 2.4GHz RF transceiver. A system level design for the radio front end for which these components are designed is also presented. The proposed receiver front end (Low-Noise Amplifier, Single-to-Differential Converter and Mixer) is based on a direct conversion architecture designed in 0.18 mu m CMOS technology. It takes advantage of on-chip single to differential signal conversion to avoid the use of cost intensive off-chip balun and external passives. The post layout simulations of front end show that the RF front-end achieves a voltage gain of 8dB without the baseband amplifier, a noise figure of 8.9 dB and IIP3 better than -15 dBm. The flicker noise corner is less than 10 KHz, with a nominal DC offset. It consumes less than 1.6 mA from a 1.8V supply.

  • 109.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Chi, Jiazuo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Design Considerations for Pipelined Continuous-Time Incremental Sigma-Delta ADCs2015Inngår i: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE conference proceedings, 2015, s. 1014-1017Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper addresses design considerations for power-efficient pipelined continuous-time (CT) incremental Sigma-Delta (IΣ∆) ADC architectures. By pipelining identical CT IΣ∆ ADC stages, the proposed architecture provides the design freedom coming from both the pipeline ADC and the IΣ∆ ADC. In searching for a low-power solution given a target resolution, different configurations are examined analytically and simulated using behavioral models. For further power reduction, power-efficient circuits are proposed to implement the active blocks in each configuration. Based on the architecture-level analysis, a configuration that leads to minimum power-area consumption is chosen and implemented as a test-case using the proposed circuit blocks. Post-layout simulations show that the test-case ADC, with 3.2-kHz bandwidth, achieves a peak SNDR of 82.5-dB while dissipating a total power of 18.27-μW. 

  • 110.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Garcia, Julian
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Analysis of Exponentially Decaying Pulse Shape DACs in Continuous-Time Sigma-Delta Modulators2012Inngår i: Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on, IEEE , 2012, s. 424-427Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The performance of continuous-time (CT) sigma-delta (ΣΔ) modulators is severely degraded by the clock jitter induced timing variation in their feedback digital-to-analog converters (DACs). To mitigate this non-ideality, jitter sensitivity reduction techniques that employ exponentially decaying pulse shape DACs have been recently reported. In this paper, exponentially decaying DACs are investigated and generalized expressions are derived. In addition, another exponentially decaying DAC proposed, which can potentially achieve both good jitter immunity and amplitude efficiency. To validate the theoretical results, the proposed DAC, together with other exponentially decaying DACs, are employed in a 3rd order 1-bit CT ΣΔ modulator test case and evaluated through behavioral simulations.

  • 111.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Garcia, Julian
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Impact of Feedback DAC Timing Errors in Continuous-Time Incremental Sigma-Delta DACs2014Inngår i: SSoCC 2014, 2014Konferansepaper (Annet vitenskapelig)
  • 112.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Manolopoulos, Vasileios
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Hybrid Vehicle Positioning and Tracking Using Mobile Phones2011Inngår i: 2011 11th International Conference on ITS Telecommunications, ITST 2011, 2011, s. 315-320Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Due to the pervasive deployments of mobile communication technologies, vehicle positioning and tracking by locating the driver's mobile phones has become feasible. However, no single positioning method can provide decent tradeoff between accuracy and coverage. To address this issue, we propose a Kalman filter-based hybrid method which can track the mobile phones traveling on-board vehicles. The proposed method combines coordinates collected by assisted global positioning system (A-GPS) mobile phones and location estimates calculated from observed time difference of arrival (OTDOA) measurements. Numerical results demonstrate the effectiveness of this hybrid scheme in a simulated vehicular scenario.

  • 113.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Manolopoulos, Vasileios
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Real-Time Urban Traffic State Estimation with A-GPS Mobile Phones as Probes2012Inngår i: Journal of Transportation Technologies, ISSN 2160-0481, Vol. 2, nr 1, s. 22-31Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a microscopic traffic simulation-based method for urban traffic state estimation using Assisted Global Positioning System (A-GPS) mobile phones. In this approach, real-time location data are collected by A-GPS mobile phones to track vehicles traveling on urban roads. In addition, tracking data obtained from individual mobile probes are aggregated to provide estimations of average road link speeds along rolling time periods. Moreover, the estimated average speeds are classified to different traffic condition levels, which are prepared for displaying a real-time traffic map on mobile phones. Simulation results demonstrate the effectiveness of the proposed method, which are fundamental for the subsequent development of a system demonstrator.

  • 114.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    DAC Waveform Effects in CT Incremental ΣΔ ADCs for Biosensor Applications2013Inngår i: 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, IEEE conference proceedings, 2013, s. 6573569-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Incremental sigma-delta (IΣΔ) analog-to-digital converters (ADCs), which are essentially ΣΔ ADCs with periodic resetting, are well suited for low-power low-speed biosensor applications. In recent years, the potential advantage in terms of power dissipation of continuous-time (CT) IΣΔ ADCs have been explored. This paper analyzes the impact of feedback digital-to-analog converters (DACs) on the performance of CT IΣΔ ADCs. Different feedback DAC schemes are firstly analyzed and then evaluated by employing them in a 3rd order single-bit CT IΣΔ ADC. Simulation results are discussed considering the trade-off between the timing error sensitivity and the power consumption, thereby offering a reference for selecting a power efficient feedback DAC scheme.

  • 115.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Two-step continuous-time incremental sigma-delta ADC2013Inngår i: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 49, nr 12, s. 749-750Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A two-step continuous-time (CT) incremental sigma-delta (I Sigma Delta) ADC, which enhances the performance of conventional CT I Sigma Delta ADCs, is proposed. By pipelining two second-order CT I Sigma Delta ADCs, the proposed two-step architecture can achieve high resolution without sacrificing the conversion rate. Compared to other alternatives, the two-step CT I Sigma Delta ADC exhibits the freedom of adjusting its accuracy and speed independently while featuring quite relaxed circuit specifications.

  • 116.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    UMTS Mobile Positioning Simulator for Vehicle Location2010Inngår i: ICWMMN 2010, PROCEEDINGS, STEVENAGE: INST ENGINEERING TECH-IET , 2010, s. 344-347Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, a tool for simulating UMTS mobile positioning in vehicular environment has been developed The primary function of this simulator is to locate the UMTS mobile in realistic propagation environments. This tool first models the network configuration and radio propagation in a vehicular scenario Based on the system level model, it then simulates the pilot signal transmitted by a base station to a mobile station through the 3GPP WCDMA FDD downlink. The received pilots at mobile station are processed to obtain the time-difference-of-arrival estimates which are used to construct the hyperbolic equations for mobile position calculation The simulator has been implemented in the Matlab and Simulink environment.

  • 117.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Vehicle Location using Wireless Wide Area Network2010Inngår i: 2010 3rd Joint IFIP Wireless and Mobile Networking Conference (WMNC), 2010Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The ability to locate the position of a mobile device has emerged as a key facility of existing and future generation mobile systems. Many value added location based services have been enabled by this feature. Due to the pervasive deployments of mobile communication technologies, vehicle positioning by locating the driver's mobile devices has become feasible. Moreover, it potentially displaces systems that were designed specifically for vehicles. This paper first investigates the standard mobile location methods and exploits this information in intelligent transportation systems, especially in vehicle location. Hybrid solutions are then proposed based on the well-established and standardized location methods.

  • 118.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Device Modelling for 60 GHz Radio Front-ends in 65 nm CMOS2009Inngår i: 2009 NORCHIP, 2009Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents an electromagnetic simulation-based modelling solution for active and passive devices which targets 60 GHz front-end integrated circuits. An EM model, using existing transistor compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on EM simulation S-parameter data is also derived. The models are process and layout dependent, which have been verified by the design of a low noise amplifier in a 60 GHz radio front-end.

  • 119.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A 60 GHz receiver front-end in 65 nm CMOS2011Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 67, nr 1, s. 61-71Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of -13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm x 0.44 mm.

  • 120.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    A Comparative Design Study of Continuous-Time Incremental Sigma-Delta ADC Architectures2016Inngår i: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, nr 12, s. 2147-2163Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a comparative design study of continuous-time (CT) incremental sigma-delta (IΣΔ) ADCs, which can expand another dimension of the IΣΔ ADC world that is dominated by discrete-time implementations. Several CT IΣΔ ADC architectures are introduced and analyzed aiming to reduce the modulator’s sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣΔ ADCs are selected to be examined, implemented, and tested. The three ADC prototypes, fabricated in a standard 0.18 μm CMOS technology, demonstrate competitive figure-of-merits in terms of power efficiency compared to the state-of-the-art counterparts.

  • 121.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems2015Inngår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 99, s. 1-10Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 µm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 µW, which corresponds to a figure-of-merit of 0.85 pJ/conv.

  • 122.
    Tian, Ye
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Lanni, Luigia
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Zetterling, Carl-Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    A 500 °C monolithic SiC BJT latched comparator2016Inngår i: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 858, s. 921-924Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a monolithic 4H-SiC BJT latched emitter-coupled logic (ECL) comparator for high temperature analog-to-digital conversion. The comparator consists of a low-gain pre-amplifier, a track and latch stage and an output buffer. For low-speed input signals, the comparator input offset voltage is 3.9 mV at 27 ºC and monotonically increases up to 9.1 mV at 500ºC. The single-ended output swing is 5.5 V at 27 ºC and 3.9 V at 500 ºC. The minimum comparison time is around 1 μs from 27 ºC to 500 ºC. The whole comparator dissipates 464 mW in average over the considered temperature range with a 15 V power supply. It consumes 2.25 × 0.84 mm2 chip area (with the bond pads included).

  • 123.
    Tian, Ye
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Lanni, Luigia
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Zetterling, Carl-Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Silicon Carbide fully differential amplifier characterized up to 500 °C2016Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, nr 6, s. 2242-2247, artikkel-id 7451254Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a monolithic fully differential amplifier implemented in a low-voltage 4H-silicon carbide bipolar junction transistor technology. The circuit has been designed, considering the variation of device parameters over a large temperature range. A base-current compensation technique has been applied to overcome the low input resistance of the amplifier. The bare chip of the amplifier has been measured from 27 °C to 500 °C using a hot-chuck probe station. Its openloop gain is 58 dB at 27 °C, and monotonically decreases to 37 dB at 500 °C. Its closed-loop gain reduction is ∼5 dB over the investigated temperature range. The gain-bandwidth product drops from 2.8 MHz at 27 °C to 1.3 MHz at 500 °C with 470 pF off-chip compensation capacitors. A low total-harmonicdistortion of −58.4 dB at 27 °C and −46.9 dB at 500 °C is achieved due to the fully differential implementation. A low input offset voltage of 0.5 mV at 27 °C and 6.9 mV at 500 °C is achieved without calibration. The relative high linearity and the low offset demonstrate the potential of this technology to be further investigated for the front-end sensor circuits in high-temperature applications.

  • 124.
    Zhao, Kangqiao
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Amir, Saifullah
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Meng, Xiaozhou
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ali, Muhammad Mohsin
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Gustafsson, Martin
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Elnaggar, Mohammed Ismail
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A reconfigurable successive approximation ADC in 0.18μm CMOS technology2008Inngår i: 15th IEEE International Conference on Electronics, Circuits and Systems, 2008. ICECS 2008, IEEE conference proceedings, 2008, s. 646-649Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents the design of a reconfigurable successive approximation analog to digital converter (ADC) for both ultra wideband and Bluetooth applications. The behavioral level design is presented along with the circuit implementation. The ADC architecture employs a split capacitor array DAC which reduces the power consumption. The ADC is implemented in a 0.18mum CMOS process and circuit level simulation results show that the ADC can achieve 28.9 dB SINAD at 66 MSPS in the UWB mode, and 53.9 dB SINAD at 1 MSPS in the Bluetooth mode.

  • 125.
    Zhao, Zongyang
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Atallah, Jad G.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Elnaggar, Mohammed Ismail
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Vertical handover for 4G multi-standard wireless transceivers2007Inngår i: 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS: VOLS 1-4, 2007, s. 1356-1359Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Future best-connected wireless solutions will involve a multitude of network standards between which the user can switch in order to optimize a set of benefits such as cost and performance. As a result of this convergence, the hardware design of the mobile device will require knowledge about the restrictions imposed by the upper networking layers. This paper starts by presenting the requirements for the connection initialization in the WLAN, WiMAX and 3G standards as they pertain to the mobile transceiver design. It is assumed that the mobile device is based on the dual front-end transceiver architecture where the primary transceiver handles the current network connection while the secondary transceiver (Sniffer) searches for an alternative connection. The paper also presents the handover procedures between these standards that will provide, among other things, the timing requirements for the circuit design.

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