Endre søk
Begrens søket
1234567 101 - 150 of 536
RefereraExporteraLink til resultatlisten
Permanent link
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Treff pr side
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sortering
  • Standard (Relevans)
  • Forfatter A-Ø
  • Forfatter Ø-A
  • Tittel A-Ø
  • Tittel Ø-A
  • Type publikasjon A-Ø
  • Type publikasjon Ø-A
  • Eldste først
  • Nyeste først
  • Skapad (Eldste først)
  • Skapad (Nyeste først)
  • Senast uppdaterad (Eldste først)
  • Senast uppdaterad (Nyeste først)
  • Disputationsdatum (tidligste først)
  • Disputationsdatum (siste først)
  • Standard (Relevans)
  • Forfatter A-Ø
  • Forfatter Ø-A
  • Tittel A-Ø
  • Tittel Ø-A
  • Type publikasjon A-Ø
  • Type publikasjon Ø-A
  • Eldste først
  • Nyeste først
  • Skapad (Eldste først)
  • Skapad (Nyeste først)
  • Senast uppdaterad (Eldste først)
  • Senast uppdaterad (Nyeste først)
  • Disputationsdatum (tidligste først)
  • Disputationsdatum (siste først)
Merk
Maxantalet träffar du kan exportera från sökgränssnittet är 250. Vid större uttag använd dig av utsökningar.
  • 101. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Performance Analysis of 3D NoCs Partitioning Methods2010Inngår i: IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, s. 479-480Konferansepaper (Fagfellevurdert)
    Abstract [en]

    3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with short vertical ones. Achieving higher performance along with reducing the network latency can be obtained by utilizing an efficient communication protocol in 3D Networks-on-Chlp (NoCs). In this work, several unlcast/multicast partitioning methods are explained in order to And an advantageous method with low communication latency. Moreover, two factors of efficiency, unicast latency and multicast latency, are analyzed by analytical models. We also perform simulation to compare the efficiency of proposed methods. The results show that Mixed Partitioning method outperforms other methods in term of latency.

  • 102. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Tenhunen, Hannu
    University of Turku, Finland.
    Performance evaluation of unicast and multicast communication in three-dimensional mesh architectures2010Inngår i: Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010, 2010, s. 161-162Konferansepaper (Fagfellevurdert)
    Abstract [en]

    As the multicast communication is utilized commonly in various parallel applications, the performance can be significantly improved by supporting multicast operations at the hardware level. In this paper, we define several factors of efficiency for unicast/multicast communication such as average of unicast latency, average of maximum multicast latency and level of parallelism in 3D mesh NoCs. Then, we propose analytical models for measuring the efficiency factors of a method in unicast/multicast communication called vertical block partitioning.

  • 103. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Neishaburi, M. H.
    Mohammadi, S.
    Afzali-Kusha, A.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    An Efficient Dynamic Multicast Routing Protocol for Distributing Traffic in NOCs2009Inngår i: 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, 2009, s. 1064-1069Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock synchronization, replication, or barrier synchronization. Among several multicast schemes proposed in on chip interconnection networks, path-based multicast scheme has been proven to be more efficient than the tree-based, and unicast-based. In this paper a low distance path-based multicast scheme is proposed. The proposed method takes advantage of the network partitioning, and utilizing of an efficient destination ordering algorithm. The results in performance, and power consumption show that the proposed method outstands the previous on chip path-based multicasting algorithms.

  • 104. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Sreejesh, N. P.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS. University of Turku, Finland.
    Efficient network interface architecture for network-on-chips2009Inngår i: 2009 NORCHIP, 2009, artikkel-id 5397837Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we present novel network interface architecture for on-chip networks to increase memory parallelism and to improve the resource utilization. The proposed architecture exploits AXI transaction based protocol to be compatible with existing IP cores. Experimental results with synthetic test case demonstrate that the proposed architecture outperforms the conventional architecture in term of latency.

  • 105. Ebrahimi, Masoumeh
    et al.
    Daneshtalab, Masoud
    Liljeberg, Pasi
    Plosila, Juha
    Flich, Jose
    Tenhunen, Hannu
    Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing2014Inngår i: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 63, nr 3, s. 718-733Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in ChipMultiprocessors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and invarious parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at thehardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs,each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore theefficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose theMinimal and Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show thatan advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the networkuntil all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsetsand the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performanceimprovement across all workloads while performance can be further improved by utilizing the MAR algorithm. Nineteen percent averageand 42 percent maximum latency reduction are obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.

  • 106.
    Ebrahimi, Masoumeh
    et al.
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektroteknik, Elektronik och inbyggda system, Elektronik och inbyggda system.
    Kelati, Amleset
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektroteknik, Elektronik och inbyggda system, Elektronik och inbyggda system.
    Nkonoki, Emma
    Kondoro, Aron
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektroteknik, Elektronik och inbyggda system.
    Rwegasira, Diana
    KTH.
    Ben Dhaou, Imed
    Taajamaa, Ville
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektroteknik, Elektronik och inbyggda system, Integrerade komponenter och kretsar.
    Creation of CERID: Challenge, Education, Research, Innovation, and Deployment in the context of smart MicroGrid2019Inngår i: IST-Africa 2019 Conference Proceedings / [ed] Paul Cunningham ; Miriam Cunningham, 2019Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The iGrid project deals with the design and implementation of a solar-powered smart microgrid to supply electric power to small rural communities. In this paper, we discuss the roadmap of the iGrid project, which forms by merging the roadmaps of KIC (knowledge and Innovation Community) and CDE (Challenge-Driven Education). We introduce and explain a five-gear chain as Challenge, Education, Research, Innovation, and Deployment, called CERID, to reach the main goals of this project. We investigate the full chain in the iGrid project, which is established between KTH Royal Institute of Technology (Sweden) and University of Dar es Salam (Tanzania). We introduce the key stakeholders and explain how CERID goals can be accomplished in higher educations and through scientific research. Challenges are discussed, some innovative ideas are introduced and deployment solutions are recommended.

  • 107.
    Ellervee, Peeter
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hemani, Ahmed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Kumar, Anshul
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Svantesson, Bengt
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Controller Synthesis in Control and Memory Centric High-level Synthesis System1996Inngår i: Proceedings of the Baltic Electronics Conference, 1996, s. 393-396Konferansepaper (Fagfellevurdert)
  • 108.
    Ellervee, Peeter
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hemani, Ahmed
    Kumar, Anshul
    Svantesson, Bengt
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Controller Synthesis in Control and Memory Centric High-Level Synthesis System1996Inngår i: 5th Biennial Baltic Electronic Conference, 1996, s. 393-396Konferansepaper (Fagfellevurdert)
  • 109.
    Ellervee, Peeter
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hemani, Ahmed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Exploring ASIC Design Space at System Level with a Neural Network Estimator1994Inngår i: Proc. of IEEE ASIC-conference, 1994, 1994Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.

  • 110. Fattah, M.
    et al.
    Airola, A.
    Ausavarungnirun, R.
    Mirzaei, N.
    Liljeberg, P.
    Plosila, J.
    Mohammadi, S.
    Pahikkala, T.
    Mutlu, O.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    A low-overhead, fully-distributed, guaranteed-delivery routing algorithm for faulty network-on-chips2015Inngår i: Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015, ACM Digital Library, 2015Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips. The algorithm is the first to provide all of the following properties at the same time: 1) fully-distributed with no centralized component, 2) guaranteed delivery (it guarantees to deliver packets when a path exists between nodes, or otherwise indicate that destination is unreachable, while being deadlock and livelock free), 3) low area cost, 4) low reconfiguration overhead upon a fault. To achieve all these properties, we propose Maze-routing, a new variant of face routing in on-chip networks and make use of deflections in routing. Our evaluations show that Maze-routing has 16X less area overhead than other algorithms that provide guaranteed delivery. Our Maze-routing algorithm is also high performance: for example, when up to 5 links are broken, it provides 50% higher saturation throughput compared to the state-of-the-art. Copyright 2015 ACM.

  • 111.
    Fawad,
    et al.
    Univ Engn & Technol Taxila, ACTSENA Res Grp, Telecommun Engn Dept, Punjab 47050, Pakistan.
    Khan, Muhammad Jamil
    Univ Engn & Technol Taxila, ACTSENA Res Grp, Telecommun Engn Dept, Punjab 47050, Pakistan..
    Rahman, MuhibUr
    Polytech Montreal, Dept Elect Engn, Montreal, PQ H3T 1J4, Canada..
    Amin, Yasar
    Univ Engn & Technol Taxila, ACTSENA Res Grp, Telecommun Engn Dept, Punjab 47050, Pakistan..
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar. Univ Turku, Dept Informat Technol, TUCS, FIN-20520 Turku, Finland..
    Low-Rank Multi-Channel Features for Robust Visual Object Tracking2019Inngår i: Symmetry, ISSN 2073-8994, E-ISSN 2073-8994, Vol. 11, nr 9, artikkel-id 1155Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Kernel correlation filters (KCF) demonstrate significant potential in visual object tracking by employing robust descriptors. Proper selection of color and texture features can provide robustness against appearance variations. However, the use of multiple descriptors would lead to a considerable feature dimension. In this paper, we propose a novel low-rank descriptor, that provides better precision and success rate in comparison to state-of-the-art trackers. We accomplished this by concatenating the magnitude component of the Overlapped Multi-oriented Tri-scale Local Binary Pattern (OMTLBP), Robustness-Driven Hybrid Descriptor (RDHD), Histogram of Oriented Gradients (HoG), and Color Naming (CN) features. We reduced the rank of our proposed multi-channel feature to diminish the computational complexity. We formulated the Support Vector Machine (SVM) model by utilizing the circulant matrix of our proposed feature vector in the kernel correlation filter. The use of discrete Fourier transform in the iterative learning of SVM reduced the computational complexity of our proposed visual tracking algorithm. Extensive experimental results on Visual Tracker Benchmark dataset show better accuracy in comparison to other state-of-the-art trackers.

  • 112.
    Färm, Petra
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Dubrova, Elena
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Logic optimization technique for molecular cascades2005Inngår i: Nanotechnology II / [ed] Lugli, P; Kish, LB; Mateos, J, SPIE - International Society for Optical Engineering, 2005, Vol. 5838, s. 95-104Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Molecular cascades introduced in(1) provide new ways to exploit the motion of individual molecules in nanometer-scale structures. Computation is performed by purely mechanical means similarly to the toppling of a row of standing domino. A specific feature of molecular cascades is that an inverter cannot be build, because it would require that all molecules in the inverter's output untopple when the input cascade topples. This is not possible because an untoppled state has higher energy than a toppled one. As a solution, we propose to avoid the need for inverters by representing signals by the dual-rail convention. As a basic building block we use a molecular block, which has four inputs x(1),...,x(4) such that x(3) = x(1)', x(4) = x(2)', and two outputs f(1) = x(1) . x(2) and f(2) = x(3) + x(4). If input variables are available in both complemented and non-complemented form, then any Boolean function can be implemented by a composition of such molecular blocks. We present an experimental tool which first uses a rule-based randomized search to optimize a Boolean network and then maps it into a network of interconnected molecular blocks.

  • 113. Gao, Y. C.
    et al.
    Wikner, J. J.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Design and analysis of an oversampling D/A converter in DMT-ADSL systems2002Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, nr 3, s. 201-210Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 mum 3.3 V CMOS process and integrated into the whole DAC chip.

  • 114. Gao, Y. H.
    et al.
    Jia, L. H.
    Isoaho, J.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    A comparison design of comb decimators for sigma-delta analog-to-digital converters2000Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 22, nr 1, s. 51-60Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 mu m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.

  • 115. Gia, T. N.
    et al.
    Jiang, M.
    Rahmani, Amir
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Westerlund, T.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Fog computing in healthcare Internet of Things: A case study on ECG feature extraction2015Inngår i: Proceedings - 15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, s. 356-363, artikkel-id 7363093Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Internet of Things technology provides a competent and structured approach to improve health and wellbeing of mankind. One of the feasible ways to offer healthcare services based on IoT is to monitor humans health in real-time using ubiquitous health monitoring systems which have the ability to acquire bio-signals from sensor nodes and send the data to the gateway via a particular wireless communication protocol. The real-time data is then transmitted to a remote cloud server for real-time processing, visualization, and diagnosis. In this paper, we enhance such a health monitoring system by exploiting the concept of fog computing at smart gateways providing advanced techniques and services such as embedded data mining, distributed storage, and notification service at the edge of network. Particularly, we choose Electrocardiogram (ECG) feature extraction as the case study as it plays an important role in diagnosis of many cardiac diseases. ECG signals are analyzed in smart gateways with features extracted including heart rate, P wave and T wave via a flexible template based on a lightweight wavelet transform mechanism. Our experimental results reveal that fog computing helps achieving more than 90% bandwidth efficiency and offering low-latency real time response at the edge of the network.

  • 116. Gia, T. N.
    et al.
    Rahmani, A. -M
    Westerlund, T.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Fault tolerant and scalable IoT-based architecture for health monitoring2015Inngår i: SAS 2015 - 2015 IEEE Sensors Applications Symposium, Proceedings, IEEE conference proceedings, 2015, s. 334-339Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A novel Internet of Things based architecture supporting scalability and fault tolerance for healthcare is presented in this paper. The wireless system is constructed on top of 6LoWPAN energy efficient communication infrastructure to maximize the operation time. Fault tolerance is achieved via backup routing between nodes and advanced service mechanisms to maintain connectivity in case of failing connections between system nodes. The presented fault tolerance approach covers many fault situations such as malfunction of sink node hardware and traffic bottleneck at a node due to a high receiving data rate. A method for extending the number of medical sensing nodes at a single gateway is presented. A complete system architecture providing a quantity of features from bio-signal acquisition such as Electrocardiogram (ECG), Electroencephalography (EEG), and Electromyography (EMG) to the representation of graphical waveforms of these gathered bio-signals for remote real-time monitoring is proposed.

  • 117. Gia, Tuan Nguyen
    et al.
    Tcarenko, Igor
    Sarker, Victor K.
    Rahmani, Amir M.
    Westerlund, Tomi
    Liljeberg, Pasi
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    IoT-Based Fall Detection System with Energy Efficient Sensor Nodes2016Inngår i: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE conference proceedings, 2016Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Fall needs to be attentively considered due to its highly frequent occurrence especially with old people - up to one third of 65 and above year-old people around the world are risk of being injured due to falling. Furthermore, fall is a direct or indirect factor causing severe traumas such as brain injuries or bone fractures. However, timely medical attention might help to avoid serious consequences from a fall. A viable solution to solve this is an IoT-based system which takes advantage of wireless sensor networks, wearable devices, Fog and Cloud computing. To deliver sufficient degree of reliability, wearable devices working at the core of a fall detection system, are required to work for prolonged period of time. In this paper we investigate energy consumption of sensor nodes in an IoT-based fall detection system and present a design of a customized sensor node. In addition, we compare the customized sensor node with other sensor nodes, built on general purpose development boards. The results show that sensor nodes based on delicate customized devices are more energy efficient than the others based on general purpose devices while considering identical specification of micro-controller and memory capacity. Furthermore, our customized sensor node with energy efficiency selections can operate continuously up to 35 hours.

  • 118. Gothenberg, A.
    et al.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Improved cascaded sigma-delta noise shaper architecture with reduced sensitivity to circuit nonlinearities2002Inngår i: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 38, nr 14, s. 683-685Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    An improved cascaded sigma-delta noise shaper with reduced sensitivity to switch and opamp nonlinearities is presented. The architecture can be used for wideband applications, i.e. RF-front ends, at low oversampling ratio, as well as for high-resolution audio applications.

  • 119. Gothenberg, A.
    et al.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Nonlinear quantization in low oversampling ratio sigma-delta noise shapers for RF applications2002Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, nr 3, s. 193-206Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low oversampling ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for the 4th-order cascaded noise shaper architectures to be used in baseband front-ends. We show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low oversampling ratio based on usage of multibit quantizers outside the actual signal noise shaping path. We also present results for nonlinear quantization effects in low oversampling ratio cascaded noise shaper architectures. We analyse the effect of the non-linearity in both the A/D and D/A-block in quantization error quantizer path for the 4th-order cascaded topology and the design constraints associated to the performance of the used A/D and D/A structures. The performance requirement for the multi-bit quantizer for high SQNR is shown for the case of low oversampling ratios. The results show that non-uniform quantization around zero input are far more crucial to the SQNR than nonlinear quantization deviating from the ideal transfer function. As the key difference to standard multibit quantizers, no special error correction or error distribution schemes are required; the linearity requirements are satisfied with 0.2 LSB accuracy of the few bit quantizer. Finally, the performance of non-linear quantization using multitone test signals are also shown.

  • 120. Gothenberg, A.
    et al.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Performance analysis of sampling switches in voltage and frequency domains using Volterra series2004Inngår i: 2004 IEEE International Symposium on Circuits and Systems, Vol 1, Proceedings, IEEE , 2004, Vol. 1, s. 765-768Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In any data converter system, the linearity of the sampling switch is a very critical parameter, especially for wideband sigma-delta modulators. Distortion introduced in the sampling instance directly degrades the quality of the input signal. In this paper we present analyses of a set of sampling switches in the frequency and voltage domains in order to find the most linear type for wide baseband excitation. Volterra series analysis is adopted to find the frequency behavior of the switches. The theoretical results are verified by circuit simulations in a 0.35mum CMOS process. It is found that the bootstrap sampling switch is a very attractive candidate, especially for frequencies near f(s)/2.

  • 121. Grange, Matt
    et al.
    Weerasekera, Roshan
    Pamunuwa, Dinesh
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Examination of Delay and Signal Integrity Metrics in Through Silicon Vias2009Inngår i: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Electronic Workshop Digest, Palais des Congrès Acropolis – Nice, France, Friday April 24, 2009, Nice, France, 2009, s. 260-264Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This article discusses results from simulations of signaling in Through Silicon Vias (TSVs) with an emphasis on latency and signal integrity effects. Data from field solver simulations is used for TSV parasitics and employed in SPICE simulations. A reduced order electrical circuit is proposed for lone TSVs as well as bundled structures and switch-factor based delay models are derived to calculate rise times in a 3x3 bundle. Furthermore Signal Integrity (SI) issues in coupled TSVs are briefly discussed.

  • 122.
    Guang, L.
    et al.
    Turku Centre for Computer Science (TUCS).
    Kanth, R.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    University of Turku.
    Hierarchical Monitoring in Smart House: Design Scalability, Dependability and Energy-Efficiency2012Inngår i: Communications in Information Science and Management Engineering, ISSN 2222-1859, Vol. 2Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Hierarchical monitoring is presented on smart house platforms to provide scalability, dependability and energy efficiency. Hierarchical monitoring is a scalable and generic approach for optimization and diagnostic operations in distributed embedded systems. The paper studies the design of hierarchical monitoring on smart house platforms as an example of WPANs (wireless personal area networks). We present the functional partition of hierarchical agents in a smart house, and show that the architecture can be conveniently built upon the widely used Zigbee standard. We give a qualitative discussion of the design scalability and dependability compared to the centralized monitoring. In addition, we quantitatively compare the energy consumption of monitoring communication in hierarchical and centralized architectures, with the classic free space propagation model. The qualitative discussion and quantitative analysis demonstrate the scalability, dependability and energy efficiency of hierarchical monitoring in a domestic environment.

  • 123.
    Guang, L.
    et al.
    Turku Centre for Computer Science (TUCS).
    Nigussie, E.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Isoaho, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs2012Inngår i: System on Chip (SoC), 2012 International Symposium on, IEEE , 2012, s. 6376351-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Comparative evaluations of centralized, clustered and distributed architectures, for energy management in NoCs, are presented. The paper starts with the systematic examination of the monitoring, decision-making, and reconfiguration processes in building coarse and fine-grained self-adaptation architectures. With examining the physical support in modern technology, network-wide, cluster-wide and per-node energy-management architectures on NoCs are presented, utilizing either voltage regulators or multiple on-chip power delivery networks (MPNs). To identify the effectiveness and efficiency of energy-performance tradeoffs, extensive quantitative simulations are performed with various temporal and spatially changing traffics. Based on the results, we can first observe that the centralized architecture can not adapt to the traffic's spatial locality for effective energy-performance tradeoff. Second, the distributed energy management has the lowest energy-delay product mostly attributed to the fast voltage switching of MPNs, while the synchronization incurs noticeable energy overhead. The clustered architecture, last but not least, is a suitable alternative when the advanced MPN technology is not available. It has low energy and energy-delay product, with very small energy overhead from the monitoring communication.

  • 124.
    Guang, L.
    et al.
    Turku Centre for Computer Science (TUCS).
    Nigussie, E.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Isoaho, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    HLS-DoNoC: High-level simulator for dynamically organizational NoCs2012Inngår i: Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on, IEEE , 2012, s. 89-94Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A high-level simulator is presented for the design and analysis of dynamically organizational Networks-on-Chip (DoNoCs). The DoNoC is able to organize statically or dynamically different network nodes for run-time coarse and fine grained reconfiguration, in particular power management. As an important step in the design flow, a simulator for early-stage design exploration is the focus of the paper. Built upon classic wormhole-based NoC architecture, the simulator is capable of experimenting diverse run-time monitoring and reconfiguration methods. In particular, dynamic clusterization can be performed with inter-cluster interfaces properly configured at the run-time. The simulator is flit-level accurate, trace-driven, and easy-to-reconfigure. It supports both synchronous and ratiochronous timing, and can provide the communication performance and power/energy consumption. The paper demonstrates the usage of the simulator in the design of various cluster-based power management schemes.

  • 125. Guang, L.
    et al.
    Nigussie, E
    Plosila, J.
    Isoaho, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Survey of self-adaptive NoCs with energy-efficiency and dependability2012Inngår i: International Journal of Embedded and Real-Time Communication Systems, ISSN 1947-3176, Vol. 3, nr 2, s. 1-22Artikkel, forskningsoversikt (Fagfellevurdert)
    Abstract [en]

    The self-adaptive Network-on-Chip (NoC) is a promising communication architecture for massively parallel embedded systems. With constant technology scaling and the consequent stronger influence of process variations, the necessity of run-time monitoring and adaptive reconfiguration becomes widely acknowledged. This article presents a survey of existing techniques and methods, in particular for energy efficiency and dependability. The article firstly examines the motivation of self-adaptive computing in parallel embedded systems. A self-adaptive system model is abstracted, which is composed of goals, monitoring interface, and self-adaptation. Based on the model, the authors extensively survey previous works addressing adaptive NoCs with different monitoring techniques and reconfiguration methods, for power/energy optimization and dependability enhancement. Several design examples are elaborated which serve proper guiding purposes. The authors also identify important issues which are often overlooked or deserve more attention. The article provides review and insight for future design on this topic.

  • 126.
    Guang, L.
    et al.
    University of Turku, Finland.
    Nigussie, E
    University of Turku, Finland.
    Plosila, J.
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study2012Inngår i: International Journal of Adaptive, Resilient and Autonomic Systems, ISSN 1947-9220, E-ISSN 1947-9239, Vol. 3Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

  • 127. Guang, L.
    et al.
    Nigussie, E.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Positioning antifragility for clouds on public infrastructures2014Inngår i: Procedia Computer Science, 2014, s. 856-861Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Cloud computing scalably and sustainably utilizes computing and communication resources. One segment of the cloud ecosystem is the services built upon public infrastructures to address general benefits. This segment itself is an open system, involving many contributors and stakeholders, and its growth and development is an unpredictable process influenced by economical, societal and technological factors.This paper argues the antifragility as an indispensable feature for cloud computing, and proposes a development process for the open system to maintain, improve and prosper under contradicting interests of users, companies and governments. The proposal emphasizes multi-player's roles and interaction, and the temporal and spatial interleaving of development stages of different application domains.

  • 128.
    Guang, L.
    et al.
    Turku Centre for Computer Science (TUCS).
    Nigussie, E.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    Vertical and horizontal integration towards collective adaptive system: a visionary approach2012Inngår i: Proceedings of the 2012 ACM Conference on Ubiquitous Computing, 2012, s. 762-765Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Hybrid multi-domain computing systems are emerging. While the context-aware self-adaptive system models are under intensive research in individual computing domains, their integration into a collective adaptive system still remains a major challenge. This position paper visions a meet-in-the-middle approach, where horizontal integration is applied to sub-system models extracted from vertical integration. The integration relies on orthogonal behavior and execution models respectively capturing the functional and non-functional features of sub-systems. The construction towards guaranteed services can be achieved with composition of static (worst-case) execution models, while best-effort services can be constructed with statistical models. Given that each computing domain has, to some extent, formulated its own design flow of context-aware systems, the envisaged meet-in-the-middle integration approach maximizes the reuse of existing models and platforms, thus is promising for the highly-complex system design process.

  • 129. Guang, L.
    et al.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Self-adaptive SoCs for dependability: Review and prospects2014Inngår i: Advancing Embedded Systems and Real-Time Communications with Emerging Technologies, IGI Global, 2014, s. 1-21Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

  • 130. Guang, Liang
    et al.
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Hierarchical Agent Monitored System: An Innovative Paradigm for Parallel Computing2009Inngår i: ACACES 2009 (International Summer School of Advanced Computer Architecture and Compilation for Embedded Systems), 2009, s. 59-62Konferansepaper (Fagfellevurdert)
  • 131.
    Guang, Liang
    et al.
    University of Turku, Finland.
    Jafri, Syed Mohammad Asad Hassan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Yang, Bo
    University of Turku Finland.
    Plosila, Juha
    University of Turku Finland.
    Hannu, Tenhunen
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems2012Inngår i: First MEDIAN Workshop (MEDIAN'12), 2012Konferansepaper (Annet vitenskapelig)
    Abstract [en]

    Dual-level fault-tolerance is presented on many-core systems, provided by the software-based system agent and hardware-based local agents. The system agent performs fault-triggered energy-aware remapping with bandwidth constraints, addressing coarse-grained processor failures. The local agents achieve fine-grained link-level fault tolerance against transient and permanent errors. The paper concisely presents the architecture, dual-level fault-tolerant techniques and experiment results.

  • 132.
    Guang, Liang
    et al.
    University of Turku, Finland.
    Jafri, Syed Mohammad Asad Hassan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Yang, Bo
    University of Turku, Finland.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hierarchical supporting structure for dynamic organization in many-core computing systems2013Inngår i: PECCS 2013: Proceedings of the 3rd International Conference on Pervasive Embedded Computing and Communication Systems, 2013, s. 252-261Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Hierarchical supporting structures for dynamic organization in many-core computing systems are presented.With profound hardware variations and unpredictable errors, dependability becomes a challenging issue in theemerging many-core systems. To provide fault-tolerance against processor failures or performance degradation,dynamic organization is proposed which allows clusters to be created and updated at the run-time. Hierarchicalsupporting structures are designed for each level of monitoring agents, to enable the tracing, storingand updating of component and system status. These supporting structures need to follow software/hardwareco-design to provide small and scalable overhead, while accommodating the functions of agents on the correspondinglevel. This paper presents the architectural design, functional simulation and implementationanalysis. The study demonstrates that the proposed structures facilitate the dynamic organization in caseof processor failures and incur small area overhead on many-core systems.

  • 133. Guang, Liang
    et al.
    Kanth, R.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hierarchical Monitoring in Smart House: Design Scalability, Dependability and Energy-Efficiency2011Inngår i: Proc. of the 3rd International Conference on Information Science and Engineering (ICISE2011) / [ed] Pan, Yi, 2011, s. 291-296Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Energy-efficient hierarchical monitoring is presented on smart house platforms. The rapid expansion of embedded systems requires scalable and portable design interfaces to tackle with the increasing complexity. Hierarchical monitoring is a scalable and generic approach for optimization and diagnostic operations in distributed embedded systems. The paper studies the design of hierarchical montioring on smart house platforms built upon the Zigbee standard of PANs (personal area networks). It presents the functional partition of hierarchical agents in a smart house, and gives a qualitative discussion of the design scalability and dependability, in particular compared to centralized monitoring. In addition, quantitative evaluation of the energy efficiency of monitoring communication in a smart house is performed using a PAN simulator with Zigbee routing configuration. We demonstrate that hierarchical monitoring is more energy efficient than centralized monitoring in various scenarios of a domestic environment.

  • 134. Guang, Liang
    et al.
    Liljeberg, P.
    Nigussie, Ethiopia
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A review of dynamic power management methods in NoC under emerging design considerations2009Inngår i: 2009 NORCHIP, 2009, s. 1-6Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A review of dynamic and adaptive techniques for power management of on-chip interconnects, under emerging design considerations, is presented. The progress of IC technology has introduced novel methods, architectures and new challenges for power-aware design exploration. An examination of stateof-the-art power management techniques enables feasible and efficient design of future NoC platforms. This review first analyzes the new challenges, architectures and technologies, including PVT (process, voltage, temperature) variations, rapidly increasing leakage power, multiple on-chip PDN (power delivery network) as well as other architectures, which bring new considerations in low-power design exploration. A wide selection of dynamic power-saving techniques for onchip interconnects are examined, classified into several categories including run-time datapath configuration, supply configuration and adaptive encoding. The effects and feasibility of these methods, especially their potentials in future technology, are judiciously analyzed. An outlook on generic power management paradigms in next-generation NoCs concludes the review.

  • 135. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Isoaho, Jouni
    Rantala, Pekka
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Interconnection alternatives for hierarchical monitoring communication in parallel SoCs2010Inngår i: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 34, nr 5, s. 118-128Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Interconnection architectures for hierarchical monitoring communication in parallel System-on-Chip (SoC) platforms are explored. Hierarchical agent monitoring design paradigm is an efficient and scalable approach for the design of parallel embedded systems. Between distributed agents on different levels, monitoring communication is required to exchange information, which forms a prioritized traffic class over data traffic. The paper explains the common monitoring operations in SoCs, and categorizes them into different types of functionality and various granularities. Requirements for on-chip interconnections to support the monitoring communication are outlined. Baseline architecture with best-effort service, time division multiple access (TDMA) and two types of physically separate interconnections are discussed and compared, both theoretically and quantitatively on a Network-on-Chip (NoC)-based platform. The simulation uses power estimation of 65 nm technology and NoC microbenchmarks as traffic traces. The evaluation points out the benefits and issues of each interconnection alternative. In particular, hierarchical monitoring networks are the most suitable alternative, which decouple the monitoring communication from data traffic, provide the highest energy efficiency with simple switching, and enable flexible reconfiguration to tradeoff power and performance.

  • 136. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Koskinen, Lauri
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication2009Inngår i: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Volume 5455 LNCS, 2009, s. 183-194Konferansepaper (Fagfellevurdert)
    Abstract [en]

    An autonomous-DVFS-enabled supply island architecture on network-on-chip platforms is proposed. This architecture exploits the temporal and spatial network traffic variations in minimizing the communication energy while constraining the latency and supply management overhead. Each island is equipped with autonomous DVFS mechanism, which traces the local and nearby network conditions. In quantitative simulations with various types of representative traffic patterns, this approach achieves greater energy efficiency than two other low-energy architectures (typically 10% - 27% lower energy). With autonomous supply management on a proper granularity as demonstrated in this study, the communication energy can be minimized in a scalable manner for many-core NoCs.

  • 137. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Rantala, Pekka
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip2010Inngår i: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 9, nr 3, s. 25-Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Hierarchical agent framework is proposed to construct a monitoring layer towards self-aware parallel systems-on-chip (SoCs). With monitoring services as a new design dimension, systems are capable of observing and reconfiguring themselves dynamically at all levels of granularity, based on application requirements and platform conditions. Agents with hierarchical priorities work adaptively and cooperatively to maintain and improve system performance in the presence of variations and faults. Function partitioning of agents and hierarchical monitoring operations on parallel SoCs are analyzed. Applying the design approach on the Network-on-Chip (NoC) platform demonstrates the design process and benefits using the novel approach.

  • 138. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip2010Inngår i: Proceedings - IEEE International SOC Conference, SOCC 2010, 2010, s. 481-486Konferansepaper (Fagfellevurdert)
    Abstract [en]

    System-level exploration of a novel Network-on-Chip (NoC) architecture with run-time communication bypassing is presented. Fine-grained DVFS (Dynamic Voltage and Frequency Scaling) is an effective power reduction technique. We propose run-time reconfigurable interconnect on each inter-router channel to minimize the latency and energy overhead. When two routers are running on the same frequency, FIFO-channel is bypassed by direct interconnect. Distributed algorithm is designed for per-core DVFS. Proper power delivery and clocking scheme are integrated. Simulation shows significant energy and latency saving.

  • 139. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    System-level exploration of run-time clusterization for energy-efficient on-chip communication2009Inngår i: 2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42, 2009, s. 63-68Konferansepaper (Fagfellevurdert)
    Abstract [en]

    System-level exploration of run-time power clusterization for energy-efficient on-chip communication is presented. Facilitated by multiple on-chip power-delivery-networks, areas of heavy or low traffics can be dynamically identified and adaptively supplied with new power schemes. This method is superior to design-time voltage island partitioning, in dealing with unpredictable spatial and temporal variations of communication traffics in large NoCs. Architectural design of the platform and online iterative configuration process are presented. The effectiveness of the proposed approach is demonstrated quantitatively on a NoC simulator with 65nm power models. With synthetic traffic traces characterizing various communication patterns, run-time power clusterization achieves considerable energy benefits compared to existing energy-efficient architectures (9% - 42% lower). The latency penalty is predictable and moderately bounded with minimal area overhead. The proposed architecture presents an ideal tradeoff, prioritizing energy efficiency, for massively parallel on-chip computing.

  • 140.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Plosila, J.
    Isoaho, Jouni
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    HAMSoC: A Monitoring-Centric Design Approach for Adaptive Parallel Computing2011Inngår i: Autonomic Networking-on-Chip: Bio-inspired Specification, Development and Verification / [ed] Phan Cong-Vinh, Taylor & Francis, 2011, s. 135-164Kapittel i bok, del av antologi (Annet vitenskapelig)
  • 141. Guang, Liang
    et al.
    Plosila, J.
    Isoaho, Jouni
    Tenhunen, Hannu
    University of Turku, Finland.
    Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification2010Inngår i: International Journal of Embedded and Real-Time Communication Systems (IJERTCS), ISSN 1947-3176, Vol. 1, nr 2, s. 86-105Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, the authors present a formal specification of a novel design paradigm, hierarchical agent monitored SoCs (HAMSOC). The paradigm motivates dynamic monitoring in a hierarchical and distributed manner, with adaptive agents embedded for local and global operations. Formal methods are of essential importance to the development of such a novel and complex platform. As the initial effort, functional specification is indispensable to the non-ambiguous system modeling before potential property verification. The formal specification defines the manner by which the system can be constructed with hierarchical components and the representation of run-time information in modeling entities and every type of the monitoring operations. The syntax follows the standard set theory with additional glossary and notations introduced to facilitate practical SoC design process. A case study of hierarchical monitoring for power management in NoC (Network-on-chip), written with the formal specification, is demonstrated

  • 142.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Plosila, J.
    Isoaho, Jouni
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    Hierarchical Agent Monitoring Services on Reconfigurable NoC Platform: A Formal Approach2009Inngår i: Workshop Digest of DSNOC 09 (Diagnostic Services in Network-on-Chips), 2009, s. 98-101Konferansepaper (Fagfellevurdert)
  • 143. Guang, Liang
    et al.
    Rantala, P.
    Nigussie, Ethiopia
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Low-latency and Energy-efficient Monitoring Interconnect for Hierarchical-agent-monitored NoCs2008Inngår i: Norchip - 26th Norchip Conference, Formal Proceedings, 2008, s. 227-232Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents quantitative analysis of monitoring interconnect architecture alternatives in hierarchical agent-based NoC platform. Hierarchical monitoring design methodology provides scalable dynamic management services with agents monitoring different levels. To enable low-latency and lowenergy agent communication, we examined three interconnect alternatives: TDM-based virtual channeling, unified dedicated monitoring network, and separate dedicated monitoring networks. With Orion and Cadence simulators, we estimated the energy and latency of monitoring communications on the three architectures for an 8*8 mesh network in 65nm technology. The results suggest that separate dedicate links mostly minimize the communication delay and energy consumption (66.7% and 82.1% respectively compared to TDM-based interconnect), while incurring moderate area penalty.

  • 144. Guang, Liang
    et al.
    Yang, B.
    Plosila, J.
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hierarchical Agent Monitoring Design Platform - towards Self-aware and Adaptive Embedded Systems2011Inngår i: PECCS 2011 - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems, 2011, s. 573-581Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Hierarchical agent monitoring design platform(HAM) is presented as a generic design approach for the emerging self-aware and adaptive embedded systems. Such systems, with various existing proposals for different advanced features, call for a concrete, practical and portable design approach. HAM addresses this necessity by providing a scalable and generically applicable design platform. This paper elaborately describes the hierarchical agent monitoring architecture, with extensive reference to the state-of-the-art technology in embedded systems. Two case studies are exemplified to demonstrate the design process and benefits of HAM design platform. One is about hierarchical agent monitored Network-on-Chip with quantitative experiments of hierarchical energy management. The other one is a projectional study of applying HAM on smart house systems, focusing on the design for enhanced dependability.

  • 145.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Yang, B.
    Department of Information Technology, University of Turku, Finland.
    Plosila, J.
    Department of Information Technology, University of Turku, Finland.
    Latif, Khalid
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    Hierarchical power monitoring on NoC - a case study for hierarchical agent monitoring design approach2010Inngår i: 28th Norchip Conference, NORCHIP 2010, 2010, s. 5669428-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A case study is presented for hierarchical agent monitoring design approach, which provides a high level abstraction for designing monitoring functions on massively parallel and distributed systems. The case study features hierarchical power monitoring on NoC platforms, where each level of agents perform specific monitoring operations based on their granularity. The monitoring hierarchy and operations are specified by a formal language for consistent and non-ambiguous system design. Various benchmarks are mapped onto NoCs, running with hierarchical power monitoring agents. Quantitative evaluations are performed in terms of energy efficiency, communication latency, and silicon overhead.

  • 146.
    Guang, Liang
    et al.
    Department of Information Technology, University of Turku, Finland.
    Yin, A.
    Rantala, P.
    Nigussie, Ethiopia
    Department of Information Technology, University of Turku, Finland.
    Liljeberg, P.
    Isoaho, Jouni
    Department of Information Technology, University of Turku, Finland.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    Hierarchical Power Monitoring for On-chip Networks2009Inngår i: Proceedings of Work in Progress Session in Euromicro PDP 2009 Conference, 2009Konferansepaper (Fagfellevurdert)
  • 147. Habib, A.
    et al.
    Amin, Yasar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Engineering and Technology (UET), Pakistan.
    Azam, M. A.
    Loo, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
    Frequency signatured directly printable humidity sensing tag using organic electronics2017Inngår i: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 14, nr 3Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper chipless RFID tag, capable of carrying 9-bit data is presented. The tag is optimized for several flexible substrates. With growing information and communication technology, sensor integration with data transmission has gained significant attention. Therefore, the tag with the same dimension is then optimized using paper substrate. For different values of permittivity, the relative humidity is observed. Hence, besides carrying information bits, the tag is capable of monitoring and sensing the humidity. The overall dimension of the tag comprising of 9 ring slot resonators is 7 mm. Due to its optimization on the paper substrate, the tag can be an ideal choice for deploying in various low-cost sensing applications.

  • 148. Habib, A.
    et al.
    Asif, R.
    Fawwad, M.
    Amin, Yasar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Engineering and Technology, Pakistan.
    Loo, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
    Directly printable compact chipless RFID tag for humidity sensing2017Inngår i: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 14, nr 10Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this letter, 8-bit paper based printable chipless tag is presented. The tag not only justifies the green electronic concept but also it is examined for sensing functionality. The compact tag structure comprises of seven L-shaped and one I-shaped dipole structure. These conducting tracks/dipole structures are of silver nano-particle based ink having a conductivity of 1.1 × 107 S/m. Each conducting track yields one bit corresponding to one peak. The tag design is optimized and analyzed for three different flexible substrates i.e. paper, Kapton® HN, and PET. The tag has ability to identify 28 = 256 objects, by using different binary combinations. The variation in length of particular conducting strip results in a shift of peak for that specific conducting track. This shift corresponds to logic state-1. The response of the tag for paper, Kapton® HN, and PET substrates is observed in the frequency band of 2.2-6.1 GHz, 2.4-6.3 GHz, and 2.5-6.5 GHz, respectively. The tag has an attractive nature because of its easy printability and usage of low-cost, flexible substrates. The tag can be deployed in various low-cost sensing applications.

  • 149. Habib, Ayesha
    et al.
    Ansar, Sohaira
    Akram, Adeel
    Azam, Muhammad Awais
    Amin, Yasar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Engineering and Technology, Pakistan.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar. University of Turku, Finland.
    Directly Printable Organic ASK Based Chipless RFID Tag for IoT Applications2017Inngår i: Radioengineering, ISSN 1210-2512, E-ISSN 1805-9600, Vol. 26, nr 2, s. 453-460Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A chipless RFID tag with unique ASK encoding technique is presented in this paper. The coding efficiency is enhanced regarding tag capacity. The amplitude variations of the backscattered RFID signal is used for encoding data instead of OOK Strips of different widths are used to have amplitude variations. The ASK technique is applied using three different substrates of Kapton (R) HN, PET, and paper. To incorporate ASK technique, dual polarized rhombic shaped resonators are designed. These tags operate in the frequency range of 3.1-10.6 GHz with size of 70 x 42 mm(2). The presented tags are flexible and offer easy printability. The paper-based decomposable organic tag appears as an ultra low-cost solution for wide scale tracking. This feature enables them to secure a prominent position in the emerging fields of IoT and green electronics.

  • 150. Haghbayan, M. -H
    et al.
    Kanduri, A.
    Rahmani, A. -M
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Liljeberg, P.
    Jantsch, A.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    MapPro: Proactive runtime mapping for dynamic workloads by quantifying ripple effect of applications on networks-on-chip2015Inngår i: Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015, Association for Computing Machinery (ACM), 2015Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Increasing dynamic workloads running on NoC-based many-core systems necessitates efficient runtime mapping strategies. With an unpredictable nature of application profiles, selecting a rational region to map an incoming application is an NP-hard problem in view of minimizing congestion and maximizing performance. In this paper, we propose a proactive region selection strategy which prioritizes nodes that offer lower congestion and dispersion. Our proposed strategy, MapPro, quantitatively represents the propagated impact of spatial availability and dispersion on the network with every new mapped application. This allows us to identify a suitable region to accommodate an incoming application that results in minimal congestion and dispersion. We cluster the network into squares of different radii to suit applications of different sizes and proactively select a suitable square for a new application, eliminating the overhead caused with typical reactive mapping approaches. We evaluated our proposed strategy over different traffic patterns and observed gains of up to 41% in energy efficiency, 28% in congestion and 21% dispersion when compared to the state-of-the-art region selection methods. Copyright 2015 ACM.

1234567 101 - 150 of 536
RefereraExporteraLink til resultatlisten
Permanent link
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf