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  • 151.
    Farahini, Nasim
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A conceptual custom super-computer design for real-time simulation of human brain2013In: 2013 21st Iranian Conference on Electrical Engineering, ICEE 2013, 2013, p. 1-6Conference paper (Refereed)
    Abstract [en]

    In this paper, we introduce BRIC, a novel custom multi-chip digital computer architecture for simulating in realtime a model of human brain in form of a spiking Bayesian Confidence Propagation Neural Network (BCPNN). The design is conceptually dimensioned for available technology in 2015-2020 with the estimated size of a pizza box, consuming less than 3 kWs of power, delivering 800 Teraflops/sec (single precision multiply operation) and 30 TBs of memory. To the best of our knowledge, this will be the smallest and lowest power real-time brain simulation engine if manufactured. The silicon and computational efficiencies come from use of 3D memory stacking, innovation in algorithm and architectural customization. The chip will be programmable allowing experimentation with variants of the BCPNN brain model.

  • 152.
    Farahini, Nasim
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lansner, Anders
    KTH, School of Computer Science and Communication (CSC), Computational Biology, CB.
    Clermidy, F.
    Svensson, C.
    A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain2014In: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE , 2014, p. 578-585Conference paper (Refereed)
    Abstract [en]

    A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

  • 153.
    Farahini, Nasim
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Paul, Kolin
    Indian Institute of Technology, Delhi, India.
    Distributed Runtime Computation of Constraints for Multiple Inner Loops2013In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, New York: IEEE , 2013, p. 389-395Conference paper (Refereed)
    Abstract [en]

    This paper presents hardware solution for runtime computation of loop constraints and synchronizing delays for multiple inner loops in parallel distributed implementation of digital signal processing sub-systems. Methods to map and generate the runtime computation code for loop constraints and synchronizing delays are also presented. Compared to the traditional methods, the proposed solution achieves 55% average code compaction and 32.7% average performance improvement. The solution has modest hardware cost that increases linearly with the dimension of the architecture and has no performance penalty. Results from multiple realistic examples are presented, analyzed and compared to the traditional methods.

  • 154.
    Farahini, Nasim
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sohofi, Hassan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jafri, Syed M. A. H.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tajammul, Muhammad Adeel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Paul, Kolin
    Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric2014In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 38, no 8, p. 788-802Article in journal (Refereed)
    Abstract [en]

    This paper presents a hardware based solution for a scalable runtime address generation scheme for DSP applications mapped to a parallel distributed coarse grain reconfigurable computation and storage fabric. The scheme can also deal with non-affine functions of multiple variables that typically correspond to multiple nested loops. The key innovation is the judicious use of two categories of address generation resources. The first category of resource is the low cost AGU that generates addresses for given address bounds for affine functions of up to two variables. Such low cost AGUs are distributed and associated with every read/write port in the distributed memory architecture. The second category of resource is relatively more complex but is also distributed but shared among a few storage units and is capable of handling more complex address generation requirements like dynamic computation of address bounds that are then used to configure the AGUs, transformation of non-affine functions to affine function by computing the affine factor outside the loop, etc. The runtime computation of the address constraints results in negligibly small overhead in latency, area and energy while it provides substantial reduction in program storage, reconfiguration agility and energy compared to the prevalent pre-computation of address constraints. The efficacy of the proposed method has been validated against the prevalent address generation schemes for a set of six realistic DSP functions. Compared to the pre-computation method, the proposed solution achieved 75% average code compaction and compared to the centralized runtime address generation scheme, the proposed solution achieved 32.7% average performance improvement.

  • 155.
    Farahini, Nasim
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tajammul, Muhammad Adeel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shami, Muhammad Ali
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Guo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ye, Wei
    Huawei, Wireless Beijing Division, China.
    39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation2013In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE , 2013, p. 1448-1451Conference paper (Refereed)
    Abstract [en]

    This paper presents an industrial case study of using a Coarse Grain Reconfigurable Architecture (CGRA) for a multi-mode accelerator for two kernels: FFT for the LTE standard and the Correlation Pool for the UMTS standard to be executed in a mutually exclusive manner. The CGRA multi-mode accelerator achieved computational efficiency of 39.94 GOPS/watt (OP is multiply-add) and silicon efficiency of 56.20 GOPS/mm2. By analyzing the code and inferring the unused features of the fully programmable solution, an in-house developed tool was used to automatically customize the design to run just the two kernels and the two efficiency metrics improved to 49.05 GOPS/watt and 107.57 GOPS/mm2. Corresponding numbers for the ASIC implementation are 63.84 GOPS/watt and 90.91 GOPS/mm2. Though the ASIC’s silicon and computational efficiency numbers are slightly better, the engineering efficiency of the pre-verified/characterized CGRA solution is at least 10X better than the ASIC solution.

  • 156. Fattah, M.
    et al.
    Airola, A.
    Ausavarungnirun, R.
    Mirzaei, N.
    Liljeberg, P.
    Plosila, J.
    Mohammadi, S.
    Pahikkala, T.
    Mutlu, O.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A low-overhead, fully-distributed, guaranteed-delivery routing algorithm for faulty network-on-chips2015In: Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015, ACM Digital Library, 2015Conference paper (Refereed)
    Abstract [en]

    This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips. The algorithm is the first to provide all of the following properties at the same time: 1) fully-distributed with no centralized component, 2) guaranteed delivery (it guarantees to deliver packets when a path exists between nodes, or otherwise indicate that destination is unreachable, while being deadlock and livelock free), 3) low area cost, 4) low reconfiguration overhead upon a fault. To achieve all these properties, we propose Maze-routing, a new variant of face routing in on-chip networks and make use of deflections in routing. Our evaluations show that Maze-routing has 16X less area overhead than other algorithms that provide guaranteed delivery. Our Maze-routing algorithm is also high performance: for example, when up to 5 links are broken, it provides 50% higher saturation throughput compared to the state-of-the-art. Copyright 2015 ACM.

  • 157. Feng, C. -C
    et al.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, M. -X
    Li, J. -W
    A 1-cycle 2 GHz bufferless router for network-on-chip2011In: Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, ISSN 1001-2486, Vol. 33, no 6, p. 42-47Article in journal (Refereed)
    Abstract [en]

    Recently, bufferless router, which does not need buffers, has become a low-cost solution for Network-on-Chip. To improve the performance of the bufferless router, a 1-cycle high-performance bufferless router was proposed for Network-on-Chip. The router used a simple permutation network instead of the serialized switch allocator and the crossbar to achieve high performance. Compared with the virtual channel router and the baseline bufferless router, the proposed bufferless router can achieve the frequency of 2 GHz with small area cost under TSMC 65 nm technology. Simulation results under both synthetic and application workloads demonstrate that the proposed bufferless router achieves much less average packet latency than the virtual channel router and other bufferless routers.

  • 158. Feng, C.
    et al.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, M.
    Xing, Z.
    Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router2013In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 21, no 6, p. 1053-1066Article in journal (Refereed)
    Abstract [en]

    Continuing decrease in the feature size of integrated circuits leads to increases in susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution for a bufferless network-on-chip, including an on-line fault-diagnosis mechanism to detect both transient and permanent faults, a hybrid automatic repeat request, and forward error correction link-level error control scheme to handle transient faults and a reinforcement-learning-based fault-tolerant deflection routing (FTDR) algorithm to tolerate permanent faults without deadlock and livelock. A hierarchical-routing-table-based algorithm (FTDR-H) is also presented to reduce the area overhead of the FTDR router. Synthesized results show that, compared with the FTDR router, the FTDR-H router can reduce the area by 27% in an 8×8 network. Simulation results demonstrate that under synthetic workloads, in the presence of permanent link faults, the throughput of an 8×8 network with FTDR and FTDR-H algorithms are 14% and 23% higher on average than that with the fault-on-neighbor (FoN) aware deflection routing algorithm and the cost-based deflection routing algorithm, respectively. Under real application workloads, the FTDR-H algorithm achieves 20% less hop counts on average than that of the FoN algorithm. For transient faults, the performance of the FTDR router can achieve graceful degradation even at a high fault rate. We also implement the fault-tolerant deflection router which can achieve 400 MHz in TSMC 65-nm technology.

  • 159.
    Feng, Chaochao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, Jinwen
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, Minxuan
    Evaluation of Deflection Routing on Various NoC Topologies2011In: Proceedings of the IEEE International Conference on ASIC (ASICON), 2011Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose two novel deflection routing algorithms for de Bruijn and Spidergon NoCs and evaluate the performance of the deflection routing on 5 NoC topologies with different synthetic traffic patterns. We also synthesize the routers in various NoC topologies with TSMC 65nm technology. The evaluation results illustrate that the performance of deflection routing is susceptible to the network topology and traffic pattern. The results can also guide the NoC architect to choose the suitable NoC topology for the specific application.

  • 160.
    Feng, Chaochao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liao, Z.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhao, Z.
    Performance analysis of on-chip bufferless router with multi-ejection ports2015In: Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015, IEEE conference proceedings, 2015Conference paper (Refereed)
    Abstract [en]

    In general, the bufferless NoC router has only one local output port for ejection, which may lead to multiple arriving flits competing for the only one output port. In this paper, we propose a reconfigurable bufferless router in which the number of ejection ports can be configured as 2, 3 and 4. Simulation results demonstrate that the average packet latency of the routers with multi-ejection ports is 18%, 10%, 6%, 14%, 9% and 7% on average less than that of the router with 1 ejection ports under six synthetic workloads respectively. For application workloads, the average packet latency of the router with more than two ejection ports is slightly better than the router with only one ejection port, which can be neglect. Making a compromise of hardware cost and performance, it can be concluded that it is no need to implement bufferless routers with 3 and 4 ejection ports, as the router with 2 ejection ports can achieve almost the same performance as the routers with 3 and 4 ejection ports.

  • 161.
    Feng, Chaochao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, Jinwen
    Zhang, Minxuan
    A Reconfigurable Fault-tolerant Deflection Routing Algorithm Based on Reinforcement Learning for Networks-on-Chip2010In: Proceedings of the International Workshop on Network on Chip Architectures (NoCArc), 2010Conference paper (Refereed)
  • 162.
    Feng, Chaochao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, Jinwen
    Zhang, Minxuan
    FoN: Fault-on-Neighbor aware Routing Algorithm for Networks-on-Chip2010In: Proceedings - IEEE International SOC Conference, SOCC 2010, 2010, p. 441-446Conference paper (Refereed)
    Abstract [en]

    Reliability has become a key issue of Networks-on-Chip (NoC) as the CMOS technology scales down to the nanoscale domain. This paper proposes a Fault-on-Neighbor (FoN) aware deflection routing algorithm for NoC which makes routing decision based on the link status of neighbor switches within 2 hops to avoid fault links and switches. Simulation results demonstrate that in the presence of faults, the saturated throughput of the FoN switch is 13% higher on average than a cost-based deflection switch for 88 mesh. The average hop counts can be up to 1.7 less than the cost-based switch. The FoN switch is also synthesized using 65nm TSMC technology and it can work at 500MHz with small area overhead.

  • 163.
    Feng, Chaochao
    et al.
    National University of Defense Technology, China.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, Minxuan
    A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip2012In: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E95D, no 5, p. 1519-1522Article in journal (Refereed)
    Abstract [en]

    In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 7 x 7 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.

  • 164.
    Feng, Chaochao
    et al.
    National University of Defense Technology, China.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, Minxuan
    Yang, Xianju
    Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip2012In: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E95D, no 4, p. 1052-1061Article in journal (Refereed)
    Abstract [en]

    In this paper, we propose three Deflection-Routing-based Multicast (DRM) schemes for a bufferless NoC. The DRM scheme without packets replication (DRM_noPR) sends multicast packet through a non-deterministic path. The DRM schemes with adaptive packets replication (DRM_PR_src and DRM_PR_all) replicate multicast packets at the source or intermediate node according to the destination position and the state of output ports to reduce the average multicast latency. We also provide fault-tolerant supporting in these schemes through a reinforcement-learning-based method to reconfigure the routing table to tolerate permanent faulty links in the network. Simulation results illustrate that the DRM_PR_all scheme achieves 41%, 43% and 37% less latency on average than that of the DRM_noPR scheme and 27%, 29% and 25% less latency on average than that of the DRM_PR_src scheme under three synthetic traffic patterns respectively. In addition, all three fault-tolerant DRM schemes achieve acceptable performance degradation at various link fault rates without any packet lost.

  • 165. Feng, Chaochao
    et al.
    Zhang, Minxuan
    Li, Jinwen
    Jiang, Jiang
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Low-overhead Fault-aware Deflection Routing Algorithm for 3D Network-on-Chip2011In: Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 2011, p. 19-24Conference paper (Refereed)
  • 166. Feng, Chien-Hsiung
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ismail, Mohammed
    Olsson, Håkan
    Analysis of Non-linearities in rf CMOS Amplifiers ICECS1999In: Proc. The 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, p. 137-140Conference paper (Refereed)
  • 167.
    Feng, Yi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mueller, Matthias
    Xaar Jet AB.
    Zapka, Werner
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Inkjet Printed UWB Impulse-based Wireless Sensor for Flexible Electronics2012In: Gigahertz Symposium, 2012Conference paper (Other academic)
  • 168.
    Feng, Yi
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University, China.
    Design of a Printable Multi-Functional Sensor for Remote Monitoring2011In: 2011 IEEE SENSORS Proceedings, IEEE Sensors Council, 2011, p. 675-678Conference paper (Refereed)
    Abstract [en]

    This paper proposes a novel printable multi-functional passive sensor for remote monitoring. The sensor mainly consists of a series of pairs of transmission lines and sensing resistors whose resistances vary with one physical parameter. A short-duration radio-frequency pulse as interrogation signal travels along the transmission line and is partially reflected at each resistor due to impedance mismatch. By measuring the energies of the discrete reflected pulses in time domain, all the physical parameters could be detected simultaneously. This design not only saves complex circuitry but also enables easy adaptation for detecting multiple parameters. We have theoretically analyzed the sensor assuming it has an arbitrary number of sensing resistors. The introduced algorithm between the pulse energies and resistances is verified by simulation. As a prototype, an inkjet-printed sensor on polyimide foil is presented. The experimental measurement has successfully proven the design concept. 

  • 169.
    Feng, Yi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lopez Cabezas, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhang, Zhi-Bin
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Flexible UHF Resistive Humidity Sensors Based on Carbon Nanotubes2012In: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 12, no 9, p. 2844-2850Article in journal (Refereed)
    Abstract [en]

    This paper presents the investigation of the resistive humidity-sensing properties of multi-walled carbon nanotubes (MWCNTs). MWCNTs functionalized by acid treatment (f-MWCNTs) exhibit rather high sensitivity in resistance toward humidity, owing to the presence of carboxylic groups on the nanotube surface. By integrating the f-MWCNTs resistor into a wireless sensor platform, flexible humidity sensors for ultra-high frequency applications are investigated. The operating frequency range of the sensor is dramatically increased from 600 MHz to 2 GHz by adjusting the resistor-electrodes' configuration. This enhancement is predominately attributed to the variation in parasitic capacitance between the resistor-electrodes.

  • 170.
    Feng, Yi
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mueller, Matthias
    Xaar Jet AB.
    Liebeskind, Jens
    Xaar Jet AB.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Schmidt, Wolfgang
    Felix Schoeller GmbH & Co. KG.
    Zapka, Werner
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Characterization of Inkjet Printed Coplanar Waveguides for Flexible Electronics2011In: NIP27: International Conference on Digital Printing Technologies and Digital Fabrication 2011: TECHNICAL PROGRAMS, ABSTRACTS, AND CD PROCEEDINGS, IS & T , 2011, p. 454-457Conference paper (Refereed)
    Abstract [en]

    The low conductivity and thin layers of the inkjet-printed metal conductors have always been a big concern in paper-based printed electronics for high frequency applications. To provide the fundamental knowledge, the high frequency characteristics of inkjet-printed coplanar waveguides on paper substrate were studied experimentally in terms of characteristic impedance and conductor losses using the time domain reflectometry technique. The influences of different printing settings and of geometric parameters on the waveguide's properties were investigated. Considering the measurement accuracy in high frequency characterization, one sample with an impedance of 51.2Ω was achieved. The electrical stability of the samples was also studied and explained. In addition, one waveguide sample was printed in a way that the pattern area with the highest current density is thickened. This variable ink-layer thickness approach has successfully been proven as a promising solution to reduce the conductor losses and yet consuming less ink.

  • 171.
    Feng, Yi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mueller, Maik
    Xaar Jet AB.
    Lopez Cabezas, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mantysalo, Matti
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zapka, Werner
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Fabrication and performance evaluation of ultralow-cost inkjet-printed chipless RFID tags2012Conference paper (Refereed)
    Abstract [en]

    This paper studies the performance of inkjet-printed chipless RFID tags based on planar inductor-capacitor resonant circuits. Besides using double-sided printing, a sandwiching process is introduced to fabricate the tags in order to eliminate the need of through-substrate via and match roll-to-roll processing. Due to lower conductivity (~1.25E+7 S/m) and smaller thickness (~1.7μm) of printed conductors with silver nanoparticle ink, the resonant peaks of inkjet-printed tags exhibit around as twice of half-power bandwidth and 60% of maximum reading distance as the etched tags from bulk copper. Nevertheless, the inkjet-printed tag performance is sufficient for many applications, and it can be adjusted and improved by printing and sintering processes.

  • 172.
    Feng, Yi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mäntysalo, Matti
    Tampere University of Technology, Finland.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Electrical and humidity-sensing characterization of inkjet-printed multi-walled carbon nanotubes for smart packaging2013In: IEEE SENSORS 2013 - Proceedings, IEEE , 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Printing is considered a cost-effective way to fabricate electronics on unconventional substrates enabling, for example, smart packaging. Functionalized multi-walled carbon nanotubes (f-MWCNTs) having carboxylic groups on their surfaces possess great potential as flexible resistive humidity sensor. In this paper, we report on the inkjet printing and characterization of f-MWCNTs in terms of sheet resistance and humidity-sensitivity. Stable f-MWCNTs ink is formulated using aqueous ethylene glycol as solvent. Sheet resistance of printed f-MWCNTs films on polyimide foil reduces by increasing the number of printed layers as well as post-printing annealing temperature. Meanwhile, the raised annealing temperature degrades the films' humidity-sensitivity, which could be explained by the loss of the carboxylic groups. The electrical and sensing properties of f-MWCNTs also have a negative temperature coefficient regarding ambient temperature, which should be considered in practical application.

  • 173.
    Fernaeus, Ylva
    et al.
    KTH, School of Computer Science and Communication (CSC), Media Technology and Interaction Design, MID.
    Tsaknaki, Vasiliki
    KTH, School of Computer Science and Communication (CSC), Media Technology and Interaction Design, MID.
    Murer, M.
    Solsona Belenguer, Jordi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Handcrafting electronic accessories using 'raw' materials2014In: TEI '14 Proceedings of the 8th International Conference on Tangible, Embedded and Embodied Interaction, 2014, p. 369-372Conference paper (Refereed)
    Abstract [en]

    In this studio we explore the design of interactive electronic accessories made from natural materials such as wood, copper, silver, wool and leather. A set of handcrafted sensor components along with easy to use sensor boards that connect with example smartphone software, will be utilized as a toolkit for the studio activities. Participants will, through hands-on activity, create with, learn about and discuss the role of natural materials in the design of wearable interactive designs.

  • 174.
    Färm, Petra
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kuehlmann, Andreas
    Cadence Berkeley Labs, Berkeley, CA 94704, United States .
    Integrated logic synthesis using simulated annealing2011In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2011, p. 407-410Conference paper (Refereed)
    Abstract [en]

    Conventional logic synthesis flows are composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions. In this paper, we present a method for integrating the three synthesis phases using an annealing algorithm as optimization framework. The annealing-based search is driven by a complex objective function, combining both technology independent as well as technology dependent optimization criteria. Our experimental results shown that, on average, the presented approach can improve the area and delay of circuits optimized with script rugged of SIS by 11.2% and 32.5% respectively.

  • 175.
    Gabry, Frédéric
    et al.
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Li, Nan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Schrammar, Nicolas
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Girnyk, Maksym
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Rasmussen, Lars K.
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Skoglund, Mikael
    KTH, School of Electrical Engineering (EES), Communication Theory. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    On the Optimization of the Secondary Transmitter's Strategy in Cognitive Radio Channels with Secrecy2014In: IEEE Journal on Selected Areas in Communications, ISSN 0733-8716, E-ISSN 1558-0008, Vol. 32, no 3, p. 451-463Article in journal (Refereed)
    Abstract [en]

    This paper investigates cooperation for secrecy in cognitive radio networks. In particular, we consider a four-node cognitive scenario where the secondary receiver is treated as a potential eavesdropper with respect to the primary transmission. The cognitive transmitter can help the primary transmission, and it should also ensure that the primary message is not leaked to the secondary user. We consider two cognitive scenarios depending on whether the secondary transmitter knows the primary message or not. In the first case, the secondary transmitter is unaware of the primary transmitter's message and acts as a helping interferer to enhance the secrecy of the primary transmission, whereas in the second case, relaying of the primary message is also within its capabilities. First, we find achievable rate regions for these two scenarios in the case of AWGN channels. We then investigate three different optimization problems: the maximization of the primary rate, the maximization of the secondary rate and the minimization of the secondary transmit power. For these optimization problems, we find closed-form expressions in important special cases. Furthermore, we analyze the cooperation between the primary and secondary transmitters from a game-theoretic perspective. We model their interaction as a Stackelberg game, for which we define and find the Stackelberg equilibrium. Finally, we use numerical examples to illustrate the rate regions, the three optimizations, and the impact of the Stackelberg game on the achievable rates and on the transmission strategies of the secondary transmitter.

  • 176.
    Gao, Jie
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Intelligent and Interactive Package Based on RFID and WSN2011Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

       An intelligent and interactive package can interact with people smartly, safely and friendly. It involves many technologies such as electronics, optics, biologic, magnetics and electro-mechanics. By combined with Radio Frequency Identification (RFID) and Wireless Sensor Network (WSN), intelligent and interactive packaging technology has been an emerging and global research topic over the years.

       In this thesis, a new technology, named Controlled Delamination Material (CDM), is introduced. It was primarily used in aerospace applications in the past and further developed by Stora Enso AB. A CDM product can delaminate easily in a controlled way by the use of electrical current. This concept opens up many interesting application possibilities for the traditional packaging industry. In order to understand the delamination mechanism, some related work on the electrochemical characteristics of the material showed the possibility to facilitate the interactive packaging system design.

       A paper-based package which is integrated with RFID system and CDM is presented to realize an intelligent and interactive system. It can be opened automatically through a finger touch. The opening action is controlled electrically by RFID system. The test results of the demonstration have proved feasibility of the solution and shown the potential for mass production.

        Following this solution, an interactive pharmaceutical package for pervasive healthcare is proposed by using EPCglobal Gen2 RFID technology. A Gen2 RFID system significantly increases the efficiency of information exchange, and reduces the medication error rate and the possibility of sale counterfeit drugs. It makes the medication accessible for patient only at the prescribed dose and time, and at the same time, the information for the action of taking medication will be delivered to the doctor as well. Such interactive pharmaceutical package not only gives unprecedented high patient compliance, but also improves the communication between patients and healthcare staffs.

        By integrating WSN with various bio-chemical sensors, in addition to temperature and moisture sensors, more kinds of information can be involved in the intelligent and interactive packaging communication system. It enhances the functionalities of the package such as rotecting the integrity and effectiveness of product, providing safety information details, and being child resistance, senior friendliness

     

  • 177.
    Gao, Jie
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Pang, Zhibo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A Study on Electrical Properties of Controlled Delamination MaterialManuscript (preprint) (Other academic)
    Abstract [en]

    Primarily used in aerospace applications, Controlled Delamination Material (CDM) has recently drawn attention to the traditional packaging industry due to its low-cost and electrical easy-open. Sinuate®, a CDM product, consists of two aluminum foils bonded together with a conductive epoxy adhesive. When applying a little electricity on its surface, the material can open easily without violence and release without residue. In this paper, a brief introduction on Sinuate® will be presented at first. And some test results on the electrical properties of the joint opening/detaching process will be shown and analyzed.

  • 178.
    Gao, Jie
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Pang, Zhibo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Interactive Packaging Solutions Based on RFIDTechnology and Controlled Delamination Material2010Conference paper (Refereed)
    Abstract [en]

    Interactive packaging is an emerging research area in recent years. It brings people convenient and smart lives, reduces consumption of traditional packaging materials and direct or indirect labor costs as well. Being integrated in interactive packaging, Radio Frequency Identification (RFID) technology becomes one of the most proactive development enablers. In this paper, an interactive and intelligent packaging solution integrating passive RFID system and Controlled Delamination Material (CDM) is given at first. Package opening action is electrically controlled by the RFID system. CDM is primarily used in aerospace applications in the past and the conductor/adhesive joint can be easily opened by applying a little electric power on to the material. Some related works will be shown about the electrochemical characteristics of CDM in order to facilitate the system design. A demonstration system was developed and the test results have proved feasibility of the solution and shown the potential of low cost for mass production. Based on this solution, an interactive medication package for pervasive healthcare is further developed, using EPCglobal Gen2 RFID technology. It will make the medication being accessible for patient only at the prescribed dose and time, and medication taking information will be delivered as well. Such medication package will not only give unprecedented high patient compliance, but also improve the communication between patients and healthcare staffs.

  • 179.
    Geng, Yang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Hybrid Integration of Active Bio-signal Cable with Intelligent Electrode: Steps toward Wearable Pervasive-Healthcare Applications2012Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Personalized and pervasive healthcare help seamlessly integrate healthcare and wellness into people’s daily life, independent of time and space. With the developments in biomedical sensing technologies nowadays, silicon based integrated circuits have shown great advantages in terms of tiny physical size, and low power consumption. As a result, they have been found in many advanced medical applications. In the meanwhile, printed electronics is considered as a promising approach enabling cost-effective manufacturing of thin, flexible, and light-weight devices. A hybrid integration of integrated circuits and printed electronics provides a promising solution for the future wearable healthcare devices.

    This thesis first reviews the current approaches for bio-electric signal sensing and the state-of-the-art designs for biomedical circuit and systems. In the second part, the idea of Intelligent Electrode and Active Cable for wearable ECG monitoring systems is proposed. Based on this concept, we design and fabricate two customized IC chips to provide a single cable solution for long-term healthcare monitoring. The first chip is a digital ASIC with a serial communication protocol implemented on chip to support data and command packets transmission between different ASIC chips. Also, it has on-chip memory to buffer the digital bio-signal. An Intelligent Electrode is formed by embedding the ASIC chip into the conductive electrode. With the on-chip integrated communication protocol, a wired sensor network can be established enabling the single cable solution. The ASIC’s controlling logic is capable of making dynamic network management, thus endows the electrode with local intelligence. The second chip is a fully integrated mixed-signal SoC. In addition to the digital controller implemented and verified in the first chip, another 2 key modules are integrated: a tunable analog front end circuits, and a 6-input SAR ADC. The second chip works as a networked SoC sensor. The command-based network management is verified through functional tests using the fabricated SoCs. With the programmable analog front end circuits, the SoC sensor can be configured to detect a variety of bio-electric signals. EOG, EMG, ECG, and EEG signals are successfully recorded through in-vivo tests.

    This research also explores the potential of using high accurate inkjet printing technology as an inexpensive integration method and enabling technology to design and fabricate bio-sensing devices. Performance evaluation of printed electrodes and interconnections on flexible substrates is made to examine the feasibility of applying them in the fabrication of Bio-Patch. The reliability of the inkjet printed sliver traces is evaluated via static bending tests. The measurement results prove that the printed silver lines can offer a reliable interconnection. In-vivo test results show that the quality of ECG signal sensed by the printed electrodes is comparable with the one gained by commercial electrodes.

    Finally, two Bio-Patch prototypes are presented: one is based on photo paper substrate, the other on polyimide substrate. These two prototypes are implemented by heterogeneous integration of the silicon based SoC sensor with cost-effective printed electronics onto the flexible substrates. The measurement results indicate the SoC operates smoothly with the printed electronics. Clean ECG signal is successfully recorded from both of the implemented Bio-Patch prototypes. This versatile SoC sensor can be used in various applications according to specific requirements. And this heterogeneous system combining high-level integrated SoC technology and inkjet printing technique provides a promising solution for future personalized and pervasive healthcare applications.

  • 180. Grange, Matt
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Weerasekera, Roshan
    Pamunuwa, Dinesh
    Modeling the Efficiency of Stacked Silicon Systems: Computational, Thermal and Electrical Performance2011Conference paper (Refereed)
    Abstract [en]

    Technological advances in processor design have typically reliedon scaling feature size and frequency. Recently however, many new design choiceshave emerged partly due to the slowing of scaling:– Many-core architectures arebeginning to replace single-core ICs to circumvent 2-D bottlenecks, The number ofI/Os are on the rise, so the cost of off-chip transactions is becoming heftier. Moreover,3-D Integration may provide further performance benefits without investment in lowertechnology nodes. Understanding these trade-offs can provide guidelines to optimizethe architecture of future systems under performance, thermal and cost constraints.We have constructed a model and tool that assesses computational efficiency underthese criteria.

  • 181. Grange, Matt
    et al.
    Weerasekera, Roshan
    Pamunuwa, Dinesh
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Weldezion, Awet Yemane
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks2011In: NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip, ACM Digital Library, 2011, p. 57-64Conference paper (Refereed)
    Abstract [en]

    A general expression for the average distance for meshes of any dimension and radix, including unequal radices in different dimensions, valid for any traffic pattern under zero-load condition is formulated rigorously to allow its calculation without network-level simulations. The average distance expression is solved analytically for uniform random traffic and for a set of local random traffic patterns. Hot spot traffic patterns are also considered and the formula is empirically validated by cycle true simulations for uniform random, local, and hot spot traffic. Moreover, a methodology to attain closed-form solutions for other traffic patterns is detailed. Furthermore, the model is applied to guide design decisions. Specifically, we show that the model can predict the optimal 3-D topology for uniform and local traffic patterns. It can also predict the optimal placement of hot spots in the network. The fidelity of the approach in suggesting the correct design choices even for loaded and congested networks is surprising. For those cases we studied empirically it is 100%.

  • 182. Grecu, Cristian
    et al.
    Ivanov, Andre
    Pande, Partha
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Salminen, Erno
    Ogras, Umit
    Marculescu, Radu
    An Initiative towards Open Network-on-Chip Benchmarks2007Report (Other academic)
  • 183. Grimm, Christoph
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shukla, Sandeep
    Villar, Eugenio
    C-Based Design of Embedded Systems - Editorial2008In: EURASIP Journal on Embedded Systems, ISSN 1687-3955, E-ISSN 1687-3963, no 1, p. 243890-Article in journal (Other academic)
  • 184.
    Guang, L.
    et al.
    Turku Centre for Computer Science (TUCS).
    Nigussie, E.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Isoaho, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs2012In: System on Chip (SoC), 2012 International Symposium on, IEEE , 2012, p. 6376351-Conference paper (Refereed)
    Abstract [en]

    Comparative evaluations of centralized, clustered and distributed architectures, for energy management in NoCs, are presented. The paper starts with the systematic examination of the monitoring, decision-making, and reconfiguration processes in building coarse and fine-grained self-adaptation architectures. With examining the physical support in modern technology, network-wide, cluster-wide and per-node energy-management architectures on NoCs are presented, utilizing either voltage regulators or multiple on-chip power delivery networks (MPNs). To identify the effectiveness and efficiency of energy-performance tradeoffs, extensive quantitative simulations are performed with various temporal and spatially changing traffics. Based on the results, we can first observe that the centralized architecture can not adapt to the traffic's spatial locality for effective energy-performance tradeoff. Second, the distributed energy management has the lowest energy-delay product mostly attributed to the fast voltage switching of MPNs, while the synchronization incurs noticeable energy overhead. The clustered architecture, last but not least, is a suitable alternative when the advanced MPN technology is not available. It has low energy and energy-delay product, with very small energy overhead from the monitoring communication.

  • 185.
    Guang, L.
    et al.
    Turku Centre for Computer Science (TUCS).
    Nigussie, E.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Isoaho, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    HLS-DoNoC: High-level simulator for dynamically organizational NoCs2012In: Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on, IEEE , 2012, p. 89-94Conference paper (Refereed)
    Abstract [en]

    A high-level simulator is presented for the design and analysis of dynamically organizational Networks-on-Chip (DoNoCs). The DoNoC is able to organize statically or dynamically different network nodes for run-time coarse and fine grained reconfiguration, in particular power management. As an important step in the design flow, a simulator for early-stage design exploration is the focus of the paper. Built upon classic wormhole-based NoC architecture, the simulator is capable of experimenting diverse run-time monitoring and reconfiguration methods. In particular, dynamic clusterization can be performed with inter-cluster interfaces properly configured at the run-time. The simulator is flit-level accurate, trace-driven, and easy-to-reconfigure. It supports both synchronous and ratiochronous timing, and can provide the communication performance and power/energy consumption. The paper demonstrates the usage of the simulator in the design of various cluster-based power management schemes.

  • 186. Guang, L.
    et al.
    Nigussie, E
    Plosila, J.
    Isoaho, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Survey of self-adaptive NoCs with energy-efficiency and dependability2012In: International Journal of Embedded and Real-Time Communication Systems, ISSN 1947-3176, Vol. 3, no 2, p. 1-22Article, review/survey (Refereed)
    Abstract [en]

    The self-adaptive Network-on-Chip (NoC) is a promising communication architecture for massively parallel embedded systems. With constant technology scaling and the consequent stronger influence of process variations, the necessity of run-time monitoring and adaptive reconfiguration becomes widely acknowledged. This article presents a survey of existing techniques and methods, in particular for energy efficiency and dependability. The article firstly examines the motivation of self-adaptive computing in parallel embedded systems. A self-adaptive system model is abstracted, which is composed of goals, monitoring interface, and self-adaptation. Based on the model, the authors extensively survey previous works addressing adaptive NoCs with different monitoring techniques and reconfiguration methods, for power/energy optimization and dependability enhancement. Several design examples are elaborated which serve proper guiding purposes. The authors also identify important issues which are often overlooked or deserve more attention. The article provides review and insight for future design on this topic.

  • 187.
    Guang, L.
    et al.
    University of Turku, Finland.
    Nigussie, E
    University of Turku, Finland.
    Plosila, J.
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study2012In: International Journal of Adaptive, Resilient and Autonomic Systems, ISSN 1947-9220, E-ISSN 1947-9239, Vol. 3Article in journal (Refereed)
    Abstract [en]

    Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

  • 188.
    Guang, Liang
    et al.
    University of Turku, Finland.
    Jafri, Syed Mohammad Asad Hassan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Yang, Bo
    University of Turku Finland.
    Plosila, Juha
    University of Turku Finland.
    Hannu, Tenhunen
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Embedding Fault-Tolerance with Dual-Level Agents in Many-Core Systems2012In: First MEDIAN Workshop (MEDIAN'12), 2012Conference paper (Other academic)
    Abstract [en]

    Dual-level fault-tolerance is presented on many-core systems, provided by the software-based system agent and hardware-based local agents. The system agent performs fault-triggered energy-aware remapping with bandwidth constraints, addressing coarse-grained processor failures. The local agents achieve fine-grained link-level fault tolerance against transient and permanent errors. The paper concisely presents the architecture, dual-level fault-tolerant techniques and experiment results.

  • 189.
    Guang, Liang
    et al.
    University of Turku, Finland.
    Jafri, Syed Mohammad Asad Hassan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Yang, Bo
    University of Turku, Finland.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hierarchical supporting structure for dynamic organization in many-core computing systems2013In: PECCS 2013: Proceedings of the 3rd International Conference on Pervasive Embedded Computing and Communication Systems, 2013, p. 252-261Conference paper (Refereed)
    Abstract [en]

    Hierarchical supporting structures for dynamic organization in many-core computing systems are presented.With profound hardware variations and unpredictable errors, dependability becomes a challenging issue in theemerging many-core systems. To provide fault-tolerance against processor failures or performance degradation,dynamic organization is proposed which allows clusters to be created and updated at the run-time. Hierarchicalsupporting structures are designed for each level of monitoring agents, to enable the tracing, storingand updating of component and system status. These supporting structures need to follow software/hardwareco-design to provide small and scalable overhead, while accommodating the functions of agents on the correspondinglevel. This paper presents the architectural design, functional simulation and implementationanalysis. The study demonstrates that the proposed structures facilitate the dynamic organization in caseof processor failures and incur small area overhead on many-core systems.

  • 190. Guang, Liang
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Adaptive Power Management for the On-Chip Communication Network2006In: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings, 2006, p. 649-656Conference paper (Refereed)
    Abstract [en]

    An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this region by adjusting frequency and voltage. For a deflective routing network we propose the design of a central controller for dynamic frequency and voltage scaling. Given history information including the load and frequency in the network, the controller adjusts the frequency and voltage such that the network operates just below the saturation point. We provide control mechanisms for continuous and discrete frequency ranges. With a discrete frequency range and taking into account voltage switching delays, we evaluate the control mechanism under stochastic, smoothly varying and very bursty traffic. Experiments demonstrate that adaptive control is very effective in minimizing power consumption at reasonable performance. Compared with a fixed high frequency network, the adaptively controlled network is significantly more power efficient. We compare it to fixed frequency networks, which are either too slow exhibiting unbounded delays, or are dimensioned for the worst case with very high frequency and are very power hungry.

  • 191. Guang, Liang
    et al.
    Kanth, R.
    Plosila, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hierarchical Monitoring in Smart House: Design Scalability, Dependability and Energy-Efficiency2011In: Proc. of the 3rd International Conference on Information Science and Engineering (ICISE2011) / [ed] Pan, Yi, 2011, p. 291-296Conference paper (Refereed)
    Abstract [en]

    Energy-efficient hierarchical monitoring is presented on smart house platforms. The rapid expansion of embedded systems requires scalable and portable design interfaces to tackle with the increasing complexity. Hierarchical monitoring is a scalable and generic approach for optimization and diagnostic operations in distributed embedded systems. The paper studies the design of hierarchical montioring on smart house platforms built upon the Zigbee standard of PANs (personal area networks). It presents the functional partition of hierarchical agents in a smart house, and gives a qualitative discussion of the design scalability and dependability, in particular compared to centralized monitoring. In addition, quantitative evaluation of the energy efficiency of monitoring communication in a smart house is performed using a PAN simulator with Zigbee routing configuration. We demonstrate that hierarchical monitoring is more energy efficient than centralized monitoring in various scenarios of a domestic environment.

  • 192. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Isoaho, Jouni
    Rantala, Pekka
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Interconnection alternatives for hierarchical monitoring communication in parallel SoCs2010In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 34, no 5, p. 118-128Article in journal (Refereed)
    Abstract [en]

    Interconnection architectures for hierarchical monitoring communication in parallel System-on-Chip (SoC) platforms are explored. Hierarchical agent monitoring design paradigm is an efficient and scalable approach for the design of parallel embedded systems. Between distributed agents on different levels, monitoring communication is required to exchange information, which forms a prioritized traffic class over data traffic. The paper explains the common monitoring operations in SoCs, and categorizes them into different types of functionality and various granularities. Requirements for on-chip interconnections to support the monitoring communication are outlined. Baseline architecture with best-effort service, time division multiple access (TDMA) and two types of physically separate interconnections are discussed and compared, both theoretically and quantitatively on a Network-on-Chip (NoC)-based platform. The simulation uses power estimation of 65 nm technology and NoC microbenchmarks as traffic traces. The evaluation points out the benefits and issues of each interconnection alternative. In particular, hierarchical monitoring networks are the most suitable alternative, which decouple the monitoring communication from data traffic, provide the highest energy efficiency with simple switching, and enable flexible reconfiguration to tradeoff power and performance.

  • 193. Guang, Liang
    et al.
    Nigussie, Ethiopia
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip2010In: Proceedings - IEEE International SOC Conference, SOCC 2010, 2010, p. 481-486Conference paper (Refereed)
    Abstract [en]

    System-level exploration of a novel Network-on-Chip (NoC) architecture with run-time communication bypassing is presented. Fine-grained DVFS (Dynamic Voltage and Frequency Scaling) is an effective power reduction technique. We propose run-time reconfigurable interconnect on each inter-router channel to minimize the latency and energy overhead. When two routers are running on the same frequency, FIFO-channel is bypassed by direct interconnect. Distributed algorithm is designed for per-core DVFS. Proper power delivery and clocking scheme are integrated. Simulation shows significant energy and latency saving.

  • 194. Guang, Liang
    et al.
    Yang, B.
    Plosila, J.
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hierarchical Agent Monitoring Design Platform - towards Self-aware and Adaptive Embedded Systems2011In: PECCS 2011 - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems, 2011, p. 573-581Conference paper (Refereed)
    Abstract [en]

    Hierarchical agent monitoring design platform(HAM) is presented as a generic design approach for the emerging self-aware and adaptive embedded systems. Such systems, with various existing proposals for different advanced features, call for a concrete, practical and portable design approach. HAM addresses this necessity by providing a scalable and generically applicable design platform. This paper elaborately describes the hierarchical agent monitoring architecture, with extensive reference to the state-of-the-art technology in embedded systems. Two case studies are exemplified to demonstrate the design process and benefits of HAM design platform. One is about hierarchical agent monitored Network-on-Chip with quantitative experiments of hierarchical energy management. The other one is a projectional study of applying HAM on smart house systems, focusing on the design for enhanced dependability.

  • 195. Halonen, E.
    et al.
    Viiru, T.
    Östman, K.
    Lopez Cabezas, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mantysalo, M.
    Oven sintering process optimization for inkjet-printed Ag Nanoparticle ink2013In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 3, no 2, p. 350-356Article in journal (Refereed)
    Abstract [en]

    This paper focuses on optimizing the oven sintering time and temperature for inkjet-printed silver nanoparticle ink on a polyimide substrate. Two basic aspects in fabricating conductor structures in printable electronics are conductivity and adhesion between the ink and the substrate material. Conductivity evolution during oven sintering is monitored with real-time resistance measurements at five different temperatures. Based on conductivity results, adhesion is evaluated at several time points at three temperatures. The higher the sintering temperature, the faster the structures reach their maximum conductivity values. The lowest conductor resistivity values are below 4 μΩcm. However, at each sintering temperature, it takes longer to reach the best adhesion values. In this paper, we aim to better understand oven sintering of silver nanoparticles and determine the best oven sintering conditions (temperature, time) for our particular ink-substrate combination. The results can be used to further define optimum sintering conditions for printed nanoparticle inks on polymer substrates.

  • 196.
    Hashmi, G. M.
    et al.
    Aalto Univ, Power Syst & High Voltage Engn Lab, Helsinki, Finland..
    Papazyan, R.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lehtonen, M.
    Aalto Univ, Power Syst & High Voltage Engn Lab, Helsinki, Finland..
    Comparing wave propagation characteristics of MV XLPE cable and covered-conductor overhead line using time domain refiectometry technique2007In: 2007 INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, IEEE , 2007, p. 350-+Conference paper (Refereed)
    Abstract [en]

    In this paper, the wave propagation characteristics of single-phase medium voltage (MV) cross-linked polyethylene (XLPE) cable are determined using Time Domain Reftectometry (TDR) measurement technique. TDR delivers the complex propagation constant (attenuation and phase constants) of lossy cable transmission line as a function of frequency. The frequency dependent propagation velocity is also determined from the TDR measurements through the parameters extraction procedure. The TDR measurement results for MV XLYE cable and coveredconductor (CC) overhead line are compared and it is proved that CC line has lower attenuation and higher propagation velocity than power cable. The measurement results can be used to localize the discontinuities in XLPE power cables and for PD detection to monitor falling trees on the MV CC overhead lines.

  • 197. Hashmi, G. M.
    et al.
    Papazyan, Ruslan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. ABB Power Technologies in Sofia, Bulgaria .
    Lehtonen, M.
    Determining wave propagation characteristics of MV XLPE power cable using time domain reflectometry technique2009In: ELECO 2009 - 6th International Conference on Electrical and Electronics Engineering, 2009, p. I159-I163Conference paper (Refereed)
    Abstract [en]

    In this paper, the wave propagation characteristics of single-phase medium voltage (MV) cross-linked polyethylene (XLPE) power cable are determined using Time Domain Reflectometry (TDR) measurement technique. TDR delivers the complex propagation constant (attenuation and phase constant) of lossy cable transmission line as a function of frequency. The frequency-dependent propagation velocity is also determined from the TDR measurements through the parameters extraction procedure. The measurement results can be used to localize the discontinuities as well as the design of communication through distribution power cables.

  • 198. Hashmi, Ghulam Murtaza
    et al.
    Papazyan, Ruslan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lehtonen, Matti
    Determining wave propagation characteristics of MV XLPE power cable using time domain reflectometry technique2011In: TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES, ISSN 1300-0632, Vol. 19, no 2, p. 207-219Article in journal (Refereed)
    Abstract [en]

    In this paper, the wave propagation characteristics of single-phase medium voltage (MV) cross-linked polyethylene (XLPE) power cable are determined using time domain reflectometry (TDR) measurement technique. TDR delivers the complex propagation constant (attenuation and phase constant) of lossy cable transmission line as a function of frequency. The frequency-dependent propagation velocity is also determined from the TDR measurements through the parameters extraction procedure. The calibration of the measuring system (MS) is carried-out to avoid the effect of multiple reflections on the accuracy of measurements. The results obtained from the measurements can be used to localize the discontinuities as well as the design of communication through distribution power cables.

  • 199. Hellberg, L.
    et al.
    Hemani, A.
    Isoaho, J.
    Jantsch, A.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mokhtari, M.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    System Oriented VLSI Curriculum at KTH1997In:  , 1997Conference paper (Refereed)
  • 200. Helmy, Amr
    et al.
    Pierre, Laurence
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Theorem Proving Techniques for Formal Verification of NoC Communications with Non-minimal Adaptive Routing2010In: Proceedings of the 13th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2010Conference paper (Refereed)
    Abstract [en]

    This paper focuses on the formal verification of communications in Networks on Chip. We describe how an enhanced version of the GeNoC proof methodology has been applied to the Nostrum NoC which encompasses various non-trivial features such as a deflective non-minimal routing algorithm. We demonstrate how the features of the Nostrum protocol layers can be captured by the current version of GeNoC that enables a step-by-step formalization of communication operations while taking various protocol details into consideration. We prove that packets arrive properly and that packets are never lost. Also, we prove the soundness of the Nostrum data link, network and transport layers

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