Change search
Refine search result
1234 151 - 189 of 189
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the 'Create feeds' function.
  • 151.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, D.
    Deterministic Worst-case Performance Analysis for Wireless Sensor Networks2008In: Proceedings of the International Wireless Communications and Mobile Computing Conference, 2008, p. 1081-1086Conference paper (Refereed)
    Abstract [en]

    Dimensioning wireless sensor networks requires formal methods to guarantee network performance and cost in any conditions. Based on network calculus, this paper presents a deterministic analysis method for evaluating the worst-case performance and buffer cost of sensor networks. To this end, we introduce three general traffic flow operators and derive their delay and buffer bounds. These operators are general because they can be used in combination to model any complex traffic flowing scenarios in sensor networks. Furthermore, our method integrates variable duty cycle to allow the sensor nodes to operate at lower rates thus saving power. Moreover, it incorporates traffic splitting mechanisms in order to balance network workload and nodes' buffers. To show how our method applies to real applications, we conduct a case study on a fresh food tracking application, which monitors the food freshness in realtime. The experimental results demonstrate that our method can be either used to perform network planning before deployment, or to conduct network reconfiguration after deployment.

  • 152.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    A Network-based System Architecture for Remote Medical Applications2007In: Proceedings of the Asia-Pacific Advanced Network Meeting, 2007Conference paper (Refereed)
    Abstract [en]

    Nowadays, the evolution of wireless communication and networktechnologies enables remote medical services to be availableeverywhere in the world. In this paper, a network-based systemarchitecture adopting wireless personal area network (WPAN)protocol IEEE 802.15.4/Zigbee standard and 3G communicationnetworks for remote medical applications is proposed. In theproposed system, the number and type of medical sensors arescalable depending on individual needs. This feature allows thesystem to be flexibly applied in several medical applications.Furthermore, a differentiated service using priority scheduling anddata compression is introduced. This scheme can not only reducetransmission delay for critical physiological signals and enhancebandwidth utilization at the same time, but also decrease powerconsumption of the hand-held personal server which uses batteryas the energy source.

  • 153.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor Networks2008In: International Journal of Software Engineering and Its Applications, ISSN 1738-9984, Vol. 2, no 3Article in journal (Refereed)
    Abstract [en]

    For many applications of sensor networks, it is essential to ensure that messages aretransmitted to their destinations within delay bounds and the buffer size of each sensor nodeis as small as possible. In this paper, we firstly introduce the system model of a mesh sensornetwork. Based on this system model, the expressions for deriving the delay bound and bufferrequirement bound are presented using network calculus theory. In order to balance trafficload and improve resource utilization, three traffic splitting mechanisms are proposed. Andthe two bounds are derived in these traffic splitting mechanisms. To show how our methodapplies to real applications, we conduct a case study on a fresh food tracking application,which monitors the food freshness status in real-time during transportation. The numericalresults show that the delay bound and buffer requirement bound are reduced while applyingtraffic splitting mechanisms. Thus the performance of the whole sensor network is improvedwith less cost.

  • 154.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Traffic splitting with network calculus for mesh sensor networks2007In: Proceedings of Future Generation Communication and Networking, FGCN 2007, IEEE Computer Society, 2007, p. 371-376Conference paper (Refereed)
    Abstract [en]

    In many applications of sensor networks, it is essential to ensure that messages are transmitted to their destinations as early as possible and the buffer size of each sensor node is as small as possible. In this paper, we firstly propose a mesh sensor network system model. Based on this system model, the expressions for deriving the delay bound and buffer requirement bound are presented using network calculus. In order to balance traffic load and improve resource utilization, three traffic splitting mechanisms are proposed The numerical results show that the delay bound and buffer requirement bound are lowered while applying those traffic splitting mechanisms. And thus the performance of the whole sensor network is improved.

  • 155.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks2009In: 2009 IEEE VEHICULAR TECHNOLOGY CONFERENCE, 2009, p. 38-42Conference paper (Refereed)
    Abstract [en]

    Retransmission has been adopted as one of the most popular schemes for improving transmission reliability in wireless sensor networks. Many previous works have been done on reliable transmission issues in experimental ways, however, there still lack of analytical techniques to evaluate these solutions. Based on the traffic model, service model and energy model, we propose an analytical method to analyze the delay and energy metrics of two categories of retransmission schemes: hop-by-hop retransmission (HBH) and end-to-end retransmission (ETE). With the experiment results, the maximum packet transfer delay and energy efficiency of these two scheme are compared in several scenarios. Moreover, the analytical results of transfer delay are validated through simulations. Our experiments demonstrate that HBH has less energy consumption at the cost of lager transfer delay compared with ETE. With the same target success probability, ETE is superior on the delay metric for low bit-error-rate (BER) cases, while HBH is superior for high BER cases.

  • 156.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhou, Dian
    Department of Microelectronics, Fudan Universiy.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling and Analysis of Rayleigh Fading Channels using Stochastic Network Calculus2011Conference paper (Refereed)
    Abstract [en]

    Deterministic network calculus (DNC) is not suitable for deriving performance guarantees for wireless networks due to their inherently random behaviors. In this paper, we develop a method for Quality of Service (QoS) analysis of wireless channels subject to Rayleigh fading based on stochastic network calculus. We provide closed-form stochastic service curve for the Rayleigh fading channel. With this service curve, we derive stochastic delay and backlog bounds. Simulation results verify that the bounds are reasonably tight. Moreover, through numerical experiments, we show the method is not only capable of deriving stochastic performance bounds, but also can provide guidelines for designing transmission strategies in wireless networks.

  • 157.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhou, Dian
    Department of Microelectronics, Fudan Universiy.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks2012In: International Journal of Distributed Sensor Networks, ISSN 1550-1329, p. 232937-Article in journal (Refereed)
    Abstract [en]

    Performance analysis is crucial for designing predictable and cost-efficient sensor networks. Based on the network calculus theory, we propose a flow-based traffic splitting strategy and its analytical method for worst-case performance analysis on cluster-mesh sensor networks. The traffic splitting strategy can be used to alleviate the problem of uneven network traffic load. The analytical method is able to derive close-form formulas for the worst-case performance in terms of the end-to-end least upper delay bounds for individual flows, the least upper backlog bounds, and power consumptions for individual nodes. Numerical results and simulations are conducted to show benefits of the splitting strategy as well as validate the analytical method. The numerical results show that the splitting strategy enables much better balance on network traffic load and power consumption. Moreover, the simulation results verify that the theoretic bounds are fairly tight.

  • 158.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhou, Dian
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Stochastic Coverage in Event-Driven Sensor Networks2011In: 2011 IEEE 22nd International Symposium On Personal Indoor And Mobile Radio Communications (PIMRC), New York: IEEE , 2011, p. 915-919Conference paper (Refereed)
    Abstract [en]

    One of the primary tasks of sensor networks is to detect events in a field of interest (FoI). To quantify how well events are detected in such networks, coverage of events is a fundamental problem to be studied. However, traditional studies mostly focus on analyzing the coverage of the FoI, which is usually called are a coverage. In this paper, we propose an analytic method to evaluate the performance of event coverage in sensor networks with randomly deployed sensor nodes and stochastic event occurrences. We provide formulas to calculate the probabilities of event coverage and event missing. The numerical results show how these two probabilities change with the sensor and event densities. Moreover, simulations are conducted to validate the analytic method. This method can provide guidelines for determining the amount of sensor nodes to achieve a certain level of coverage in event-driven sensor networks.

  • 159. Su, Hai
    et al.
    Qiu, Meikang
    Chen, Huimin
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Qin, Xiao
    Jamming-Resilient Multi-Radio Multi-Channel Multihop Wireless Network for Smart Grid2011In: In Proceedings of the 7th ACM Annual Cyber Security and Information Intelligence Research Workshop (CSIIR’11), 2011Conference paper (Refereed)
  • 160. Tong, L.
    et al.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. Tianjin University of Technology, China.
    Zhang, H.
    Exploration of slot allocation for on-chip TDM virtual circuits2009In: Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, IEEE Computer Society, 2009, p. 127-132Conference paper (Refereed)
    Abstract [en]

    Time-Division-Multiplexing (TDM) Virtual Circuit (VC) has been proposed to guarantee the Quality-of-Service requirements in communication for Network-on-Chip. In this paper, we explore the design space of slot allocation for configuring TDM VCs. Specifically, we investigate different slot assignment schemes, namely, distributed, random and consecutive schemes, which have significant impact on the configurability. We also propose to construct disjoint connected VC sets to effectively reduce the search space. We have realized and integrated them into our VC configuration flow. Our experimental results suggest that the optimal slot allocation cycle equals to the ratio of the link bandwidth to the maximal VC bandwidth, and the distributed slot assignment scheme performs better than the random and consecutive schemes.

  • 161. Wang, Jian
    et al.
    Chen, Zhe
    Guo, Jinhong
    Li, Yubai
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs2017In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 3, p. 930-937Article in journal (Refereed)
    Abstract [en]

    The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive silicon regions called dark silicon, which significantly impacts the system performance. In this paper, we propose a thread-to-core mapping method for dark-silicon-constrainedCMPs to address their thermal issue. We first propose a thermal predictionmodel to forecast CMP temperature after the CMP executes a forthcoming application. Then, we develop an ant colony optimization-based algorithm to conduct the thread-to- core mapping process, such that the CMP peak temperature is minimized and, consequently, the probability of triggering CMP dynamic thermal management is decreased. Finally, we evaluate our method and compare it with the baseline (a standard Linux scheduler) and other existing methods (NoC-Sprinting, DaSiM mapping, and TP mapping). The simulation results show that our method gains good thermal profile and computational performance, and performs well with chip scaling. Specifically, it eliminates all thermal emergency time, outperforming all other methods, and gains million instructions per second improvement up to 12.9% against the baseline.

  • 162.
    Wang, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. Univ Elect Sci & Technol China, China.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Li, Yubai
    A New CDMA Encoding/Decoding Method for on-Chip Communication Network2016In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 24, no 4, p. 1607-1611Article in journal (Refereed)
    Abstract [en]

    As a high performance on-chip communication method, the code division multiple access (CDMA) technique has recently been applied to networks on chip (NoCs). We propose a new standard-basis-based encoding/decoding method to leverage the performance and cost of CDMA NoCs in area, power assumption, and network throughput. In the transmitter module, source data from different senders are separately encoded with an orthogonal code of a standard basis and these coded data are mixed together by an XOR operation. Then, the sums of data can be transmitted to their destinations through the onchip communication infrastructure. In the receiver module, a sequence of chips is retrieved by taking an AND operation between the sums of data and the corresponding orthogonal code. After a simple accumulation of these chips, original data can be reconstructed. We implement our encoding/decoding method and apply it to a CDMA NoC with a star topology. Compared with the state-of-the-art Walsh-code-based (WB) encoding/decoding technique, our method achieves up to 67.46% power saving and 81.24% area saving together with decrease of 30%-50% encoding/decoding latency. Moreover, the CDMA NoC with different sizes applying our encoding/decoding method gains power saving, area saving, and maximal throughput improvement up to 20.25%, 22.91%, and 103.26%, respectively, than the WB CDMA NoC.

  • 163. Wang, Jian
    et al.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Li, Yubai
    Fu, Yusheng
    Guo, Jinhong
    A High-Level Thermal Model-Based Task Mapping for CMPs in Dark-Silicon Era2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 9, p. 3406-3412Article in journal (Refereed)
    Abstract [en]

    The chip multiprocessor (CMP) thermal issue impacting the system reliability and cooling cost has become a limiting factor for chip scaling and attracted growing attentions in the dark-silicon era. We propose a thermal-aware thread-to-core mapping method for CMPs under the dark-silicon constraint. We first propose a high-level spatial-temporal information-based thermal model to capture the relationship between the mapping result and the system thermal distribution. Then, we develop a thermal-aware mapping algorithm, which can automatically assign threads to proper cores based on the proposed model. Finally, we evaluate our method through simulations. Compared with three other mapping methods, namely, random, network-on-chip (NoC)-sprinting and round-robin, our thermal-priority design decreases the peak temperature by up to 4.31 K while showing good communication performance (34.7% of improvement against random and 50.3% against NoC sprinting, and only 6.3% of degradation against round robin); and our latency-priority design achieves the best communication performance with an improvement up to 62.6% and a satisfactory thermal profile.

  • 164. Wang, Yu
    et al.
    Zhou, Kai
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Yang, Huazhong
    Dynamic TDM Virtual Circuit Implementation for NoCs2008In: Proceedings of Asia-Pacific Conference on Circuits and Systems (APCCAS’08), 2008, p. 1533-1536Conference paper (Refereed)
    Abstract [en]

    Quality-of-Service (QoS) communication has been a key issue since the birth of Network-on-Chip (NoC). Time Division Multiplexing (TDM) techniques are well-recognized to be capable of providing guarantees in latency and bandwidth. However, current TDM VC proposals assume synchronous operation and use a costly slot allocation table to statically allocate bandwidth. In this paper, we propose a novel TDM VC implementation that releases the strict synchronous operation assumption and computes slot allocation fully dynamically. To promise VC contention-free, we use the Logical Network theory to guide the slot computation. The slot allocation information is computed once and propagated downstream. This enables adaptive VC configuration and also allows us to use smaller allocation tables in routers. We describe our dynamic TDM VC implementation mechanism, and detail the router design to support this mechanism.

  • 165.
    Weldezion, Awet Yemane
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Grange, Matt
    Pamunuwa, Dinesh
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Weerasekera, Roshan
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Scalability of Network-on-Chip Communication Architecture for 3-D Meshes2009In: 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, NEW YORK: IEEE , 2009, p. 114-123Conference paper (Refereed)
    Abstract [en]

    Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologiesfor 3-D Network-on-Chips (NoC) using Through-Silicon-Was (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.

  • 166.
    Weldezion, Awet Yemane
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Weerasekera, Roshan
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture2009In: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, NEW YORK: IEEE , 2009, p. 42-48Conference paper (Refereed)
    Abstract [en]

    Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid state drives - (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3-D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. Simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns.

  • 167. Wolf, Pieter van der
    et al.
    Henriksson, Tomas
    Bruce, Alistair
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Millberg, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Clouard, Alain
    Definition of Device Level Interface with QoS: Draft Specification2007Report (Other academic)
    Abstract [en]

    The extensions to standard IP communication interfaces proposed in SPRINT WP3document D3.1 are defined.

    Flow identification signals are added to the DLI signal level interface so transactionscan indicate the services they require. These services are specified as Contracts thatdefine the flow characteristics required for correct operation. These characteristics arethe main input to an analysis method to validate that a SoC design achieves its performance targets.

    DLI-Guard units are defined that enforce Contracts by regulating an IP module’s identified flows. Monitoring of flow characteristics, such as latency, is also optionally provided. A configuration API for DLI-Guards is outlined together with example code toillustrate its use.

    This specification is successfully applied to AMBA AXI, the prime example DLI

  • 168. Xiong, Q.
    et al.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Wu, F.
    Xie, C.
    Real-time analysis for wormhole NoC: Revisited and revised2016In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Association for Computing Machinery (ACM), 2016, p. 75-80Conference paper (Refereed)
    Abstract [en]

    The network delay upper-bound analysis problem is of fundamental importance to real-time applications in Network-on-Chip (NoC). In the paper, we revisit a state-of-the-art analysis model for real-time communication in wormhole NoC with priority-based preemptive arbitration and show that the model may provide pessimistic or even incorrect network delay upper-bound. We then propose a revised analysis model to correct the flaws in the previous model by further classifying indirect interference as upstream and downstream indirect interferences according to the relative positions of traffic flows and taking buffer influence into consideration. Simulated evaluations show that our model provides tighter and correct network delay upper-bound compared with the state-of-the-art model.

  • 169. Xiong, Q.
    et al.
    Wu, F.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Xie, C.
    Extending Real-Time Analysis for Wormhole NoCs2017In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 66, no 9, p. 1532-1546, article id 7884964Article in journal (Refereed)
    Abstract [en]

    The delay upper-bound analysis problem is of fundamental importance to real-Time applications in Network-on-Chips (NoCs). In the paper, we revisit two state-of-The-Art analysis models for real-Time communication in wormhole NoCs with priority-based preemptive arbitration and show that the models only support specific router architectures with large buffer sizes. We then propose an extended analysis model to estimate delay upper-bounds for all router architectures and buffer sizes by identifying and analyzing the differences between upstream and downstream indirect interferences according to the relative positions of traffic flows and taking the buffer influence into consideration. Simulated evaluations show that our model supports one more router architecture and applies to small buffer sizes compared to the previous models.

  • 170.
    Yao, Yuan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    DVFS for NoCs in CMPs: A thread voting approach2016In: 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), Institute of Electrical and Electronics Engineers (IEEE), 2016, Vol. 2016, p. 309-320, article id 7446074Conference paper (Refereed)
    Abstract [en]

    As the core count grows rapidly, dynamic voltage/frequency scaling (DVFS) in networks-on-chip (NoCs) becomes critical in optimizing energy efficacy in chip multiprocessors (CMPs). Previously proposed techniques often exploit inherent network-level metrics to do so. However, such network metrics may contradictorily reflect application's performance need, leading to power over/under provisioning. We propose a novel on-chip DVFS technique for NoCs that is able to adjust per-region V/F level according to voted V/F levels of communicating threads. Each region is composed of a few adjacent routers sharing the same V/F level. With a voting-based approach, threads seek to influence the DVFS decisions independently by voting for a preferred V/F level that best suits their own performance interest according to their runtime profiled message generation rate and data sharing characteristics. The vote expressed in a few bits is then carried in the packet header and spread to the routers on the packet route. The final DVFS decision is made democratically by a region DVFS controller based on the majority election result of collected votes from all active threads. To achieve scalable V/F adjustment, each region works independently, and the voting-based V/F tuning forms a distributed decision making process. We evaluate our technique with detailed simulations of a 64-core CMP running a variety of multi-threaded PARSEC benchmarks. Compared with a network without DVFS and a network metric (router buffer occupancy) based approach, experimental results show that our voting based DVFS mechanism improves the network energy efficacy measured in MPPJ (million packets per joule) by about 17.9% and 9.7% on average, respectively, and the system energy efficacy measured in MIPJ (million instructions per joule) by about 26.3% and 17.1% on average, respectively.

  • 171.
    Yao, Yuan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems2014In: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE , 2014, p. 343-348Conference paper (Refereed)
    Abstract [en]

    Flow regulation is a traffic shaping technique, which can be used to improve communication performance with better utilization of network resources in chip multi-processors (CMPs). This paper presents fuzzy flow regulation. Being different from the static flow regulation policy, our system makes regulation decisions fully dynamically according to traffic dynamism and the state of interconnection network. The central idea is to use fuzzy logic to mimic the behavior of an expert that can recognize the network status and then intelligently control the admission of input flows. As the experiment results show, the maximum improvement in average delay reaches 53.0% against static regulation and 37.4% against no regulation. The maximum improvement in average throughput reaches 37.5% against static regulation and 23.8% against no regulation.

  • 172.
    Yao, Yuan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Memory-Access Aware DVFS for Network-on-Chip in CMPs2016In: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE conference proceedings, 2016, p. 1433-1436Conference paper (Refereed)
    Abstract [en]

    We present a new DVFS technique for network-on-chip (NoC) that adjusts the voltage/frequency scales of routers according to memory-access characteristics of application running on the CMP. The memory characteristics are periodically profiled, reflecting both resource-access density in the network and memory-access criticality for application performance. The network conducts per-router voltage/frequency tuning using the memory-access density information while it performs priority-based switch allocation to speed up critical packets and avoid starvation using the memory-criticality information. Compared to a latest per-router DVFS approach, benchmark experiments demonstrate that our memory-access characteristics aware DVFS technique achieves not only better power saving, energy-delay product, but also enhanced network and application performance.

  • 173.
    Yao, Yuan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs2016In: Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016, IEEE, 2016, p. 279-290Conference paper (Refereed)
    Abstract [en]

    With the degree of parallelism increasing, performance of multi-threaded shared variable applications is not only limited by serialized critical section execution, but also by the serialized competition overhead for threads to get access to critical section. As the number of concurrent threads grows, such competition overhead may exceed the time spent in critical section itself, and become the dominating factor limiting the performance of parallel applications. In modern operating systems, queue spinlock, which comprises a low-overhead spinning phase and a high-overhead sleeping phase, is often used to lock critical sections. In the paper, we show that this advanced locking solution may create very high competition overhead for multithreaded applications executing in NoC-based CMPs. Then we propose a software-hardware cooperative mechanism that can opportunistically maximize the chance that a thread wins the critical section access in the low-overhead spinning phase, thereby reducing the competition overhead. At the OS primitives level, we monitor the remaining times of retry (RTR) in a thread's spinning phase, which reflects in how long the thread must enter into the high-overhead sleep mode. At the hardware level, we integrate the RTR information into the packets of locking requests, and let the NoC prioritize locking request packets according to the RTR information. The principle is that the smaller RTR a locking request packet carries, the higher priority it gets and thus quicker delivery. We evaluate our opportunistic competition overhead reduction technique with cycle-accurate full-system simulations in GEM5 using PARSEC (11 programs) and SPEC OMP2012 (14 programs) benchmarks. Compared to the original queue spinlock implementation, experimental results show that our method can effectively increase the opportunity of threads entering the critical section in low-overhead spinning phase, reducing the competition overhead averagely by 39.9% (maximally by 61.8%) and accelerating the execution of the Region-of-Interest averagely by 14.4% (maximally by 24.5%) across all 25 benchmark programs.

  • 174. Yin, Alexander Wei
    et al.
    Liljeberg, Pasi
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Monitoring Agent Based Autonomous Reconfigurable Network-on-Chip2008In: In DAC08 Workshop Digest in Diagnostic Services in Network-on-Chips, 2008Conference paper (Refereed)
    Abstract [en]

    Emerging technologies such as invasive electronics andnano-scale Network-on-Chip systems frequently requireultra-low power and fault tolerance. Implementing thiskind of systems requires the use of a robust monitoringstructure and autonomous self-adjustment. In this paperdifferent distributed system monitoring agentarchitectures are analyzed. The monitored informationcan be used to determine faulty components and to adjustsystem operation points towards minimal energy.

  • 175.
    Zhang, Yuang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, L.
    Jantsch, A.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Gao, M.
    Fu, Y.
    Pan, H.
    Exploring stacked main memory architecture for 3D GPGPUs2015In: Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015, IEEE conference proceedings, 2015Conference paper (Refereed)
    Abstract [en]

    The tremendous number of threads on general purpose graphic processing units (GPGPUs) poses significant challenges on memory architecture design. 3D stacked main memory architecture atop GPGPU is a potential approach to provide high data communication bandwidth and low access latency to meet the requirement of GPGPUs. In this paper, we explore the performance of 3D GPGPUs with stacked main memory. The experimental results show that the 3D stacked GPGPU can provide up to 124.1% and on average 55.8% performance improvement compared to a 2D GPGPU scheme.

  • 176.
    Zhang, Yuang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. Nanjing University, China.
    Li, L.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Fu, Y.
    Gao, M.
    Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips2014In: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE , 2014, p. 1961-1964Conference paper (Refereed)
    Abstract [en]

    Last level cache (LLC) is crucial for the performance of chip multiprocessors (CMPs), while power is a significant design concern for 3D CMPs. In this paper, we focus on the SRAM-based Non-Uniform Cache Architecture (NUCA) for 3D Multi-core Network-on-Chip (McNoC) systems. A tightly mixed SRAM NUCA for 3D mesh NoC is presented and analyzed. We evaluate the performance and network power with benchmarks based on a full system simulation framework. Experiment results on 16-core 3D NoC systems show that the tightly mixed NUCA could provide up to 31.71% and on average 5.95% performance improvement compared to a base 3D NUCA scheme. The tightly mixed 3D NUCA NoC can reduce network power consumption in 1.07%-15.74% and 9.64% on average compared to a baseline 3D NoCs. Our analysis and experimental results provide a guideline to design efficient 3D NoCs with stacking NUCA.

  • 177.
    Zhang, Yuang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. Institute of VLSI Design, Key Laboratory of Advanced Photonic and Electronic Materials, Nanjing University, China .
    Li, Li
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Gao, Minglun
    Pan, Hongbing
    Han, Feng
    A survey of memory architecture for 3D chip multi-processors2014In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 38, no 5, p. 415-430Article in journal (Refereed)
    Abstract [en]

    3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and the parallelism of CMPs, which are emerging as active research topics in VLSI and multi-core computer architecture communities. One significant potentiality of 3D CMPs is to exploit the diversity of integration processes and high volume of vertical TSV bandwidth to mitigate the well-known "Memory Wall" problem. Meanwhile, the 3D integration techniques are under the severe thermal, manufacture yield and cost constraints. Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs. The micro-architectures of memories can be designed in the 3D integrated circuit context and integrated into 3D CMPs. This paper surveys the design of memory architectures for 3D CMPs. We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs. The representative works are reviewed and the remaining opportunities and challenges are discussed to guide the future research in this emerging area.

  • 178.
    Zhang, Yuang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Li, Li
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Gao, Minglun
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Towards Hierarchical Cluster based Cache Coherence for Large-Scale Network-on-Chip2009In: DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, p. 119-122Conference paper (Refereed)
    Abstract [en]

    We introduce a novel hierarchical cluster based cache coherence scheme for large-scale NoC based distributed memory architectures. We describe the hierarchical memory organization. We show analytically that the proposed scheme has better performance than traditional counterparts both in memory overhead and communication cost.

  • 179.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yan, Xiaolang
    Design and Optimization of a CDMA-based Multi-Reader Passive UHF RFID System for Dense Scenarios2012In: IEICE transactions on communications, ISSN 0916-8516, E-ISSN 1745-1345, Vol. E95B, no 1, p. 206-216Article in journal (Refereed)
    Abstract [en]

    In dense passive radio frequency identification (RFID) systems, code division multiple access (CDMA) techniques can be used to alleviate severe collisions and thus enhance the system performance. However, conventional CDMA techniques are challenging to implement, especially for passive tags due to cost and power constraints. In this paper, we design a CDMA-based multi-reader passive ultra high frequency (UHF) RFID system in which a reader detects only the strongest tag signal and a tag uses Gold codes only on the preamble and the data bits of RN16 without increasing its clock frequency. We present a new communication procedure based on dynamic framed slotted ALOHA (DFSA). In order to optimize the system, we theoretically analyze the system performance in terms of slot capacity and identification rate, and formally show how the code length and the number of readers affect the identification rate. Furthermore, we propose an effective method for tag estimation and frame size adjustment, and validate it via simulations. Through an example, we demonstrate how the analysis-based technique can be used to optimize the system configurations with respect to the number of readers and the number and length of Gold codes.

  • 180.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Yan, Xiaolang
    Institute of VLSI Design, Zhejiang University, Hangzhou, China.
    Zheng, Li-Rong
    A high performance multi-reader passive RFID system for Internet-of-ThingsIn: IEEE Transactions on Wireless Communications, ISSN 1536-1276, E-ISSN 1558-2248Article in journal (Other academic)
  • 181.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yan, Xiaolang
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things: concept and analysis2012In: International Journal of Communication Systems, ISSN 1074-5351, E-ISSN 1099-1131, Vol. 25, no 9, p. 1103-1121Article in journal (Refereed)
    Abstract [en]

    Radio frequency identification (RFID) is a compelling technology for Internet of Things (IoT). Ultra-wideband (UWB) technology is one promising wireless technique for future RFID, especially for high-throughput sensing applications. On-off keying UWB RFID system provides high pulse rate but suffers severe collisions that limit the system throughput. This paper proposes to utilize low pulse rate code division multiple access/pulse position modulation UWB in the tag-to-reader link to provide multiple tag access capability and build a high-throughput RFID system for IoT. We analyze asynchronous matched filter receiver and decorrelating receiver for multi-tag detection and design an effective medium access control scheme to optimize the network throughput. We propose an effective dynamic frame size adjustment algorithm on the basis of theoretical analysis and determine the preferable length of Gold codes. With a similar data rate, the throughput of the proposed system using the decorrelating receiver is 8.6 times higher than that of the electronic product code class 1 generation 2 system. Only using 1/10 pulse rate and 1/15 data rate, the proposed system outperforms the on-off keying UWB RFID system 1.4 times in terms of throughput.

  • 182.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Yan, Xiaolang
    Institute of VLSI Design, Zhejiang University, Hangzhou, China.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    COSMO: CO-simulation with MATLAB and OMNeT++ for indoor wireless networks2010In: 2010 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE GLOBECOM 2010, 2010Conference paper (Refereed)
    Abstract [en]

    Simulations are widely used to design and evaluate new protocols and applications of indoor wireless networks. However, the available network simulation tools face the challenges of providing accurate indoor channel models, three-dimensional (3-D) models, model portability, and effective validation. In order to overcome these challenges, this paper presents a new CO-Simulation framework based on MATLAB and OMNeT++ (COSMO) to rapidly build credible simulations for indoor wireless networks. A hierarchical ad hoc passive RFID network for indoor tag locating is described as a case study, demonstrating the significance and efficiency of COSMO compared with other network simulators. COSMO surpasses other network simulators in terms of workload and validity.

  • 183.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Pang, Zhibo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yan, Xiaolang
    Institute of VLSI Design, Zhejiang University, Hangzhou, China.
    A low delay multiple reader passive RFID system using orthogonal TH-PPM IR-UWB2010In: Proceedings - International Conference on Computer Communications and Networks, ICCCN, Zurich, 2010Conference paper (Refereed)
    Abstract [en]

    Current passive RFID systems face the challenges to locate mobile objects in real time in indoor environments, including the realization of low delay as well as effective cooperation among readers and accurate ranging ability in the physical layer. In order to overcome these challenges, this paper presents a low delay multi-reader passive RFID system using ultra high frequency (UHF) radio as the forward link from readers to tags and orthogonal time hopping pulse-position modulation (TH-PPM) impulse ultra-wideband radio (IR-UWB) over the dynamic framed slotted ALOHA algorithm as the backward link from tags to readers. The asymmetric radio links overlap parts of the forward and backward transmission and avoid reader-tag collisions. Readers cooperate via network synchronization by a server and a contention-based update strategy to acknowledge tags. An optimal system configured with 4 readers using 16 orthogonal TH sequences is suggested and operates 3 times faster than the theoretical potential of EPC Class-1 Generation-2 protocol with the listen-before-talk scheme. 

  • 184.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Saakian, Vardan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Yan, Xiaolang
    Institute of VLSI Design, Zhejiang University.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Item-Level Indoor Localization With Passive UHF RFID Based on Tag Interaction Analysis2013In: IEEE transactions on industrial electronics (1982. Print), ISSN 0278-0046, E-ISSN 1557-9948, Vol. 61, no 4, p. 2122-2135Article in journal (Refereed)
    Abstract [en]

    Radio-frequency identification (RFID) with a received signal strength indicator (RSSI) is a low-cost and low-complexity approach for item-level indoor localization. Although RSSI-based algorithms suffer from multipath effect and other environmental factors, reference tags and RSSI changes can be utilized to further improve the localization accuracy. However, the current algorithms lack deep analysis of the influence of tag interaction on localization accuracy and faces the challenge of simultaneously locating multiple close targets. In this paper, we propose an analysis method about how tag interaction affects a tag antenna radiation pattern and an RSSI change. The tag interaction analysis guides us to improve the design of RSSI-based localization algorithms. We take the k-nearest neighbor (k-NN) algorithm and the Simplex algorithm as two examples. The experimental results show that the revised k-NN and the revised Simplex algorithms are robust to different numbers, spacing, and materials of target objects, and they are superior to other RFID localization schemes, considering cost, capability of simultaneous localization of multiple targets, and location estimation errors.

  • 185.
    Zhao, Xueqian
    et al.
    KTH. Natl Univ Def Technol, Peoples R China.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics.
    A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in Simulink2017In: ACM Transactions on Modeling and Computer Simulation, ISSN 1049-3301, E-ISSN 1558-1195, Vol. 27, no 3, article id 16Article in journal (Refereed)
    Abstract [en]

    The eXecutable Micro-Architectural Specification (xMAS) language developed in recent years finds an effective way to model on-chip communication fabrics and enables performance-bound analysis with network calculus at the micro-architectural level. For network-on-Chip (NoC) performance analysis, model validation is essential to ensure correctness and accuracy. In order to facilitate the xMAS modeling and corresponding analysis validation, this work presents a unified platform based on xMAS in Simulink. The platform provides a friendly graphical user interface for xMAS modeling and parameter setup by taking advantages of the Simulink modeling environment. The regulator and latency-rate sever are added to the xMAS primitive set to support typical flow and service behaviors. Hierarchical model build-up and Verilog-HDL code generation are essentially supported to manage complex models and to conduct cycle-accurate bit-accurate simulations. Based on the generated simulation models of xMAS, this tool is applied to evaluate the tightness of analytical delay bound results. We demonstrate the application as well as the work flow of the xMAS tool through a two-agent communication example and an all-to-one communication example with a tree topology.

  • 186.
    Zhao, Xueqian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Backlog bound analysis for virtual-channel routers2015In: 2015 IEEE Computer Society Annual Symposium on VLSI, Institute of Electrical and Electronics Engineers (IEEE), 2015, Vol. 07, p. 422-427Conference paper (Refereed)
    Abstract [en]

    Backlog bound analysis is crucial for predicting buffer sizing boundary in on-chip virtual-channel routers. However, the complicated resource contention among traffic flows makes the analysis difficult. Because conventional simulation-based approaches are generally incapable of investigating the worst-case scenarios for the backlog bounds, we propose a formal analysis technique. We identify basic buffer use scenarios and propose corresponding analysis models to formally deduce per-buffer backlog bound using network calculus. A topology independent analysis technique is developed to convey the per-buffer backlog bound analysis step by step. We further develop an algorithm to automate the analysis procedure with polynomial complexity. A case study shows how to apply the technique and the analytical bounds are tight.

  • 187.
    Zhao, Xueqian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Empowering study of delay bound tightness with simulated annealing2014In: Proceedings -Design, Automation and Test in Europe, DATE, 2014Conference paper (Refereed)
    Abstract [en]

    Studying the delay bound tightness typically takes a practical approach by comparing simulated results against analytic results. However, this is often a manual process whereas many simulation parameters have to be configured before the simulations run. This is a tedious and time-consuming process. We propose a technique to automate this process by using a simulated annealing approach. We formulate the problem as an online optimization problem, and embed a simulated annealing algorithm in the simulation environment to guide the search of configuration parameters which give good tightness results. This is a fully automated procedure and thus provide a promising path to automatic design space exploration in similar contexts. Experiment results of an all-to-one communication network with large searching space and complicated constraints illustrate the effectiveness of our method.

  • 188.
    Zhao, Xueqian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip2015In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 34, no 6, p. 986-999, article id 7038204Article in journal (Refereed)
    Abstract [en]

    Studying the tightness of analytical delay and backlog bounds is critical for network-on-chip designs, since formal analysis predicts the boundary of communication delay and buffer dimensioning. However, this evaluation process is often a tedious, time-consuming, and manual simulation process whereas many simulation parameters have to be configured before the simulations run. We formulate the tightness evaluation as constrained optimization problems for delay bound and backlog bounds, respectively. The well-defined problems enable a fully automated configuration searching process, which can be guided by a heuristic algorithm with cycle-accurate simulations integrated. This is a fully automated procedure and thus provides a promising path to automatic design space exploration in similar contexts. Experimental results over various topologies and traffic patterns indicate that our method is effective in finding the configuration for best tightness up to 98%, even when up to 50 parameters are configured in a multidimensional discrete search space under complex constraints.

  • 189.
    Zhao, Xueqian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Per-flow delay bound analysis based on a formalized microarchitectural model2013In: 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013, IEEE , 2013, p. 6558411-Conference paper (Refereed)
    Abstract [en]

    System design starting from high level models can facilitate formal verification of system properties, such as safety and deadlock freedom. Yet, analyzing their QoS property, in our context, per-flow delay bound, is an open challenge. Based on xMAS (eXecutable Micro-Architectural Specification), a formal framework modeling communication fabrics, we present a QoS analysis procedure using network calculus. Given network and flow knowledge, we first create a well-defined xMAS model for a specific application on a concrete on-chip network. Then the specific xMAS model can be mapped to its network calculus analysis model for which existing QoS analysis techniques can be applied to compute end-to-end delay bound per flow. We give an example to show the step-by-step analysis procedure and discuss the tightness of the results.

1234 151 - 189 of 189
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf