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  • 151.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors2019In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 212, p. 13-20Article in journal (Refereed)
    Abstract [en]

    Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.

  • 152.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Legallais, Maxime
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Mouis, Mireille
    Pignot-Paintrand, Isabelle
    Stambouli, Valérie
    Ternon, Céline
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment2019In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 18Article in journal (Refereed)
  • 153.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Legallais, Maxime
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mouis, Mireille
    Stambouli, Valerie
    Ternon, Celine
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication and characterization of high-K dielectric integrated silicon nanowire sensor for DNA sensing application2016In: BIOSENSING AND NANOMEDICINE IX, SPIE - International Society for Optical Engineering, 2016, article id UNSP 99300QConference paper (Refereed)
  • 154.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Pixel-based biosensor for enhanced control: silicon nanowires monolithically integrated with field-effect transistors in fully depleted silicon on insulator technology2019In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 22, article id 225502Article in journal (Refereed)
    Abstract [en]

    Silicon nanowires (SiNWs) are a widely used technology for sensing applications. Complementary metal-oxide-semiconductor (CMOS) integration of SiNWs advances lab-on-chip (LOC) technology and offers opportunities for read-out circuit integration, selective and multiplexed detection. In this work, we propose novel scalable pixel-based biosensors exploiting the integration of SiNWs with CMOS in fully-depleted silicon-on-insulator technology. A detailed description of the wafer-scale fabrication of SiNW pixels using the CMOS compatible sidewall-transfer-lithography as an alternative to widely investigated time inefficient e-beam lithography is presented. Each 60 nm wide SiNWs sensor is monolithically connected to a control transistor and novel on-chip fluid-gate forming an individual pixel that can be operated in two modes: biasing transistor frontgate (V-G) or substrate backgate (V-BG). We also present the first electrical results of single N and P-type SiNW pixels. In frontgate mode, N and P-type SiNW pixels exhibit subthreshold slope (SS) approximate to 70-80 mV/dec and I-on/I-off approximate to 10(5). The N-type and P-type pixels have an average threshold voltage, Vth of -1.7 V and 0.85 V respectively. In the backgate mode, N and P-type SiNW pixels exhibit SS approximate to 100-150 mV/dec and I-on/I-off approximate to 10(6). The N and P-type pixels have an average V-th of 5 V and -2.5 V respectively. Further, the influence of the backgate and frontgate voltage on the switching characteristics of the SiNW pixels is also studied. In the frontgate mode, the Vth of the SiNW pixels can be tuned at 0.2 V for 1 V change in V-BG for N-type or at -0.2 V for -1 V change in V-BG for P-type pixels. In the backgate mode, it is found that for stable operation of the pixels, the V-G of the N and P-type transistors must be in the range 0.5-2.5 V and 0 V to -2.5 V respectively.

  • 155.
    Johansson, Ted
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Malin, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Norstrom, Hans
    Smith, Ulf
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of SOI-generated stress on BiCMOS performance2006In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 50, no 6, p. 935-942Article in journal (Refereed)
    Abstract [en]

    Two BiCMOS processes were adapted for SOI and the performance of the bipolar devices was studied. Differences in electrical parameters were observed, in particular the current gain, which processing or doping profiles could not explain, but correlated with observed stress in transistors. Simulation of the process flow with stress included revealed that stress was generated to a higher degree in the SOI wafers in the presence of deep trench isolation (DTI). Theoretical estimations and electrical simulations with and without stress yielded results consistent with observed data. Thus, we conclude that the observed differences are caused by process-induced in-plane biaxial stress.

  • 156.
    Johansson, Ted
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Norstrom, H.
    Smith, U.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of SOI-generated stress on BiCMOS performance2005In: Semiconductor Device Research Symposium, 2005 International, 2005, p. 444-445Conference paper (Refereed)
  • 157.
    Jonsson, Fredrik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sandén, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Elnaggar, Mohammed Ismail
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A Voltage Controlled Oscillator with Automatic Amplitude Control in SiGe Technology2001In: 19th Norchip: Kista 12-13 November 2001, 2001, p. 28-33Conference paper (Refereed)
  • 158.
    Kajihara, J.
    et al.
    Japan.
    Kuroki, S. -I
    Japan.
    Ishikawa, S.
    Japan.
    Maeda, T.
    Japan.
    Sezaki, H.
    japan.
    Makino, T.
    Japan.
    Ohshima, T.
    japan.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 423-427Conference paper (Refereed)
    Abstract [en]

    4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200°C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni stack, Nb-Ni Alloy, Ni and Nb/Ti were investigated, and the Nb/Ni stack silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.

  • 159. Kataria, S.
    et al.
    Wagner, S.
    Ruhkopf, J.
    Gahoi, A.
    Pandey, H.
    Bornemann, R.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    Univ Siegen, Germany.
    Chemical vapor deposited graphene: From synthesis to applications2014In: Physica Status Solidi (a) applications and materials science, ISSN 1862-6300, E-ISSN 1862-6319, Vol. 211, no 11, p. 2439-2449Article, review/survey (Refereed)
    Abstract [en]

    Graphene is a material with enormous potential for numerous applications. Therefore, significant efforts are dedicated to large-scale graphene production using a chemical vapor deposition (CVD) technique. In addition, research is directed at developing methods to incorporate graphene in established production technologies and process flows. In this paper, we present a brief review of available CVD methods for graphene synthesis. We also discuss scalable methods to transfer graphene onto desired substrates. Finally, we discuss potential applications that would benefit from a fully scaled, semiconductor technology compatible production process.

  • 160.
    Kolahdouz, Esfahani Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A low cost multi quantum SiGe/Si/Schottky structure for high performance IR detectors2011In: European Solid-State Device Res. Conf., 2011, p. 327-330Conference paper (Refereed)
    Abstract [en]

    SiGe(C)/Si(C) multi quantum wells (MQWs) individually or in series with a Schottky diode (SQW) have been characterized as the thermistor materials for high performance bolometer application. The thermal response of the thermistor materials is expressed in temperature coefficient of resistance (TCR) and an excellent value of 6%/K is obtained for the SQWs. The noise power spectrum density was also measured and the K 1/f was estimated as low as 4.7×10 -14. The outstanding characteristics for the SQWs are due to low defect density and high interfacial quality in the multilayer structures. These results are very promising for the rising market of low cost IR detectors in the near future.

  • 161.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Farniya, Ali Afshar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Improving the performance of SiGe-based IR detectors2010In: Sige, Ge, And Related Compounds 4: Materials, Processing, And Devices, Electrochemical Society, 2010, no 6, p. 221-225Conference paper (Refereed)
    Abstract [en]

    During recent years, single crystalline (Sc) SiGe has been recognized as a new low cost thermistor material for IR detection. In this study the effect of Ge content, pixel size and the Ni silicide on the performance of SiGe/Si thermistor material have been presented. The noise level was decreased for more than one order of magnitude when the Ni silicide layer was integrated below the metal contacts. The silicidation slightly improved TCR values for the detectors(+0.22%/K). However, Increasing the Ge content had the most significant effect on the TCR. A statistical analysis was applied to evaluate the effect of each parameter. It was found using the factorial method that decreasing the pixel size will enhance the TCR value.

  • 162.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Farniya, Ali Afshar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    The performance improvement evaluation for SiGe-based IR detectors2011In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 62, no 1, p. 72-76Article in journal (Refereed)
    Abstract [en]

    During recent years, single crystalline (Sc) SiGe has been recognized as a new low cost thermistor material for IR detection. In this study the effect of Ge content, pixel size and the Ni silicide on the performance of SiGe/Si thermistor material have been presented. The noise level was decreased for more than one order of magnitude when the Ni silicide layer was integrated below the metal contacts. The silicidation slightly improved TCR values for the detectors (+0.22%/K). However, increasing the Ge content had the most significant effect on the TCR. A statistical analysis was applied to evaluate the effect of each parameter. Using the factorial method, it was realized that decreasing the pixel size would enhance the TCR value.

  • 163.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Khatibi, Ali
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, Rick
    Riley, Deborah J.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Comprehensive Evaluation and Study of Pattern Dependency Behavior in Selective Epitaxial Growth of B-Doped SiGe Layers2009In: IEEE transactions on nanotechnology, ISSN 1536-125X, E-ISSN 1941-0085, Vol. 8, no 3, p. 291-297Article in journal (Refereed)
    Abstract [en]

    The influence of chip layout and architecture on the pattern dependency of selective epitaxy of B-doped SiGe layers has been studied. The variations of Ge-, B-content, and growth rate have been investigated locally within a wafer and globally from wafer to wafer. The results are described by the gas depletion theory. Methods to control the variation of layer profile are suggested.

  • 164.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, R.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Selective Epitaxial Growth with Full Control of Pattern Dependency Behavior for pMOSFET Structures2008In: SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES / [ed] Harame D; Caymax M; Koester S; Miyazaki S; Rim K; Tillack B; Boquet J; Cressier J; Masini G; Reznicek A; Takagi S, 2008, Vol. 16, no 10, p. 153-158Conference paper (Refereed)
    Abstract [en]

    This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in pMOSPET structures. The pattern dependency behavior of tile growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by gas depletion theory of the growth species in tile stationary boundary layer over tile wafer. The control of SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a water pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.

  • 165.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wise, R.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Selective Epitaxial Growth with Full Control of Pattern Dependency Behavior for pMOSFET Structures2009In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 156, no 3, p. H169-H171Article in journal (Refereed)
    Abstract [en]

    This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) structures. The pattern dependency behavior of the growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by the gas depletion theory of the growth species in the stationary boundary layer over the water. Control of the SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.

  • 166.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Maresca, Luca
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Riley, D.
    Wise, R.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    New method to calibrate the pattern dependency of selective epitaxy of SiGe layers2009In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 53, no 8, p. 858-861Article in journal (Refereed)
    Abstract [en]

    Selective epitaxial growth (SEG) of Si1-xGex layers on patterned substrates containing isolated, grouped and global chips has been investigated. The interaction between chips on a wafer was studied, and the results are explained by kinetic gas theory for CVD techniques. A test pattern was designed with a series of grouped chips to calibrate the pattern dependency of SEG (both growth rate and Ge content). The amount of exposed Si coverage on chips in the test pattern ranged between 0.05 and 37%. The layer profile of the calibration pattern was compared to profiles on wafers having a global chip design. A model was developed to estimate the Ge content on substrates with a global design.

  • 167.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Moeen, Mahdi
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kinetic Modeling of Low Temperature Epitaxy Growth of SiGe Using Disilane and Digermane2012In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 159, no 5, p. H478-H481Article in journal (Refereed)
    Abstract [en]

    Low temperature epitaxy (LTE) in Chemical Vapor Deposition (CVD) refers to 350-650 degrees C interval. This temperature range is critical for this process since the thermal and lattice mismatch (or strain relaxation) issues diminish in advanced BiCMOS processing. The modeling of the epitaxy process is a vital task to increase the understanding the growth process and to design any desired device structure. In this study, an empirical model for Si2H6/Ge2H6-based LTE of SiGe is developed and compared with experimental work. The model can predict the number of free sites on Si surface, growth rate of Si and SiGe, and the Ge content at low temperatures. A good agreement between the model and the experimental data is obtained.

  • 168.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High performance infra-red detectors based on Si/SiGe multilayers quantum structure2012In: Materials Science & Engineering: B. Solid-state Materials for Advanced Technology, ISSN 0921-5107, E-ISSN 1873-4944, Vol. 177, no 17, p. 1563-1566Article in journal (Refereed)
    Abstract [en]

    Recently, single crystalline (Sc) Si/SiGe multi quantum structure has been recognized as a new low-cost thermistor material for IR detection. Higher signal-to-noise (SNR) ratio and temperature coefficient of resistance (TCR) than existing thermistor materials have converted it to a candidate for infrared (IR) detection in night vision applications. In this study, the effects of Ge content, C doping and the Ni silicidation of the contacts on the performance of SiGe/Si thermistor material have been investigated. Finally, an uncooled thermistor material with TCR of -4.5%/K for 100 μm × 100 μm pixel sizes and low noise constant (K 1/f) value of 4.4 × 10 -15 is presented. The outstanding performance of the devices is due to Ni silicide contacts, smooth interfaces, and high quality multi quantum wells (MQWs) containing high Ge content.

  • 169. Konstantinov, A.
    et al.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zaring, C.
    Keri, I.
    Svedberg, J. -O
    Gumaelius, K.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Reimark, M.
    Operation of Silicon Carbide BJTs Free from Bipolar Degradation2010In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2 / [ed] Bauer, AJ; Friedrichs, P; Krieger, M; Pensl, G; Rupp, R; Seyller, T, 2010, p. 1057-1060Conference paper (Refereed)
    Abstract [en]

    The mechanisms of bipolar degradation in silicon carbide BJTs are investigated and identified. Bipolar degradation occurs as result of stacking fault (SF) growth within the low-doped collector region. A stacking fault blocks vertical current transport through the collector, driving the defective region into saturation. This results in considerable drop of emitter current gain if the BJT is run at a reasonably low collector-emitter bias. The base region does not play any significant role in bipolar degradation. Long-term stress tests have shown full stability of large-area high-power BJTs under minority carrier injection conditions provided the devices are fabricated using low Basal Plane Dislocation (BPD) material. However, an approximately 20% current gain compression is observed for the first 30-60 hours of burn-in under common emitter operation, which is related to instability of surface recombination in the passive base region.

  • 170. Koo, S. -M
    et al.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Forsberg, U.
    Janzen, E.
    Simulation and Measurement of Switching Characteristics of 4H-SiC Buried-Gate JFETs2003In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 433-436, p. 773-776Article in journal (Refereed)
    Abstract [en]

    Buried-gate junction field-effect transistors (JFETs) have been fabricated in 4H polytype silicon carbide (SiC). The dynamic switching characteristics of the JFETs in a circuit with inductive load have been characterized. The drain voltage rise/fall time of ∌30 ns and 25 ns have been observed for turn-off and turn-on, respectively. The results have been compared to numerical mixed-mode circuit simulations with finite element structures.

  • 171. Koo, S. -M
    et al.
    Khartsev, S. I.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Grishin, Alexander. M.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Towards ferroelectric field effect transistors in 4H-silicon carbide2002In: Materials Research Society Symposium - Proceedings, Boston, MA, 2002, Vol. 742, p. 371-379Conference paper (Refereed)
    Abstract [en]

    We report on the integration of ferroelectric Pb(Zr,Ti)O3 (PZT) thin films on 4H-silicon carbide and their electrical properties. The structures of metal-ferroelectric-(insulator)-semiconductor MF(I)S and metal-ferroelectric-metal-insulator-semiconductor MFMIS have been fabricated and characterized. The MFMIS structures of Au/PZT/Pt/Ti/SiO2/SiC have shown fully saturated P-E hysteresis loops with remnant polarization Pr = 14.2 ΌC/cm2 and coercive field Ec = 58.9 kV/cm. The MFIS structures exhibited stable capacitance-voltage C-V loops with low conductance (<0.1 mS/cm2, tan Ύ ∌ 0.0007 at 12 V, 400 kHz) and memory window as wide as 10 V, when a 5 nm-thick Al2O3 was used as a high bandgap (Eg ∌ 9 eV) barrier buffer layer between PZT (Eg ∌ 3.5 eV) and SiC (Eg ∌ 3.2 eV). Both structures on n- and p- SiC have shown electrical properties promising for the application to the gate stacks for the SiC field-effect transistors (FETs) and the design and process issues on different types of the metal-ferroelectric-silicon carbide field-effect transistors (FETs) have also been proposed.

  • 172. Koo, S. M.
    et al.
    Khartsev, Sergiy
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grishin, Alexander M.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ferroelectric Pb(Zr0.52Ti0.48)/SiC field-effect transistor2003In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 83, no 19, p. 3975-3977Article in journal (Refereed)
    Abstract [en]

    Nonvolatile operation of ferroelectric gate field-effect transistors in silicon carbide (SiC) is demonstrated. Depletion mode transistors have been realized by forming a Pb(Zr0.52Ti0.48)O-3/Al2O3 gate stack on n-type epitaxial channel layer and p-type substrate of 4H-SiC. A memory window, as wide as 5 V, has been observed in the drain current and the ferroelectric gate voltage transfer characteristics. The transistor showed memory effect from room temperature up to 200 degreesC, whereas stable transistor operation was observed up to 300 degreesC. The retention of remnant polarization was preserved after 2x10(4) s at 150 degreesC with no bias on the gate.

  • 173. Koo, S. M.
    et al.
    Khartsev, Sergiy
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grishin, Alexander M.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ferroelectric Pb(Zr,Ti)O-3/Al2O3/4H-SiC diode structures2002In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 81, no 5, p. 895-897Article in journal (Refereed)
    Abstract [en]

    Pb(Zr,Ti)O-3 (PZT) films (450 nm thick) were grown on 4H-silicon carbide (SiC) substrates by a pulsed-laser deposition technique. X-ray diffraction confirms single PZT phase without a preferred orientation. Stable capacitance-voltage (C-V) loops with low conductance (<0.1 mS/cm(2), tan deltasimilar to0.0007 at 400 kHz) and memory window as wide as 10 V were obtained when 5-nm-thick Al2O3 was used as a high band gap (E(g)similar to9 eV) barrier buffer layer between PZT (E(g)similar to3.5 eV) and SiC (E(g)similar to3.2 eV). High-frequency (400 kHz) C-V characteristics revealed clear accumulation, and depletion behavior. Although the charge injection from SiC is the dominant mechanism for C-V hysteresis in PZT/Al2O3/SiC, negligible sweep rate dependence and negligible applied bias dependence were observed compared to that of PZT/SiC. By using room-temperature photoilluminated C-V measurements, the interface states as well as the charge trapping in the PZT/Al2O3 stacks have been calculated.

  • 174. Koo, S. M.
    et al.
    Khartsev, Sergiy
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grishin, Alexander M.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Processing and properties of ferroelectric Pb(Zr,Ti)O-3/silicon carbide field-effect transistor2003In: Integrated Ferroelectrics, ISSN 1058-4587, E-ISSN 1607-8489, Vol. 57, p. 1221-1231Article in journal (Refereed)
    Abstract [en]

    Metal-ferroelectric-(insulator)-semiconductor MF(I)S structures have been fabricated and the properties of pulsed laser-deposited PZT/Al-2 O-3 gate stacks have been studied on n - and p -type 4H-SiC. Among several polytypes of SiC, 4H-SiC is considered as the most attractive one because of its wider bandgap (E-g congruent to 3.2 eV) as well as higher and more isotropic bulk mobility than other polytypes. Single PZT phase without a preferred orientation was confirmed by x-ray diffraction. The interface trap densities N-IT , fixed oxide charges Q(F) , and trapped oxide charges Q HY have been estimated by C-V curves with and without photo-illuminated measurements at room temperature. It is found that the charge injection from SiC is the dominant mechanism for C-V hysteresis. Importantly, with PZT/Al-2 O-3 gate stacks, superior C-V characteristics with negligible sweep rate dependence and negligible time dependence under the applied bias were obtained compared to PZT directly deposited on SiC. The MFIS structures exhibited very stable capacitance-voltage C-V loops with low conductance (<0.1 mS/cm(2) , tan delta similar to 0.0007 at 400 kHz) and memory window as wide as 10 V, when 5 nm-thick Al2O3 was used as a high bandgap (E-g similar to 9 eV) barrier buffer layer between PZT (E-g similar to 3.5 eV) and SiC (E-g similar to 3.2 eV). The structures have shown excellent electrical properties promising for the gate stacks as the SiC field-effect transistors (FETs). Depletion mode transistors were prepared by forming a Pb(Zr-0.52 Ti-0.48 )O-3 /Al-2 O-3 gate stack on 4H-SiC. Based on this structure, ferroelectric Pb(Zr,Ti)O-3 (PZT) thin films have been integrated on 4H-silicon carbide (SiC) in a SiC field-effect transistor process. Nonvolatile operation of ferroelectric-gate field-effect transistors in silicon carbide (SiC) is demonstrated.

  • 175. Koo, S. M.
    et al.
    Lee, S. K.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Electrical characteristics of metal-oxide-semiconductor capacitors on plasma etch-damaged silicon carbide2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 9, p. 1375-1380Article in journal (Refereed)
    Abstract [en]

    The characteristics of metal-oxide-semiconductor (MOS) capacitors formed on inductively coupled plasma (ICP) etch-damaged SiC have been investigated. MOS capacitors were prepared by dry-oxidation on ICP-etch-damaged n- and p-type. 6H- and 4H-SiC. The effect of a sacrificial oxidation treatment on the damaged surfaces has also been examined. Capacitance-voltage and current-voltage measurements of these capacitors were performed and referenced to those of simultaneously prepared control samples without etch damage. The effective interface densities (N-IT) and fixed oxide charges (Q(V)) of etch-damaged samples have been found to increase while the breakdown field strength (E-BD) of the oxide decreases. The barrier height (phib) at the SiC-SiO2, interface, determined from a Fowler-Nordheim analysis, decreased for MOS capacitors on etch-damaged surfaces. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged SiC.

  • 176. Koo, S. -M
    et al.
    Lee, S. -K
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Forsberg, U.
    Janzen, E.
    Influence of trenching effect on the characteristics of buried-gate SiC junction field-effect transistors2002In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 389-393, no 2, p. 1235-1238Article in journal (Refereed)
    Abstract [en]

    Two different structures of junction field-effect transistors in 4H-SiC, with and without trenching effect in the channel region, have been fabricated and characterized. The devices formed with metal mask show a trenching profile (>∌0.2 Όm) after dry etch in the channel groove region and exhibited static induction transistor (SIT)-like characteristics in the sub-threshold region of I-V curves as the channel thickness decreases. The devices without trenching effect have been processed by using a wet-etched oxide mask resulting in a sloped dry-etch profile (Ξ=∌30°) in the channel, and consequently showed well-saturated drain characteristics for all the channel thicknesses. The conduction mechanisms in these JFETs are examined by the potential profiles from two dimensional numerical simulations.

  • 177. Koo, S. M.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Lee, H. S.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Combination of JFET and MOSFET devices in 4H-SiC for high-temperature stable circuit operation2003In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 39, no 12, p. 933-935Article in journal (Refereed)
    Abstract [en]

    A novel combination of junction-gated and metal-oxide-semiconductor field effect transistor (JMOSFET) has been fabricated and characterised in 4H-SiC. The high-temperature stable operation of JMOSFETs has been explored in terms of constant current levels. The JMOSFETs have shown the feasibility for operating with constant on and off current levels from room temperature up to 300degreesC. Another advantage of this device is the improved current density by accumulation of the MOS n-channel.

  • 178.
    Koo, Sang-Mo
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    SiC JMOSFETs for high-temperature stable circuit operation2004In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 457-460, p. 1445-1448Article in journal (Refereed)
    Abstract [en]

    4H-SiC junction-gated and metal-oxide-semiconductor field effect transistors (JMOSFETs) have been fabricated for high temperature stable circuit operation. The JMOSFETs have shown the feasibility for operating with constant on and off current levels from room temperature up to 300 degreesC. Moreover, by accumulating the channel using the MOS gate, over 2.5 times higher current density than normal JFET operation has been achieved. The temperature dependent I-V and the sub-threshold characteristics have been studied by using 2-dimensional simulation.

  • 179. Koo, S.-M.
    et al.
    Khartsev, S. I.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Grishin, Alexander. M.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characteristics of PZT/Al2O3 stack on SiC demonstrated in a NVFET2003In: 34th IEEE Semicondctor Interface Specialists Conference, 2003, 2003Conference paper (Refereed)
  • 180. Koo, S.-M.
    et al.
    Lee, S.-K.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Metal-oxide-semiconductor structures in inductively coupled plasma etch damaged 6H- and 4H-SiC2001In: 32nd IEEE Semiconductor Interface Specialists Conference, 2001, 2001Conference paper (Refereed)
  • 181. Koo, S.-M.
    et al.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Khartsev, S. I.
    Grishin, Alexander. M.
    Multifunction Integration of Junction-MOSFETs and Nonvolatile FETs on a Single 4H-SiC Substrate for 300°C Operation2003In: Proc. IEEE International Electron Devices Meeting (IEDM) 2003, IEEE conference proceedings, 2003, p. 575-578Conference paper (Refereed)
  • 182. Kuroki, S. I.
    et al.
    Nagatsuma, H.
    de Silva, M.
    Ishikawa, S.
    Maeda, T.
    Sezaki, H.
    Kikkawa, T.
    Makino, T.
    Ohshima, T.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of 4H-SiC nMOSFETs in harsh environments, high-temperature and high gamma-ray radiation2016In: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015, Trans Tech Publications Ltd , 2016, p. 864-867Conference paper (Refereed)
    Abstract [en]

    Characteristics of 4H-SiC nMOSFETs with arsenic-doped S/D and NbNi silicide contacts in harsh environments of high-temperature up to 450°C, and high gamma-ray radiation up to over 100 Mrad, were investigated. At high temperature, field effect mobility increased as proportional to T3/2, and threshold voltage was shifted with temperature coefficients of -4.3 mV/K and -2.6 mV/K for oxide thicknesses of 10 nm and 20 nm, respectively. After Co60 gamma-ray exposure of 113 Mrad, the field effect mobility was varied within 8% for oxide thickness of 10 nm, however for 20 nm oxide thickness, this variation was 26%. The threshold voltage shifts were within 6%.

  • 183. Kurose, T.
    et al.
    Kuroki, S. -I
    Ishikawa, S.
    Maeda, T.
    Sezaki, H.
    Makino, T.
    Ohshima, T.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Low-parasitic-capacitance self-aligned 4H-SiC nMOSFETs for harsh environment electronics2018In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 924, p. 971-974Article in journal (Refereed)
    Abstract [en]

    Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure

  • 184.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bipolar Integrated OR-NOR Gate in 4H-SiC2011In: Proceedings of International Conference on Silicon Carbibe and Related Materials 2011, 2011Conference paper (Refereed)
  • 185.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Measurements and simulations of lateral PNP transistors in a SiC NPN BJT technology for high temperature integrated circuits2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 758-761Article in journal (Refereed)
    Abstract [en]

    In this work, a 4H-SiC lateral PNP transistor fabricated in a high voltage NPN technology has been simulated and characterized. The possibility of fabricating a lateral PNP with a current gain larger than 1 has been investigated. Device and circuit level solutions have been performed.

  • 186.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bipolar integrated OR-NOR gate in 4H-SiC2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1257-1260Article in journal (Refereed)
    Abstract [en]

    An integrated bipolar OR-NOR gate based on emitter coupled logic (ECL) is demonstrated in 4H-SiC. Operated from 27 up to 300 °C on -15 V supply voltage the logic gate exhibits stable noise margins (NMs) of about 1 V in the entire temperature range, and high and low output voltage levels that move towards positive voltages when the temperature increases: from -3 up to -2.7 V and from -5.4 up to -5.1 V respectively. In the same temperature range transistor current gain (β) goes from 46 down to 21.

  • 187.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits2013In: Journal of Microelectronics and Electronic Packaging, ISSN 1551-4897, E-ISSN 1555-8037, Vol. 10, no 4, p. 155-162Article in journal (Refereed)
    Abstract [en]

    A 4H-SiC bipolar technology suitable for hightemperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on -15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm² on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

  • 188.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Improved surface passivation by enhanced N2O annealing for high gain 4H-SiC BJTsManuscript (preprint) (Other academic)
  • 189.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SiC Etching and Sacrificial Oxidation Effects on the Performance of 4H-SiC BJTs2014In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 778-780, p. 1005-1008Article in journal (Refereed)
    Abstract [en]

    Performance of 4H-SiC BJTs fabricated on a single 100mm wafer with different SiC etching and sacrificial oxidation procedures is compared in terms of peak current gain in relation to base intrinsic sheet resistance. The best performance was achieved when device mesas were defined by inductively coupled plasma etching and a dry sacrificial oxide was grown at 1100 °C.

  • 190.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-temperature characterization of 4H-SiC darlington transistors for low voltage applications2013In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 740-742, p. 966-969Article in journal (Refereed)
    Abstract [en]

    4H-SiC bipolar Darlington transistors (D-BJTs) for low voltage applications have been fabricated, simulated and characterized up to 300 °C, where they exhibit a current gain of 460. The influence on D-BJT current gain of relative current capability of driver and output BJTs has been investigated, and the collector resistance has been identified as the main limitation for the D-BJTs.

  • 191.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    500 degrees C Bipolar Integrated OR/NOR Gate in 4H-SiC2013In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 34, no 9, p. 1091-1093Article in journal (Refereed)
    Abstract [en]

    Successful operation of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter coupled logic is reported from -40 degrees C to 500 degrees C. Nonmonotonous temperature dependence (previously predicted by simulations but now measured) was observed for the transistor current gain; in the range -40 degrees C - 300 degrees C it decreased when the temperature increased, while it increased in the range 300 degrees C-500 degrees C. Stable noise margins of similar to 1 V were measured for a 2-input OR/NOR gate operated on -15 V supply voltage from 0 degrees C to 500 degrees C for both OR and NOR output.

  • 192.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    ECL-based SiC logic circuits for extreme temperatures2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821-823, p. 910-913Article in journal (Refereed)
  • 193.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 1, p. 11-13Article in journal (Refereed)
    Abstract [en]

    The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50-150 nm were deposited prior to the same annealing process in N2O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, similar to 60% higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of similar to 200 at room temperature and >100 at 300 degrees C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains.

  • 194.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lateral p-n-p Transistors and Complementary SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 4, p. 428-430Article in journal (Refereed)
    Abstract [en]

    Lateral p-n-p transistors and a complementary bipolar technology have been demonstrated for analog integrated circuits. Besides vertical n-p-n's, this technology provides lateral p-n-p's at the cost of one additional lithographic and dry etching step. Both devices share the same epitaxial layers and feature topside contacts to all terminals. The influence on p-n-p current gain of contact topology (circular versus rectangular), effective base width, base/emitter doping ratio, and temperature was studied in detail. In the range -40 degrees C to 300 degrees C, the current gain of the p-n-p transistor shows a maximum of similar to 37 around 0 degrees C and decreases to similar to 8 at 300 degrees C, whereas in the same range, the gain of n-p-n transistors exhibits a negative temperature coefficient.

  • 195.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Danielsson, Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Electrical characteristics of 4H-SiC BJTs at elevated temperatures2005In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 483-485, p. 897-900Article in journal (Refereed)
    Abstract [en]

    The DCI-V characteristics of 4H-SiC BJTs have been studied in the temperature range 25 &DEG; C to 300 &DEG; C. The DC current gain at 300 &DEG; C decreased 56% compared to its value at 25 &DEG; C. Under high power operation, the SiC BJTs were strongly influenced by self-heating, which significantly limits the performance of device. Pulsed measurements were performed and compared to DC measurements to distinguish the effects of self-heating. From DC IN measurements, the junction temperature and thermal resistance were extracted to 102 &DEG; C and 19 &DEG; C/W respectively for a power level of 7.3 W at ambient temperature 25 &DEG; C.

  • 196.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 8, p. 1894-1898Article in journal (Refereed)
    Abstract [en]

    This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 x 1.8 nun (with an active area of 3.24 mm') showed a common emitter current gain 0 of 42, specific on-resistance Rsp ON of 9 mQ - em', and open-base breakdown voltage BVcEO of-1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the p+ regrown layer from the surface of the emitter-base junction. The BJT with p+ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs; with only etched flat-surface JTE.

  • 197.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Allerstam, F.
    Sveinbjörnsson, E. Ö.
    1200 V 4H-SiC BJTs with a Common Emitter Current Gain of 60 and Low On-resistance2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 600-603, p. 1151-1154Article in journal (Refereed)
    Abstract [en]

    This paper reports a 4H-SiC bipolar junction transistor (BJT) with a breakdown voltage (BVCEO) of 1200 V, a maximum current gain (beta) of 60 and the low on-resistance (Rsp-on)of 5.2 m Omega cm(2). The high gain is attributed to an improved surface passivation SiO2 layer which was grown in N2O ambient in a diffusion furnace. The SiC BJTs with passivation oxide grown in N2O ambient show less emitter size dependence than reference SiC BJTs, with conventional SiO2 passivation, due to a reduced surface recombination current. SiC BJT devices with an active area of 1.8 mm x 1.8 mm showed a current gain of 53 in pulsed mode and a forward voltage drop Of V-CE=2V at I-C=15 A (J(C)=460 A/cm(2)).

  • 198.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    4H-SiC power BJTs with high current gain and low on-resistance2007In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 556-557, p. 767-770Article in journal (Refereed)
    Abstract [en]

    4H-SiC BJTs have been fabricated with varying geometrical designs. The maximum value of the current gain was about 30 at I-c=85 mA, V-CE=14 V and room temperature (RT) for a 20 mu m emitter width structure. A collector-emitter voltage drop V-CE of 2 V at a forward collector current 55 mA (J(C) = 128 A/cm(2)) was obtained and a specific on-resistance of 15.4 m Omega center dot cm(2) was extracted at RT. Optimum emitter finger widths and base-contact implant distances were derived from measurement. The temperature dependent DC IN characteristics of the BJTs have been studied resulting in 45 % reduction of the gain and 75 % increase of the on-resistance at 225 degrees C compared to RT. Forward-bias stress on SiC BJTs was investigated and about 20 % reduction of the initial current gain was found after 27.5 hours. Resistive switching measurements with packaged SiC BJTs were performed showing a resistive fast turn-on with a VCE fall-time of 90 ns. The results indicate that significantly faster switching can be obtained by actively controlling the base current.

  • 199.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Low-forward-voltage-drop 4H-SiC BJTs without base contact implantation2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 8, p. 1907-1911Article in journal (Refereed)
    Abstract [en]

    Bipolar junction transistors (BJTs) of 4H-SiC, with a low collector--emitter forward voltage drop YCE, have been fabricated without base contact implantation. A comparison of BJTs on the same wafer with and without base contact implantation shows less than 10% higher VcE for the BJTs without base contact implantation. Omitting the base contact implantation eliminates high concentrations of implantation-induced defects that act as recombination centers. This is advantageous because it allows a shorter distance Wp+ between the emitter edge and the base contact, without affecting the current gain when no base contact implantation is used. The BJTs without contact implantation show a constant current gain as Wp+ was reduced from 3 to I pm, whereas the gain decreased by 45% for the BJTs with base contact implantation for the same reduction of Wp+. A key to the successful fabrication of low-forward-voltage-drop SiC BJTs without base contact implantation is the formation of low-resistivity Ni/Ti/Al ohmic contacts to the base. The contact resistivity on the base region (N-A approximate to 4 x 10(17) cm(-3)) was measured with linear transmission line method structures to PC = 1.9 X 10(-3) Omega cm(2), whereas the contact resistivity with the base contact implantation was PC = 1.3 x 10-4 Omega cm(2), both after rapid thermal processing annealing at 800 degrees C.

  • 200.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Allerstam, F.
    Department of Microtechnology and Nanoscience, Chalmers University of Technology.
    Sveinbjörnsson, Einar Ö.
    Department of Microtechnology and Nanoscience, Chalmers University of Technology.
    Surface passivation oxide effects on the current gain of 4H-SiC bipolar junction transistors2008In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 92, no 8, p. 082113-1-082113-3Article in journal (Refereed)
    Abstract [en]

    Effects of surface recombination on the common emitter current gain have been studied in 4H-silicon carbide (SiC) bipolar junction transistors (BJTs) with passivation formed by conventional dry oxidation and with passivation formed by dry oxidation in nitrous oxide (N2O) ambient. A gradual reduction of the current gain was found after removal of the passivation oxide followed by air exposure. Comparison of the measurement results for two different passivated BJTs indicates that the BJTs with passivation by dry oxidation in nitrous oxide (N2O) ambient show a half order of magnitude reduction of base current, resulting in a half order of magnitude increase of current gain at low currents. This improvement of current gain is attributed to reduced surface recombination caused by reduced interface trap densities at the base-emitter junction sidewall.

1234567 151 - 200 of 469
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