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  • 151. Haghbayan, M. -H
    et al.
    Rahmani, A. -M
    Fattah, M.
    Liljeberg, P.
    Plosila, J.
    Navabi, Z.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Power-aware online testing of manycore systems in the dark silicon era2015Inngår i: Proceedings -Design, Automation and Test in Europe, DATE, IEEE conference proceedings, 2015, s. 435-440Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Online defect screening techniques to detect runtime faults are becoming a necessity in current and near future technologies. At the same time, due to aggressive technology scaling into the nanometer regime, power consumption is becoming a significant burden. Most of today's chips employ advanced power management features to monitor the power consumption and apply dynamic power budgeting (i.e., capping) accordingly to prevent over-heating of the chip. Given the notable power dissipation of existing testing methods, one needs to efficiently manage the power budget to cover test process of a many-core system in runtime. In this paper, we propose a power-aware online testing method for many-core systems benefiting from advanced power management capabilities. The proposed power-aware method uses non-intrusive online test scheduling strategy to functionally test the cores in their idle period. In addition, we propose a test-aware utilization-oriented runtime mapping technique that considers the utilization of cores and their test criticality in the mapping process. Our extensive experimental results reveal that the proposed power-aware online testing approach can efficiently utilize temporarily free resources and available power budget for the testing purposes, within less than 1% penalty on system throughput for the 16nm technology.

  • 152. Haghbayan, M. -H
    et al.
    Rahmani, A. M.
    Miele, A.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Online software-based self-testing in the dark silicon era2017Inngår i: The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era, Springer, 2017, s. 259-287Kapittel i bok, del av antologi (Fagfellevurdert)
    Abstract [en]

    Aggressive technology scaling and intensive computations have caused acceleration in the aging and wear-out process of digital systems, hence leading to an increased occurrence of premature permanent faults. Online testing techniques are becoming a necessity in current and near future digital systems. However, state-of-the-art techniques are not aware of the other digital systems’ power/performance requirements that exist in modern multi-/many-core systems. This chapter presents an approach for power-aware non-intrusive online testing in many-core systems. The approach aims at scheduling at runtime Software-Based Self-Test (SBST) routines on the various cores to exploit their idle periods in order to benefit the potentially available power budget and minimize the performance degradation. Furthermore, a criticality metric is used to identify and rank cores that need testing at a time and power and reliability issues related to the testing at different voltage and frequency levels are taken into account. Experimental results show that the proposed approach can (1) efficiently perform cores’ testing, within less than 1?% penalty on system throughput and by dedicating only 2?% of the actual consumed power, (2) adapt to the current stress level of the cores by using the utilization metric, and (3) cover all the voltage and frequency levels during the various tests.

  • 153. Haghbayan, M. -H
    et al.
    Rahmani, A. -M
    Weldezion, Awet Yemane
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Liljeberg, P.
    Plosila, J.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. Department of Information Technology, University of Turku, Turku, Finland .
    Dark silicon aware power management for manycore systems under dynamic workloads2014Inngår i: 2014 32nd IEEE International Conference on Computer Design, ICCD 2014, 2014, s. 509-512Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Dark Silicon denotes the phenomenon that, due to thermal and power constraints, the fraction of transistors that can operate at full frequency is decreasing with each technology generation. We propose a PID (Proportional Integral Derivative) controller based dynamic power management method that considers an upper bound on power consumption (called the Thermal Design Power (TDP)). To avoid violation of the TDP constraint for manycore systems running highly dynamic workloads, it provides fine-grained DVFS (Dynamic Voltage and Frequency Scaling) including near-threshold operation. In addition, the method distinguishes applications with hard Real-Time, soft Real-Time and no Real-Time constraints and treats them with appropriate priorities. In simulations with dynamic workloads mixed-critical application profiles, we show that the method is effective in honoring the TDP bound and it can boost system throughput by over 43% compared to a naive TDP scheduling policy.

  • 154.
    Haghbayan, Mohammad-Hashem
    et al.
    University of Turku, Finland.
    Kanduri, Anil
    University of Turku, Finland.
    Rahmani, Amir-Mohammad
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Liljeberg, Pasi
    University of Turku, Finland.
    Jantsch, Axel
    TU Wien, Austria.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip2015Inngår i: NOCS '15 Proceedings of the 9th International Symposium on Networks-on-Chip, ACM Digital Library, 2015Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Increasing dynamic workloads running on NoC-based many-core systems necessitates efficient runtime mapping strategies. With an unpredictable nature of application profiles, selecting a rational region to map an incoming application is an NP-hard problem in view of minimizing congestion and maximizing performance. In this paper, we propose a proactive region selection strategy which prioritizes nodes that offer lower congestion and dispersion. Our proposed strategy, MapPro, quantitatively represents the propagated impact of spatial availability and dispersion on the network with every new mapped application. This allows us to identify a suitable region to accommodate an incoming application that results in minimal congestion and dispersion. We cluster the network into squares of different radii to suit applications of different sizes and proactively select a suitable square for a new application, eliminating the overhead caused with typical reactive mapping approaches. We evaluated our proposed strategy over different traffic patterns and observed gains of up to 41% in energy efficiency, 28% in congestion and 21% dispersion when compared to the state-of-the-art region selection methods.

  • 155. Haghbayan, Mohammad-Hashem
    et al.
    Miele, Antonio
    Rahmani, Amir M.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Liljeberg, Pasi
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. Univ Turku.
    A Lifetime-Aware Runtime Mapping Approach for Many-core Systems in the Dark Silicon Era2016Inngår i: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE conference proceedings, 2016, s. 854-857Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach.

  • 156. Haghbayan, Mohammad-Hashem
    et al.
    Rahmani, Amir M.
    Liljeberg, Pasi
    Jantsch, Axel
    Miele, Antonio
    Bolchini, Cristiana
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Can Dark Silicon Be Exploited to Prolong System Lifetime?2017Inngår i: IEEE design & test, ISSN 2168-2356, E-ISSN 2168-2364, Vol. 34, nr 2, s. 51-59Artikkel i tidsskrift (Fagfellevurdert)
  • 157. Haghbayan, Mohammad-Hashem
    et al.
    Rahmani, Amir-Mohammad
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Miele, Antonio
    Fattah, Mohammad
    Plosila, Juha
    Liljeberg, Pasi
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures2016Inngår i: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, nr 3, s. 730-743Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Aggressive technology scaling triggers novel challenges to the design of multi-/many-core systems, such as limited power budget and increased reliability issues. Today's many-core systems employ dynamic power management and runtime mapping strategies trying to offer optimal performance while fulfilling power constraints. On the other hand, due to the reliability challenges, online testing techniques are becoming a necessity in current and near future technologies. However, state-of-the-art techniques are not aware of the other power/performance requirements. This paper proposes a power-aware non-intrusive online testing approach for many-core systems. The approach schedules software based self-test routines on the various cores during their idle periods, while honoring the power budget and limiting delays in the workload execution. A test criticality metric, based on a device aging model, is used to select cores to be tested at a time. Moreover, power and reliability issues related to the testing at different voltage and frequency levels are also handled. Extensive experimental results reveal that the proposed approach can i) efficiently test the cores within the available power budget causing a negligible performance penalty, ii) adapt the test frequency to the current cores' aging status, and iii) cover available voltage and frequency levels during the testing.

  • 158. Haghbayan, Mohammad-Hashem
    et al.
    Teravainen, Sami
    Rahmani, Amir-Mohammad
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. Turku Univ..
    Liljeberg, Pasi
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Adaptive Fault Simulation on Many-core Microprocessor Systems2015Inngår i: PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS), IEEE Computer Society, 2015, s. 151-154Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platfonn, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.

  • 159.
    Hamed, Zaid
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku (UTU), Finland.
    Yang, Geng
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    A Programmable Low Power Current Source for Bioimpedance Measurement: Towards a Wearable Personalized Health2015Inngår i: 2015 37th Annual International Conference of The IEEE ENGINEERING in Medicine and Biology Society (EMBC), 2015, s. 2038-2042Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Bioimpedance is a noninvasive measurement method that facilitates body composition analysis, besides being indicative of many other health parameters. In this work a novel programmable, low complexity, high output impedance, high voltage compliance and wideband current source for bioimpedance applications is presented. Previously, we designed, fabricated and tested in vivo a bio-patch for acquisition of multiple bio-signals [1]. Upon integration with our previous work, this circuit is envisioned to constitute part of a personalized health assistant. Simulation at worst case corners and real operation conditions was carried out using UMC-180 nm 1 poly 6 metal CMOS process. Full duty cycle, shortened or stepped square waves can be generated. Amplitude control of 8 different current levels is supported. Frequency can be tuned up to 1 MHz and an output impedance of 2.8 MO @ 250 KHz is achieved at full current capacity. Total current consumption is comparable to the injected current, making the circuit highly efficient.

  • 160. Hellberg, L.
    et al.
    Hemani, A.
    Isoaho, J.
    Jantsch, A.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Mokhtari, M.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    System Oriented VLSI Curriculum at KTH1997Inngår i:  , 1997Konferansepaper (Fagfellevurdert)
  • 161. Hellberg, L.
    et al.
    Hemani, A.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Isoaho, J.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Mokhtari, M.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Integration of Physical and Functional Electronic System Representations in Electronic Curriculum1997Inngår i:  , 1997Konferansepaper (Fagfellevurdert)
  • 162.
    Hellberg, Lars
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hemani, Ahmed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Isoaho, Jouni
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Mokhtari, Mehran
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    System oriented VLSI curriculum at KTH1997Inngår i:  , 1997, s. 57-59Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products

  • 163. Hemani, A.
    et al.
    Svantesson, B.
    Ellervee, P.
    Postula, A.
    Öberg, J.
    Jantsch, A.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    High-level Synthesis of Control and Memory Intensive Communication Systems1995Inngår i:  , 1995Konferansepaper (Fagfellevurdert)
  • 164.
    Hemani, Ahmed
    et al.
    KTH, Tidigare Institutioner (före 2005), Mikroelektronik och informationsteknik, IMIT.
    Lazraq, T.
    Postula, Adam
    Department of CSEE, University of Queensland.
    Svantesson, Bengt
    KTH, Tidigare Institutioner (före 2005), Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner (före 2005), Mikroelektronik och informationsteknik, IMIT.
    Design of Operation and Maintenance Part of the ATM Protocol1996Inngår i: Journal on Communications, Hungarian Scientific Society for Telecommunications, special issue on ATM networks, s. 34-39Artikkel i tidsskrift (Fagfellevurdert)
  • 165.
    Hemani, Ahmed
    et al.
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Mokhtari, Mehran
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Isoaho, Jouni
    Tampere University of Technology, Signal Processing Laboratory.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A structure of modern VLSI curriculum1994Inngår i:  , 1994, s. 204-208Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper describes the restructuring of VLSI education at Royal Institute of Technology, Sweden. Changing needs of industry, advances in technology and design methodology has required a significant reorganisation of VLSI education with emphasis on system issues. This restructuring is not viewed as a one step process, rather as a continuous process including close interaction between education and research

  • 166.
    Hemani, Ahmed
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Svantesson, Bengt
    Ellervee, Peeter
    Postula, Adam
    Öberg, J.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Trade-offs in High-level Synthesis of Telecommunication Circuits1995Inngår i:  , 1995Konferansepaper (Fagfellevurdert)
  • 167.
    Hemani, Ahmed
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Svantesson, Bengt
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ellervee, Peeter
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Postula, Adam
    Dept. of Electrical and Computer Engineering, University of Queensland.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    High-level synthesis of control and memory intensive communication systems1995Inngår i:  , 1995, s. 185-191Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level

  • 168.
    Hemani, Ahmed
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Svantesson, Bengt
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ellervee, Peeter
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Postula, Adam
    Dept. of Electrical and Computer Engineering, University of Queensland.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Trade-offs in High-level Synthesis of Telecommunication Circuits1995Konferansepaper (Fagfellevurdert)
  • 169.
    Hemani, Ahmed
    et al.
    KTH, Tidigare Institutioner (före 2005), Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner (före 2005), Mikroelektronik och informationsteknik, IMIT.
    Mokhtari, Mehran
    KTH, Tidigare Institutioner (före 2005), Mikroelektronik och informationsteknik, IMIT.
    Hellberg, Lars
    KTH, Tidigare Institutioner (före 2005), Mikroelektronik och informationsteknik, IMIT.
    Restructuring VLSI Education at Royal Inst. Of Technology1993Konferansepaper (Fagfellevurdert)
  • 170.
    Huan, Yuxiang
    et al.
    KTH, Skolan för elektroteknik och datavetenskap (EECS). Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Xu, Jiawei
    Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Zheng, Li-rong
    KTH. Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    Zou, Zhuo
    Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    A 3D Tiled Low Power Accelerator for Convolutional Neural Network2018Inngår i: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Konferansepaper (Fagfellevurdert)
    Abstract [en]

    It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.

  • 171. Ibwe, K. S.
    et al.
    Kalinga, E. A.
    Mvungi, N. H.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT).
    Taajamaa, V.
    The impact of industry participation on challenge based learning2018Inngår i: International Journal of Engineering ,Science and Innovative Technology, ISSN 0949-149X, E-ISSN 2277-3754, Vol. 34, nr 1, s. 187-200Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The future of learning is being revolutionized by challenge based learning (CBL), where academia offers solutions to real life challenges. Unfortunately, in developing countries academia overlook the importance of involving stakeholders who are the prospective owners of the solutions developed. This is because of the weak link between academic institutions and industry in research and development activities. However, to solve real life challenges faced by the society the researchers need to work closely and continuously with the targeted community for them to get the sense of ownership and for the solutions to take into account all relevant factors. This paper presents the impacts realized when eight stakeholders were fully involved from identification to developing solutions of the challenges facing the electrical power sector in Tanzania which is wholly managed by a public utility company TANESCO from generation to distribution. Challenge based courses introduced in taught PhD and MSc programs were used to create the necessary skills but also to evaluate the effectiveness of the approach in realizing the intended objectives. Nine PhD and six MSc students were involved. The stakeholders' involvement helped the research students to align the identification of the challenges to be in line with societal perception rather being purely scientific and/or technical like excessive reactive power or skin effect and to work in multidisciplinary teams. This paper presents the process adopted in real life challenges identification, the proposed solutions to the identified challenges and how academia can link with industry in solving real-life problems facing the society, in particular the higher learning institutions in developing countries. 

  • 172.
    Ibwe, Kwame
    et al.
    Univ Dar Es Salaam, Dar Es Salaam, Tanzania..
    Kalinga, Ellen
    Univ Dar Es Salaam, Dar Es Salaam, Tanzania..
    Mvungi, Nerey
    Univ Dar Es Salaam, Dar Es Salaam, Tanzania..
    Kelati, Amleset
    KTH.
    Tenhunen, Hannu
    KTH.
    Ben Dhaou, Imed
    Qassim Univ, Buraydah, Saudi Arabia.;Univ Monastir, Monastir, Tunisia..
    The Role of Challenge Driven Learning in Activating Industry-Academia Cooperation in Low Income Countries2017Inngår i: 10th International Conference 0f Education, Research and Innovation (ICERI2017) / [ed] Chova, LG Martinez, AL Torres, IC, International Academy of Technology, Education and Development (IATED) , 2017, s. 8158-8166Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The industry-academia cooperation to solve the real-life problems facing the societies of which the industry and academia are serving is a common phenomenon in developed economies and even to some of the middle-income countries. The challenges with such cooperation come from the level of trust that the industries have in the capacity of academia to solve their technical and scientific challenges. These challenges are vividly observable in low-income countries where large multinational companies having franchisees in these countries do not prefer local experts from academic institutions but rather engage such services from developed countries. The same applies to local companies and industries, public institutions and government agencies. The challenge does not come from the incompleteness of the academia to solve such challenges, but from the long perceived stigma that academia solutions are merely theoretical and cannot be realized in practice. This may have been perpetrated by the way academia have been conducting their research and development projects. Conventionality, academia identified a challenge for industry and started working on perceived solution to the change from start to finish just to find a nice work prototype mismatch the actual operational environment and conditions. The importance of the cooperation with the industries was only a concept which was never realized. It is important that the cooperation is emphasized early to avoid the current situation of not recognizing the potentials, and/or using the local academia multidisciplinary capacity. The challenge is how to make academia to effectively engage with local industries for the mutual benefits of both parties in low-income countries. Hence, challenge driven learning (CDL) is perceived as a possible way forward. To that effect, postgraduate course for MSc and PhD programme was introduced specifically to use challenge driven education approach. It is a project based course focused on building capacity in group/team work and multidisciplinary engagement to reflect demands for addressing a real life challenge. The challenge to the students which was systematically chosen inefficient and ineffective methods/systems used to clear faults which occur in different parts of the electrical power system network, either reported or observed by the utility company staff. The students, therefore, worked to develop solutions to facilitate efficient fault clearance jointly with utility company staff involved design, innovation, workshops with stakeholders, site visits and feedback from stakeholders. The regular involvement of the key stakeholder user, the utility company, was perceived as a means to promote and strengthen industry-academia cooperation in low-income countries. The Question is how can academia win trust from industries in low-income countries that they can solve their real-life problems? This paper adopts the perspective of challenge driven learning (CDL) methodology using a project based course in a postgraduate program as a tool. The validation data for this paper are based on inputs from the PhD and Masters CDL attending the course and the utility company staff. Based on the literature review, student's iterative designs based on student's presentations to client and to other stakeholders in workshops, complimentary site visits to study the actual situation on the ground and environment the students refined their designs and implementation strategies.

  • 173. Iqbal, M. S.
    et al.
    Shahid, H.
    Riaz, M. A.
    Rauf, S.
    Amin, Y.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
    FSS inspired polarization insensitive chipless RFID tag2017Inngår i: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 14, nr 10Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A polarization insensitive, compact, fully-passive bit encoding structure exhibiting 1 : 1 resonator-to-bit correspondence is presented. Inspired by frequency selective surface (FSS) based microwave absorbers, the structure readily operates as a chipless radio frequency identification (RFID) tag. The unit cell is composed of several concentric hexagonal loops. Finite repetitions of the unit cell constitute the proposed RFID tag in its entirety. The required bit sequence is encoded in the frequency domain by addition or omission of corresponding nested resonant elements. A functional prototype is fabricated on a commercial-grade grounded FR4 substrate, occupying a physical footprint of 23 × 10mm2 while offering a capacity of 14 bits. The proposed tag boasts a minuscule profile, and demonstrates polarization insensitivity as well as stable oblique angular performance.

  • 174. Isoaho, J A
    et al.
    Rantala, P A
    Nurmi, T J
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    New course on computational platforms towards nanoscale systems2005Inngår i: 23rd NORCHIP Conference 2005, 2005, s. 226-229Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper we present an educational approach for a paradigm shift needed when changing from deep submicron CMOS designs to real nano andnanoscaletechnologies [7] in complex communication and computationsystemimplementations. Here we present an introductioncourseimplemented for starting the paradigm shift in curriculum. Here we presentcoursetargets, structure and implementation as well as future designer competence profiles. Thecourseis consisting of five thematic areas: nano-scale technologies, parallelplatforms, concurrent algorithms, reconfigurablesystemsand autonomoussystemmanagement. These thematic areas compound the core of future nanosystems educational program upgrades for current NoC curricula.

  • 175.
    Isoaho, Jouni
    et al.
    Tampere University of Technology, Signal Processing Laboratory.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hemani, Ahmed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    High level synthesis in DSP ASIC optimization1994Inngår i:  Proc. of 7th IEEE ASIC Conference and Exhibit, 1994, s. 75-78Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples

  • 176.
    Isoaho, Jouni
    et al.
    Tampere University of Technology, Signal Processing Laboratory.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hemani, Ahmed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    HLS based DSP optimization with ASIC RTL libraries1994Inngår i:  , 1994, s. 218-225Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach

  • 177.
    Jabeen, Iqra
    et al.
    Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan..
    Ejaz, Asma
    Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan..
    Akram, Adeel
    Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan..
    Amin, Yasar
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektroteknik, Elektronik och inbyggda system, Integrerade komponenter och kretsar. Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan.;Royal Inst Technol KTH, Dept Elect Syst, iPack Vinn Excellence Ctr, Stockholm, Sweden..
    Loo, Jonathan
    Middlesex Univ, Sch Engn & Informat Sci, Dept Comp Sci, London, England..
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektroteknik, Elektronik och inbyggda system, Integrerade komponenter och kretsar. Univ Turku, TUCS, Dept Informat Technol, Turku, Finland..
    Elliptical slot based polarization insensitive compact and flexible chipless RFID tag2019Inngår i: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 29, nr 11, artikkel-id e21734Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A miniaturized, polarization insensitive, and fully passive chipless radio frequency identification tag is proposed in this research article. The realized tag is based on slotted elliptical structures in a nested loop fashion with identical lengths and widths of slot resonators. Alteration of data sequence is accomplished by addition and elimination of nested resonators in the geometric structure. The tag is capable to encode 10 bits of data and covers spectral range from 3.6 to 15.6 GHz. The formulated structure demonstrates polarization insensitive characteristic. The data encoding structure is analyzed and optimized for different substrates that are, Rogers RT/duroid/5880, Rogers RT/duroid/5870, and Taconic TLX-0 over the miniaturized footprint of 22.8 x 16 mm(2). The presented tag is robust, novel, compact, and flexible exhibiting a stable response to impinging electromagnetic waves at various angles of incidence.

  • 178.
    Jafri, Syed. M. A. H.
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Bag, Ozan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Farahini, Nasim
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Kolin, Paul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Plosila, Juha
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Energy-Aware Coarse-Grained Reconfigurable Architectures using Dynamically Reconfigurable Isolation Cells2013Inngår i: Proceedings Of The Fourteenth International Symposium On Quality Electronic Design (ISQED 2013), 2013, s. 104-111Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a self adaptive architecture to enhance the energy efficiency of coarse-grained reconfigurable architectures (CGRAs). Today, platforms host multiple applications, with arbitrary inter-application communication and concurrency patterns. Each application itself can have multiple versions (implementations with different degree of parallelism) and the optimal version can only be determined at runtime. For such scenarios, traditional worst case designs and compile time mapping decisions are neither optimal nor desirable. Existing solutions to this problem employ costly dedicated hardware to configure the operating point at runtime (using DVFS). As an alternative to dedicated hardware, we propose exploiting the reconfiguration features of modern CGRAs. Our solution relies on dynamically reconfigurable isolation cells (DRICs) and autonomous parallelism, voltage, and frequency selection algorithm (APVFS). The DRICs reduce the overheads of DVFS circuitry by configuring the existing resources as isolation cells. APVFS ensures high efficiency by dynamically selecting the parallelism, voltage and frequency trio, which consumes minimum power to meet the deadlines on available resources. Simulation results using representative applications (Matrix multiplication, FIR, and FFT) showed up to 23% and 51% reduction in power and energy, respectively, compared to traditional DVFS designs. Synthesis results have confirmed significant reduction in area overheads compared to state of the art DVFS methods.

  • 179. Jafri, Syed M. A. H.
    et al.
    Ozbag, Ozan
    KTH.
    Farahini, Nasim
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Paul, Kolin
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Plosila, Juha
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs2015Inngår i: ACM Journal on Emerging Technologies in Computing Systems, ISSN 1550-4832, Vol. 11, nr 4, artikkel-id 40Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In the era of platforms hosting multiple applications with arbitrary performance requirements, providing a worst-case platform-wide voltage/frequency operating point is neither optimal nor desirable. As a solution to this problem, designs commonly employ dynamic voltage and frequency scaling (DVFS). DVFS promises significant energy and power reductions by providing each application with the operating point (and hence the performance) tailored to its needs. To further enhance the optimization potential, recent works interleave dynamic parallelism with conventional DVFS. The induced parallelism results in performance gains that allow an application to lower its operating point even further (thereby saving energy and power consumption). However, the existing works employ costly dedicated hardware (for synchronization) and rely solely on greedy algorithms to make parallelism decisions. To efficiently integrate parallelism with DVFS, compared to state-of-the-art, we exploit the reconfiguration (to reduce DVFS synchronization overheads) and enhance the intelligence of the greedy algorithm (to make optimal parallelism decisions). Specifically, our solution relies on dynamically reconfigurable isolation cells and an autonomous parallelism, voltage, and frequency selection algorithm. The dynamically reconfigurable isolation cells reduce the area overheads of DVFS circuitry by configuring the existing resources to provide synchronization. The autonomous parallelism, voltage, and frequency selection algorithm ensures high power efficiency by combining parallelism with DVFS. It selects that parallelism, voltage, and frequency trio which consumes minimum power to meet the deadlines on available resources. Synthesis and simulation results using various applications/algorithms (WLAN, MPEG4, FFT, FIR, matrix multiplication) show that our solution promises significant reduction in area and power consumption (23% and 51%) compared to state-of-the-art.

  • 180. Jafri, Syed M. A. H.
    et al.
    Piestrak, Stanislaw J.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Paul, Kolin
    Plosila, Juha
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Private reliability environments for efficient fault-tolerance in CGRAs2014Inngår i: Design automation for embedded systems, ISSN 0929-5585, E-ISSN 1572-8080, Vol. 18, nr 3-4, s. 295-327Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In the era of platforms hosting multiple applications with variable reliability needs, worst-case platform-wide fault-tolerance decisions are neither optimal nor desirable. As a solution to this problem, designs commonly employ adaptive fault-tolerance strategies that provide each application with the reliability level actually needed. However, in the CGRA domain, the existing schemes either only allow to shift between different levels of modular redundancy (duplication, triplication, etc.) or protect only a particular region of a device (e.g. configuration memory, computation, or data memory). To complement these strategies, we propose private fault-tolerance environments which, in addition to modular redundancy, also provide low cost sub-modular (e.g. residue mod 3) redundancy capable of handling both permanent and temporary faults in configuration memory, computation, communication, and data memory. In addition, we also present adaptive configuration scrubbing techniques which prevent fault accumulation in the configuration memory. Simulation results using a few selected algorithms (FFT, matrix multiplication, and FIR filter) show that the approach proposed is capable of providing flexible protection with energy overhead ranging from 3.125 % to 107 % for different reliability levels. Synthesis results have confirmed that the proposed architecture reduces the area overhead for self-checking (58 %) and fault-tolerant (7.1 %) versions, compared to the state of the art adaptive reliability techniques.

  • 181.
    Jafri, Syed M. A. H.
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Tajammul, Adeel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    Indian Institute of Technology.
    Ellervee, Peeter
    Plosila, Juha
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Morphable Compression Architecture for Efficient Configuration in CGRAs2014Inngår i: 2014 17th Euromicro Conference on Digital System Design (DSD), 2014, s. 42-49Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads (up to 50% area of the overall platform). As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties (i.e. compression ratio and decoding time), and is therefore best suited for a particular class of applications (and situation). However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to enjoy a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Thereby, our solution offers minimal memory while meeting the required configuration deadlines. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (from configware replication to 52%) and configuration cycles (from 33 nsec to 1.5 secs) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

  • 182.
    Jafri, Syed M.A.H.
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System. University of Turku, Finland.
    Tajammul, Adeel
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System. University of Turku, Finland.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Paul, Kolin
    Ellervee, Peeter
    Plosila, Juha
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System. University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Customizable Compression Architecture for Efficient Configuration in CGRAs2011Inngår i: Proceedings: 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, 2011, s. 31-31Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads. As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties, and is therefore best suited for a particular class of applications. However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform.

  • 183.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Bag, Ozan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Farahini, Nasim
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Energy-Aware CGRAs using Dynamically Re-configurable isolation Cells2013Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a self adaptive architectureto enhance the energy efficiency of coarse-grained reconfigurablearchitectures (CGRAs). Today, platforms host multipleapplications, with arbitrary inter-application communication andconcurrency patterns. Each application itself can have multipleversions (implementations with different degree of parallelism)and the optimal version can only be determined at runtime. Forsuch scenarios, traditional worst case designs and compile timemapping decisions are neither optimal nor desirable. Existingsolutions to this problem employ costly dedicated hardware toconfigure the operating point at runtime (using DVFS). As analternative to dedicated hardware, we propose exploiting thereconfiguration features of modern CGRAs. Our solution relieson dynamically reconfigurable isolation cells (DRICs) and autonomousparallelism, voltage, and frequency selection algorithm(APVFS). The DRICs reduce the overheads of DVFS circuitryby configuring the existing resources as isolation cells. APVFSensures high efficiency by dynamically selecting the parallelism,voltage and frequency trio, which consumes minimum powerto meet the deadlines on available resources. Simulation resultsusing representative applications (Matrix multiplication, FIR,and FFT) showed up to 23% and 51% reduction in powerand energy, respectively, compared to traditional DVFS designs.Synthesis results have confirmed significant reduction in areaoverheads compared to state of the art DVFS methods.

  • 184.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. Turku Centre for Computer Science, Finland; University of Turku, Finland.
    Gia, T.N.
    University of Turku, Finland.
    Dytckov, Sergei
    University of Turku, Finland.
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Plosila, Juha
    Turku Centre for Computer Science, Finland; University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    NeuroCGRA: A CGRA with support for neural networks2014Inngår i: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014, IEEE , 2014, s. 506-511Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) are becoming an increasingly popular implementation platform. In real world applications, the CGRAs are required to simultaneously host processing (e.g. Audio/video acquisition) and estimation (e.g. audio/video/image recognition) tasks. For estimation problems, neural networks, promise a higher efficiency than conventional processing. However, most of the existing CGRAs provide no support for neural networks. To realize realize both neural networks and conventional processing on the same platform, this paper presents NeuroCGRA. NeuroCGRA allows the processing elements and the network to dynamically morph into either conventional CGRA or a neural network, depending on the hosted application. We have chosen the DRRA as a vehicle to study the feasibility and overheads of our approach. Synthesis results reveal that the proposed enhancements incur negligible overheads (4.4% area and 9.1% power) compared to the original DRRA cell.

  • 185.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Guang, Liang
    University of Turku, Finland.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Plosila, Juha
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes2012Inngår i: Proceedings: 15th Euromicro Conference on Digital System Design, DSD 2012, 2012, s. 242-249Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents an energy efficient architectureto provide on-demand fault tolerance to multiple traffic classes,running simultaneously on single network on chip (NoC) platform.Today, NoCs host multiple traffic classes with potentiallydifferent reliability needs. Providing platform-wide worst-case(maximum) protection to all the classes is neither optimal nordesirable. To reduce the overheads incurred by fault tolerance,various adaptive strategies have been proposed. The proposedtechniques rely on individual packet fields and operating conditionsto adjust the intensity and hence the overhead of faulttolerance. Presence of multiple traffic classes undermines theeffectiveness of these methods. To complement the existing adaptivestrategies, we propose on-demand fault tolerance, capableof providing required reliability, while significantly reducing theenergy overhead. Our solution relies on a hierarchical agentbased control layer and a reconfigurable fault tolerance datapath. The control layer identifies the traffic class and directs thepacket to the path providing the needed reliability. Simulationresults using representative applications (matrix multiplication,FFT, wavefront, and HiperLAN) showed up to 95% decrease inenergy consumption compared to traditional worst case methods.Synthesisresultshave confirmedanegligible additionaloverhead,for providing on-demand protection (up to 5.3% area), comparedto the overall fault tolerance circuitry.

  • 186.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Guang, Liang
    University of Turku, Finland.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    Indian Institute of Technology, Delhi, India.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes2013Inngår i: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 37, nr 8, s. 811-822Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents an energy efficient architecture to provide on-demand fault tolerance to multiple traffic classes, running simultaneously on single network on chip (NoC) platform. Today, NoCs host multiple traffic classes with potentially different reliability needs. Providing platform-wide worst-case (maximum) protection to all the classes is neither optimal nor desirable. To reduce the overheads incurred by fault tolerance, various adaptive strategies have been proposed. The proposed techniques rely on individual packet fields and operating conditions to adjust the intensity and hence the overhead of fault tolerance. Presence of multiple traffic classes undermines the effectiveness of these methods. To complement the existing adaptive strategies, we propose on-demand fault tolerance, capable of providing required reliability, while significantly reducing the energy overhead. Our solution relies on a hierarchical agent based control layer and a reconfigurable fault tolerance data path. The control layer identifies the traffic class and directs the packet to the path providing the needed reliability. Simulation results using representative applications (matrix multiplication, FFT, wavefront, and HiperLAN) showed up to 95% decrease in energy consumption compared to traditional worst case methods. Synthesis results have confirmed a negligible additional overhead, for providing on-demand protection (up to 5.3% area), compared to the overall fault tolerance circuitry.

  • 187.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Guang, Liang
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Self-Adaptive NoC Power Management with Dual-Level Agents: Architecture and Implementation2012Inngår i: PECCS 2012 - Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems, 2012, s. 450-458Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Architecture and Implementation of adaptive NoC to improve performance and power consumption is presented. On platforms hosting multiple applications, hardware variations and unpredictable workloads make static design-time assignments highly sub-optimal e.g. in terms of power and performance. As a solution to this problem, adaptive NoCs are designed, which dynamically adapt towards optimal implementation. This paper addresses the architectural design of adaptive NoC, which is an essential step towards design automation. The architecture involves two levels of agents: a system level agent implemented in software on a dedicated general purpose processor and the local agents implemented as microcontrollers of each network node. The system agent issues specific instructions to perform monitoring and reconfiguration operations, while the local agents operate according to the commands from the system agent. To demonstrate the system architecture, best-effort power management with distributed voltage and frequency scaling is implemented, while meeting run-time execution requirements. Four benchmarks (matrix multiplication, FFT, wavefront, and hiperLAN transmitter) are experimented on a cycle-accurate RTL-level shared-memory NoC simulator. Power analysis with 65nm multi-Vdd library shows a significant reduction in energy consumption (from 21 % to 36 %). The synthesis also shows minimal area overhead (4 %) of the local agent compared to the original NoC switch.

  • 188.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Plosila, Juha
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Compact Generic Intermediate representation (CGIR) to enable late binding in Coarse Grained Reconfigurable Architectures2011Konferansepaper (Fagfellevurdert)
  • 189.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Plosila, Juha
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures2011Inngår i: Proc. IEEE Int Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW) Symp, 2011, s. 290-293Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper considers the possibility of speeding up the configuration by reducing the size of configware in coarsegrained reconfigurable architectures (CGRAs). Our goal was to reduce the number of cycles and increase the configuration bandwidth. The proposed technique relies on multicasting and bitstream compression. The multicasting reduces the cycles by configuring the components performing identical functions simultaneously, in a single cycle, while the bitstream compression increases the configuration bandwidth. We have chosen the dynamically reconfigurable resource array (DRRA) architecture as a vehicle to study the efficiency of this approach. In our proposed method, the configuration bitstream is compressed offline and stored in a memory. If reconfiguration is required, the compressed bitstream is decompressed using an online decompresser and sent to DRRA. Simulation results using practical applications showed upto 78% and 22% decrease in configuration cycles for completely parallel and completely serial implementations, respectively. Synthesis results have confirmed nigligible overhead in terms of area (1.2 %) and timing.

  • 190.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Leon, Guillermo Serrano
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Abbas, N.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    Indian Institute of Technology.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    TransPar: Transformation based dynamic Parallelism for low power CGRAs2014Inngår i: Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014, 2014Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer runtime parallelism to reduce energy consumption (by lowering voltage/frequency). To implement the runtime parallelism, CGRAs commonly store multiple compile-time generated implementations of an application (with different degree of parallelism) and select the optimal version at runtime. However, the compile-time binding incurs excessive configuration memory overheads and/or is unable to parallelize an application even when sufficient resources are available. As a solution to this problem, we propose Transformation based dynamic Parallelism (TransPar). TransPar stores only a single implementation and applies a series for transformations to generate the bitstream for the parallel version. In addition, it also allows to displace and/or rotate an application to parallelize in resource constrained scenarios. By storing only a single implementation, TransPar offers significant reductions in configuration memory requirements (up to 73% for the tested applications), compared to state of the art compaction techniques. Simulation and synthesis results, using real applications, reveal that the additional flexibility allows up to 33% energy reduction compared to static memory based parallelism techniques. Gate level analysis reveals that TransPar incurs negligible silicon (0.2% of the platform) and timing (6 additional cycles per application) penalty.

  • 191.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Leon, Guillermo Serrano
    Iqbal, J.
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    Indian Institute of Technology.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs2014Inngår i: Proceedings - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014, 2014, s. 233-241Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Compile-time mapping decisions are neither optimal nor desirable to efficiently support the diverse and unpredictable application requirements. As a solution to this problem, recently proposed architectures offer run-time remapping. The run-time remappers displace or expand (parallelize/serialize) an application to optimize different parameters (such as platform utilization). However, the existing remappers support application displacement or expansion in either horizontal or vertical direction. Moreover, most of the works only address dynamic remapping in packet-switched networks and therefore are not applicable to the CGRAs that exploit circuitswitching for low-power and high predictability. To enhance the optimality of the run-time remappers, this paper presents a design framework called Run-time Rotatable-expandable Partitions (RuRot). RuRot provides architectural support to dynamically remap or expand (i.e. parallelize) the hosted applications in CGRAs with circuit-switched interconnects. Compared to state of the art, the proposed design supports application rotation (in clockwise and anticlockwise directions) and displacement (in horizontal and vertical directions), at run-time. Simulation results using a few applications reveal that the additional flexibility enhances the device utilization, significantly (on average 50 % for the tested applications). Synthesis results confirm that the proposed remapper has negligible silicon (0.2 % of the platform) and timing (2 cycles per application) overheads.

  • 192.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Piestrak, Stanislaw J.
    IJL/Universit´e de Lorraine, France.
    Paul, Kolin
    Indian Institute of Technology, Delhi, India.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs2013Inngår i: Digital System Design (DSD), 2013 Euromicro Conference on, IEEE conference proceedings, 2013, s. 525-534Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a polymorphic fault tolerant architecture that can be tailored to efficiently support the reliability needs of multiple applications at run-time. Today, coarse-grained reconfigurable architectures (CGRAs) host multiple applications with potentially different reliability needs. Providing platform-wide worst-case (maximum) protection to all the applications is neither optimal nor desirable. To reduce the fault-tolerance overhead, adaptive fault-tolerance strategies have been proposed. The proposed techniques access the reliability requirements of each application and adjust the fault-tolerance intensity (and hence overhead), accordingly. However, existing flexible reliability schemes only allow to shift between different levels of modular redundancy (duplication, triplication, etc.) and deal with only a single class of faults (e.g. soft errors). To complement these strategies, we propose energy-aware fault-tolerance that, in addition to modular redundancy, can also provide low cost, sub-modular (e.g. residue mod 3) redundancy, to cater both permanent and temporary faults. Our solution relies on an agent based control layer and a configurable fault-tolerance data path. The control layer identifies the application class and configures the data path to provide the needed reliability. Simulation results using a few selected algorithms (FFT, matrix multiplication, and FIR filter) showed that the proposed method provides flexible protection with energy overhead ranging from 3.125% to 107% for different reliability levels. Synthesis results have confirmed that the proposed architecture significantly reduces the area overhead for self-checking (59.1%) and fault tolerant (7.1%) versions, compared to the state of the art adaptive reliability techniques.

  • 193.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System. University of Turku, Finland.
    Tajammul, Muhammad Adeel
    KTH.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Paul, Kolin
    Plosila, Juha
    Ellervee, Peeter
    Tenuhnen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Polymorphic Configuration Architecture for CGRAs2016Inngår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 24, nr 1, s. 403-407Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In the era of platforms hosting multiple applications with arbitrary reconfiguration requirements, static configuration architectures are neither optimal nor desirable. The static reconfiguration architectures either incur excessive overheads or cannot support advanced features (like time-sharing and runtime parallelism). As a solution to this problem, we present a polymorphic configuration architecture (PCA) that provides each application with a configuration infrastructure tailored to its needs.

  • 194.
    Jafri, Syed Mohammad Asad Hassan
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Tajammul, Muhammad Adeel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, Kolin
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. Indian Institute of Technology.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Energy-Aware-Task-Parallelism for Efficient Dynamic Voltage, and Frequency Scaling, in CGRAs2013Inngår i: Proceedings - 2013 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2013, IEEE , 2013, s. 104-112Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Today, coarse grained reconfigurable architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Each application itself is composed of multiple tasks, spatially mapped to different parts of platform. Providing worst-case operating point to all applications leads to excessive energy and power consumption. To cater this problem, dynamic voltage and frequency scaling (DVFS) is a frequently used technique. DVFS allows to scale the voltage and/or frequency of the device, based on runtime constraints. Recent research suggests that the efficiency of DVFS can be significantly enhanced by combining dynamic parallelism with DVFS. The proposed methods exploit the speedup induced by parallelism to allow aggressive frequency and voltage scaling. These techniques, employ greedy algorithm, that blindly parallelizes a task whenever required resources are available. Therefore, it is likely to parallelize a task(s) even if it offers no speedup to the application, thereby undermining the effectiveness of parallelism. As a solution to this problem, we present energy aware task parallelism. Our solution relies on a resource allocation graphs and an autonomous parallelism, voltage, and frequency selection algorithm. Using resource allocation graph, as a guide, the autonomous parallelism, voltage, and frequency selection algorithm parallelizes a task only if its parallel version reduces overall application execution time. Simulation results, using representative applications (MPEG4, WLAN), show that our solution promises better resource utilization, compared to greedy algorithm. Synthesis results (using WLAN) confirm a significant reduction in energy (up to 36%), power (up to 28%), and configuration memory requirements (up to 36%), compared to state of the art.

  • 195.
    Jafri, Syed
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Piestrak, S. J.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Paul, K.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Implementation and evaluation of configuration scrubbing on CGRAs: A case study2013Inngår i: 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings, IEEE Computer Society, 2013, s. 6675262-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper investigates the overhead imposed by various configuration scrubbing techniques used in fault-tolerant Coarse Grained Reconfigurable Arrays (CGRAs). Today, reconfigurable architectures host large configuration memories. As we progress further in the nanometer regime, these configuration memories have become increasingly susceptible to single event upsets caused e.g. by cosmic radiation. Configuration scrubbing is a frequently used technique to protect these configuration memories against single event upsets. Existing works on configuration scrubbing deal only with FPGA without any reference to the CGRAs (in which configuration memories consume up to 50% of silicon area). Moreover, in the known literature lacks a comprehensive comparison of various configuration scrubbing techniques to guide system designers about the merits/demerits of different scrubbing methods which could be applied to CGRAs. To address these problems, in this paper we classify various configuration scrubbing techniques and quantify their trade-offs when implemented on a CGRA. Synthesis results reveal that scrubbing logic incurs negligible silicon overhead (up to 3% of the area of computational units). Simulation results obtained for a few algorithms/applications (FFT, FIR, matrix multiplication, and WLAN) show that the choice of the configuration scrubbing scheme (external vs. internal) has significant impact on both the size of configuration memory and the number of reconfiguration cycles (respectively 20-80% more and up to 38 times more for the former).

  • 196.
    Jantsch, Axel
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ellervee, Peeter
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hemani, Ahmed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Öberg, Johnny
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Hardware/software partitioning and minimizing memory interface traffic1994Inngår i: Proceedings of the conference on European design automation 1994, 1994, s. 226-231Konferansepaper (Fagfellevurdert)
  • 197.
    Jantsch, Axel
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Special Issue on Networks on Chip - guest editor’s introduction2004Inngår i: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 50, nr 2-3, s. 61-63Artikkel i tidsskrift (Annet vitenskapelig)
  • 198.
    Javed, Aqsa
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.
    Ejaz, Asma
    ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan.
    Mehak, Sumrin
    ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan.
    Amin, Yasar
    KTH. ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan.
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar. Department of Information Technology, TUCS, University of Turku, Turku, 20520, Finland.
    Miniaturized cross-lines rectangular ring-shaped flexible multiband antenna2019Inngår i: Applied Computational Electromagnetics Society Journal, ISSN 1054-4887, Vol. 34, nr 5, s. 625-630Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A compact, flexible antenna for wireless applications, i.e., WLAN/WiMAX/Wi-Fi, UMTS2100, C-Band, and DSRC is presented. The quad-band antenna is designed and analyzed in terms of efficiency, gain, radiation pattern, return loss, and VSWR. The optimized design consists of a CPW fed rectangular ring patch with the semi-circular ground. The cross-lines and the semicircular ground is investigated to ascertain the multiband effect. A concept of inset feed mechanism is also interpolated to enhance impedance matching. The framed antenna is examined under the bent condition as well. The reported work is an apt candidate for the proposed applications because of its high efficiency of 95% with a peak gain of 3.22 dBi along with VSWR less than 2. With stable radiation pattern and bandwidth, there is a justified concurrence between simulated and measured results.

  • 199. Javed, Nimra
    et al.
    Habib, Ayesha
    Amin, Yasar
    Loo, Jonathan
    Akram, Adeel
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Directly Printable Moisture Sensor Tag for Intelligent Packaging2016Inngår i: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 16, nr 16, s. 6147-6148Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A compact, flexible 24-b dual-polarized chip-less radio frequency identification tag with a size of 20.6mm x 19.9mm is realized. The tag structure is optimized and analyzed for Taconic, Kapton HN and organic substrate. The prototype fabricated on HP photopaper with silver nanoparticles-based conductive ink is exhibiting a behavior of moisture sensor. The proposed moisture sensor tag has a bandwidth of 13.5GHz. The direct printability of moisture sensor tag makes it suitable for intelligent packaging and various low-cost applications.

  • 200. Javeda, Nimra
    et al.
    Habib, Ayesha
    Akram, Adeel
    Amin, Yasar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    16-bit frequency signatured directly printable tag for organic electronics2016Inngår i: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 13, nr 11, artikkel-id 20160406Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A compact 16-bit chipless RFID moisture sensor tag with a size of 13.2 x 19.6mm(2) is designed, fabricated and analyzed. The presented moisture sensor tag is realized on a paper substrate with silver nano particle based ink patches as conducting material. The frequency band of operation is 0.5 to 14 GHz having an overall bandwidth of 13.5 GHz. It is loaded with slots of different lengths and widths, etched on the conductive material. The tag exhibits stable sensing characteristic towards moisture in the real environment. The flexible, sensitive and environmental friendly nature of the proposed tag makes it suitable for wider, low-cost and organic electronics applications.

1234567 151 - 200 of 538
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