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  • 201.
    Carbone, Paris
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Fóra, Gyula
    CSL Computer Systems Laboratory, SICS Swedish Institute of Compute Science.
    Ewen, Stephan
    Data Artisans GmbH.
    Haridi, Seif
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Tzoumas, Kostas
    Data Artisans GmbH.
    Lightweight Asynchronous Snapshots for Distributed Dataflows2015Report (Other academic)
    Abstract [en]

    Distributed stateful stream processing enables the deployment and execution of large scale continuous computations in the cloud, targeting both low latency and high throughput. One of the most fundamental challenges of this paradigm is providing processing guarantees under potential failures. Existing approaches rely on periodic global state snapshots that can be used for failure recovery. Those approaches suffer from two main drawbacks. First, they often stall the overall computation which impacts ingestion. Second, they eagerly persist all records in transit along with the operation states which results in larger snapshots than required. In this work we propose Asynchronous Barrier Snapshotting (ABS), a lightweight algorithm suited for modern dataflow execution engines that minimises space requirements. ABS persists only operator states on acyclic execution topologies while keeping a minimal record log on cyclic dataflows. We implemented ABS on Apache Flink, a distributed analytics engine that supports stateful stream processing. Our evaluation shows that our algorithm does not have a heavy impact on the execution, maintaining linear scalability and performing well with frequent snapshots. 

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  • 202.
    Carbone, Paris
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Gévay, G. E.
    Hermann, G.
    Katsifodimos, A.
    Soto, J.
    Markl, V.
    Haridi, Seif
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Large-scale data stream processing systems2017In: Handbook of Big Data Technologies, Springer International Publishing , 2017, p. 219-260Chapter in book (Other academic)
    Abstract [en]

    In our data-centric society, online services, decision making, and other aspects are increasingly becoming heavily dependent on trends and patterns extracted from data. A broad class of societal-scale data management problems requires system support for processing unbounded data with low latency and high throughput. Large-scale data stream processing systems perceive data as infinite streams and are designed to satisfy such requirements. They have further evolved substantially both in terms of expressive programming model support and also efficient and durable runtime execution on commodity clusters. Expressive programming models offer convenient ways to declare continuous data properties and applied computations, while hiding details on how these data streams are physically processed and orchestrated in a distributed environment. Execution engines provide a runtime for such models further allowing for scalable yet durable execution of any declared computation. In this chapter we introduce the major design aspects of large scale data stream processing systems, covering programming model abstraction levels and runtime concerns. We then present a detailed case study on stateful stream processing with Apache Flink, an open-source stream processor that is used for a wide variety of processing tasks. Finally, we address the main challenges of disruptive applications that large-scale data streaming enables from a systemic point of view.

  • 203.
    Carbone, Paris
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Vlassov, Vladimir
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Auto-Scoring of Personalised News in the Real-Time Web: Challenges, Overview and Evaluation of the State-of-the-Art Solutions2015Conference paper (Refereed)
    Abstract [en]

    The problem of automated personalised news recommendation, often referred as auto-scoring has attracted substantial research throughout the last decade in multiple domains such as data mining and machine learning, computer systems, e commerce and sociology. A typical "recommender systems" approach to solving this problem usually adopts content-based scoring, collaborative filtering or more often a hybrid approach. Due to their special nature, news articles introduce further challenges and constraints to conventional item recommendation problems, characterised by short lifetime and rapid popularity trends. In this survey, we provide an overview of the challenges and current solutions in news personalisation and ranking from both an algorithmic and system design perspective, and present our evaluation of the most representative scoring algorithms while also exploring the benefits of using a hybrid approach. Our evaluation is based on a real-life case study in news recommendations.

  • 204.
    Carlsson, Jonas
    KTH, School of Computer Science and Communication (CSC).
    Improving performance on base stations by improving spatial locality in caches2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    For real-time systems like base stations there are time constraints for them to operate smoothly. This means that things like caches which brings stochastic variables will most likely not be able to be added. Ericsson however want to add caches both for the possible performance gains but also for the automatic loading of functions. As it stands, Ericsson can only use direct mapped caches and the chance for cache misses on the base stations is large. We have tried to see if randomness can be decreased by placing code in the common memory. The new placement is based on logs from earlier runs. There are two different heuristic approaches to do this. The first was developed by Pettis \& Hansen and the second was developed by Gloy \& Smith. We also discuss a third alternative by Hashemi, Kaeli \& Calder (HKC) which was not tested. However the results show there are no practical improvements by using code placement strategies.

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  • 205.
    CARRA, Florian
    KTH, School of Computer Science and Communication (CSC).
    Recommender System for Retail Industry: Ease customers’ purchase by generating personal purchase carts consisting of relevant and original products2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In this study we explore the problem of purchase cart recommendationin the field of retail. How can we push the right customize purchase cart that would consider both habits and serendipity constraints? Recommender Systems application is widely restricted to Internet services providers: movie recommendation, e-commerce, search engine. We brought algorithmic and technological breakthroughs to outdated retail systems while keeping in mind its own specificities: purchase cart rather than single products, restricted interactions between customers and products. After collecting ingenious recommendations methods, we defined two major directions - the correctness and the serendipity - that would serve as discriminant aspects to compare multiple solutions we implemented. We expect our solutions to have beneficial impacts on customers, gaining time and open-mindedness, and gradually obliterate the separation between supermarkets and e-commerce platforms as far as customized experience is concerned.

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  • 206.
    Carrera Jeri, Patrick
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH).
    Risk Stratification of Endometriosis through Machine Learning using Lifestyle Data: An Extensive Analysis on Lifestyle Data to Reveal Patterns in People with Endometriosis2023Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Endometriosis affect 11% of women of reproductive years worldwide. The project made use of lifestyle factors coming from the Lucy application. The Pearson correlation test was used to find linear correlation between endometriosis and lifestyle factors, while different machine learning models and logistic regression was used for finding non-linear correlations. The strongest linear correlation found (-0.23) was irregular menstruation however, the score does suggest a weak linear correlation. Decision Tree, Gradient boosted DT, XgBoost, Random Forest, and Logistic regression were usedto find patterns within the dataset. Risk stratification results proved to be unreliable. Decision Tree and its variants show strong evidence of correlation between endometriosis and the following features: weight, irregular menstruation, menstruation length, height, cycle length, irregular cycle, age, pregnancy, and daily symptoms. Additional analysis on those features could give more insight on what may be correlated as well as cause endometriosis.

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  • 207.
    Castañeda Lozano, Roberto
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Constraint Programming for Random Testing of a Trading System2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Financial markets use complex computer trading systems whose failures can cause serious economic damage, making reliability a major concern. Automated random testing has been shown to be useful in finding defects in these systems, but its inherent test oracle problem (automatic generation of the expected system output) is a drawback that has typically prevented its application on a larger scale.

    Two main tasks have been carried out in this thesis as a solution to the test oracle problem. First, an independent model of a real trading system based on constraint programming, a method for solving combinatorial problems, has been created. Then, the model has been integrated as a true test oracle in automated random tests. The test oracle maintains the expected state of an order book throughout a sequence of random trade order actions, and provides the expected output of every auction triggered in the order book by generating a corresponding constraint program that is solved with the aid of a constraint programming system.

    Constraint programming has allowed the development of an inexpensive, yet reliable test oracle. In 500 random test cases, the test oracle has detected two system failures. These failures correspond to defects that had been present for several years without being discovered neither by less complete oracles nor by the application of more systematic testing approaches.

    The main contributions of this thesis are: (1) empirical evidence of both the suitability of applying constraint programming to solve the test oracle problem and the effectiveness of true test oracles in random testing, and (2) a first attempt, as far as the author is aware, to model a non-theoretical continuous double auction using constraint programming.

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    TRITA-ICT-EX-2010:69.pdf
  • 208.
    Castañeda Lozano, Roberto
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS. RISE SICS (Swedish Institute of Computer Science).
    Constraint-Based Register Allocation and Instruction Scheduling2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to improve latency or throughput) are central compiler problems. This dissertation proposes a combinatorial optimization approach to these problems that delivers optimal solutions according to a model, captures trade-offs between conflicting decisions, accommodates processor-specific features, and handles different optimization criteria.

    The use of constraint programming and a novel program representation enables a compact model of register allocation and instruction scheduling. The model captures the complete set of global register allocation subproblems (spilling, assignment, live range splitting, coalescing, load-store optimization, multi-allocation, register packing, and rematerialization) as well as additional subproblems that handle processor-specific features beyond the usual scope of conventional compilers.

    The approach is implemented in Unison, an open-source tool used in industry and research that complements the state-of-the-art LLVM compiler. Unison applies general and problem-specific constraint solving methods to scale to medium-sized functions, solving functions of up to 647 instructions optimally and improving functions of up to 874 instructions. The approach is evaluated experimentally using different processors (Hexagon, ARM and MIPS), benchmark suites (MediaBench and SPEC CPU2006), and optimization criteria (speed and code size reduction). The results show that Unison generates code of slightly to significantly better quality than LLVM, depending on the characteristics of the targeted processor (1% to 9.3% mean estimated speedup; 0.8% to 3.9% mean code size reduction). Additional experiments for Hexagon show that its estimated speedup has a strong monotonic relationship to the actual execution speedup, resulting in a mean speedup of 5.4% across MediaBench applications.

    The approach contributed by this dissertation is the first of its kind that is practical (it captures the complete set of subproblems, scales to medium-sized functions, and generates executable code) and effective (it generates better code than the LLVM compiler, fulfilling the promise of combinatorial optimization). It can be applied to trade compilation time for code quality beyond the usual optimization levels, explore and exploit processor-specific features, and identify improvement opportunities in conventional compilers.

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  • 209.
    Castañeda Lozano, Roberto
    et al.
    SICS (Swedish Institute of Computer Science), Sweden.
    Carlsson, Mats
    SICS (Swedish Institute of Computer Science), Sweden.
    Drejhammar, Frej
    SICS (Swedish Institute of Computer Science), Sweden.
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science), Sweden.
    Constraint-Based Register Allocation and Instruction Scheduling2012In: Principles and Practice of Constraint Programming: 18th International Conference, CP 2012, Québec City, QC, Canada, October 8-12, 2012. Proceedings / [ed] Michela Milano, Springer, 2012, p. 750-766Conference paper (Refereed)
    Abstract [en]

    This paper introduces a constraint model and solving techniques for code generation in a compiler back-end. It contributes a new model for global register allocation that combines several advanced aspects: multiple register banks (subsuming spilling to memory), coalescing, and packing. The model is extended to include instruction scheduling and bundling. The paper introduces a decomposition scheme exploiting the underlying program structure and exhibiting robust behavior for functions with thousands of instructions. Evaluation shows that code quality is on par with LLVM, a state-of-the-art compiler infrastructure.

    The paper makes important contributions to the applicability of constraint programming as well as compiler construction: essential concepts are unified in a high-level model that can be solved by readily available modern solvers. This is a significant step towards basing code generation entirely on a high-level model and by this facilitates the construction of correct, simple, flexible, robust, and high-quality code generators.

  • 210.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS. RISE SICS (Swedish Institute of Computer Science).
    Carlsson, Mats
    RISE SICS (Swedish Institute of Computer Science).
    Hjort Blindell, Gabriel
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS.
    Schulte, Christian
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS.
    Combinatorial Register Allocation and Instruction Scheduling2018Report (Other academic)
    Abstract [en]

    This paper introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems. Combinatorial optimization has the potential to solve these problems optimally and to exploit processor-specific features readily. Our approach is the first to leverage this potential in practice: it captures the complete set of program transformations used in state-of-the-art compilers, scales to medium-sized functions of up to 1000 instructions, and generates executable code. This level of practicality is reached by using constraint programming, a particularly suitable combinatorial optimization technique. Unison, the implementation of our approach, is open source, used in industry, and integrated with the LLVM toolchain.

    An extensive evaluation of estimated speed, code size, and scalability confirms that Unison generates better code than LLVM while scaling to medium-sized functions. The evaluation uses systematically selected benchmarks from MediaBench and SPEC CPU2006 and different processor architectures (Hexagon, ARM, MIPS). Mean estimated speedup ranges from 1% to 9.3% and mean code size reduction ranges from 0.8% to 3.9% for the different architectures. Executing the generated code on Hexagon confirms that the estimated speedup indeed results in actual speedup. Given a fixed time limit, Unison solves optimally functions of up to 647 instructions, delivers improved solutions for functions of up to 874 instructions, and achieves more than 85% of the potential speed for 90% of the functions on Hexagon.

    The results in this paper show that our combinatorial approach can be used in practice to trade compilation time for code quality beyond the usual compiler optimization levels, fully exploit processor-specific features, and identify improvement opportunities in existing heuristic algorithms.

  • 211.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science).
    Carlsson, Mats
    SICS (Swedish Institute of Computer Science).
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Register allocation and instruction scheduling in Unison2016In: Proceedings of CC 2016: The 25th International Conference on Compiler Construction, Association for Computing Machinery (ACM), 2016, p. 263-264Conference paper (Refereed)
    Abstract [en]

    This paper describes Unison, a simple, flexible, and potentially optimal software tool that performs register allocation and instruction scheduling in integration using combinatorial optimization. The tool can be used as an alternative or as a complement to traditional approaches, which are fast but complex and suboptimal. Unison is most suitable whenever high-quality code is required and longer compilation times can be tolerated (such as in embedded systems or library releases), or the targeted processors are so irregular that traditional compilers fail to generate satisfactory code.

  • 212.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science) and KTH (Royal Institute of Technology).
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Carlsson, Mats
    SICS (Swedish Institute of Computer Science).
    Drejhammar, Frej
    SICS (Swedish Institute of Computer Science).
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Constraint-based Code Generation2013In: Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, M-SCOPES 2013, Association for Computing Machinery (ACM), 2013, p. 93-95Conference paper (Refereed)
    Abstract [en]

    Compiler back-ends generate assembly code by solving three main tasks: instruction selection, register allocation and instruction scheduling. We introduce constraint models and solving techniques for these code generation tasks and describe how the models can be composed to generate code in unison. The use of constraint programming, a technique to model and solve combinatorial problems, makes code generation simple, flexible, robust and potentially optimal.

  • 213.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science) and KTH (Royal Institute of Technology).
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Survey on Combinatorial Register Allocation and Instruction Scheduling2014Report (Other academic)
    Abstract [en]

    Register allocation and instruction scheduling are two central compiler back-end problems that are critical for quality. In the last two decades, combinatorial optimization has emerged as an alternative approach to traditional, heuristic algorithms for these problems. Combinatorial approaches are generally slower but more flexible than their heuristic counterparts and have the potential to generate optimal code. This paper surveys existing literature on combinatorial register allocation and instruction scheduling. The survey covers approaches that solve each problem in isolation as well as approaches that integrate both problems. The latter have the potential to generate code that is globally optimal by capturing the trade-off between conflicting register allocation and instruction scheduling decisions.

  • 214.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS. RISE SICS (Swedish Institute of Computer Science).
    Schulte, Christian
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS.
    Survey on Combinatorial Register Allocation and Instruction Scheduling2018In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341Article in journal (Refereed)
    Abstract [en]

    Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the last three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time.

    This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization.

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  • 215.
    Catarci, Tiziana
    et al.
    Sapienza University of Rome.
    Ferro, Nicola
    University of Padua.
    Forner, Pamela
    CELCT.
    Hiemstra, Djoerd
    University of Twente.
    Karlgren, Jussi
    KTH, School of Computer Science and Communication (CSC), Theoretical Computer Science, TCS. Gavagai.
    Peñas, Anselmo
    UNED.
    Santucci, Guiseppe
    Sapienza University of Rome.
    Womser-Hacker, Christa
    University of Hildesheim.
    CLEF 2012: Information Access Evaluation meetsMultilinguality, Multimodality, and VisualAnalytics2012In: SIGIR Forum, ISSN 0163-5840, E-ISSN 1558-0229, Vol. 46, no 2, p. 29-33Article in journal (Refereed)
  • 216.
    Ceccato, Vania
    et al.
    KTH, School of Architecture and the Built Environment (ABE), Urban Planning and Environment, Urban and Regional Studies.
    Solymosi, Reka
    Univ Manchester, Sch Social Sci, Manchester, Lancs, England..
    Müller, Oskar
    KTH, School of Architecture and the Built Environment (ABE), Urban Planning and Environment.
    The Use of Twitter by Police Officers in Urban and Rural Contexts in Sweden2021In: International Criminal Justice Review, ISSN 1057-5677, E-ISSN 1556-3855, Vol. 31, no 4, p. 456-476, article id 10575677211041926Article in journal (Refereed)
    Abstract [en]

    The aim of this article is to investigate the nature of information sharing via Twitter by police officers. We examine the content of Tweets in urban and rural contexts using a sample of 20 police-related Twitter accounts, comparing official and personal accounts active in Southern Sweden. Exploratory data analysis and in-depth content analysis of a sample of Tweets compose the underlying methodology. We find a distinct pattern of consistency in the content of the information shared via the official police accounts compared to the personal accounts, regardless of if they are from urban or rural areas. However, some urban-rural differences were observed between official and personal accounts regarding public engagement, operationalized as likes and Retweets. The study calls for a discussion of new models of police engagement using social media by a society that is increasingly shaped by the internet.

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  • 217.
    Chamberlain, Roger
    et al.
    Washington University, St. Louis, MO, United States.
    Taha, Walid
    Halmstad University, Halmstad, Sweden.
    Törngren, Martin
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems. KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Preface2019In: Cyber Physical Systems. Design, Modeling, and Evaluation: 7th International Workshop, CyPhy 2017, Seoul, South Korea, October 15-20, 2017, Revised Selected Papers, Springer Verlag , 2019Conference paper (Refereed)
  • 218.
    Champati, Jaya Prakash
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Information Science and Engineering.
    Liang, B.
    Single Restart with Time Stamps for Parallel Task Processing with Known and Unknown Processors2020In: IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, E-ISSN 1558-2183, Vol. 31, no 1, p. 187-200, article id 8765409Article in journal (Refereed)
    Abstract [en]

    We study the problem of scheduling nn tasks on m+m^{\prime }m+m' parallel processors, where the processing times on mm processors are known while those on the remaining m^{\prime }m' processors are not known a priori. This semi-online model is an abstraction of certain heterogeneous computing systems, e.g., with the mm known processors representing local CPU cores and the unknown processors representing remote servers with uncertain availability of computing cycles. Our objective is to minimize the makespan of all tasks. We initially focus on the case m^{\prime }=1m'=1 and propose a semi-online algorithm termed Single Restart with Time Stamps (SRTS), which has time complexity O(n \log n)O(nlogn). We derive its competitive ratio in comparison with the optimal offline solution. If the unknown processing times are deterministic, the competitive ratio of SRTS is shown to be either always constant or asymptotically constant in practice, respectively in cases where the processing times are independent and dependent on mm. A similar result is obtained when the unknown processing times are random. Furthermore, extending the ideas of SRTS, we propose a heuristic algorithm termed SRTS-Multiple (SRTS-M) for the case m^{\prime }>1m'>1. Finally, where tasks arrive dynamically with unknown arrival times, we extend SRTS to Dynamic SRTS (DSRTS) and find its competitive ratio. Besides the proven competitive ratios, simulation results further suggest that SRTS and SRTS-M give superior performance on average over randomly generated task processing times, substantially reducing the makespan over the best known alternatives. Interestingly, the performance gain is more significant for task processing times sampled from heavy-tailed distributions.

  • 219.
    Champati, Jaya Prakash
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Information Science and Engineering.
    Mamduhi, Mohammad H.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Decision and Control Systems (Automatic Control).
    Johansson, Karl H.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Decision and Control Systems (Automatic Control).
    Gross, James
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Information Science and Engineering.
    Performance Characterization Using AoI in a Single-loop Networked Control System2019In: IEEE INFOCOM 2019 - IEEE Conference on Computer Communications Workshops, INFOCOM Workshops 2019, IEEE , 2019, p. 197-203Conference paper (Refereed)
    Abstract [en]

    The joint design of control and communication scheduling in a Networked Control System (NCS) is known to be a hard problem. Several research works have successfully designed optimal sampling and/or control strategies under simplified communication models, where transmission delays/times are negligible or fixed. However, considering sophisticated communication models, with random transmission times, result in highly coupled and difficult-to-solve optimal design problems due to the parameter inter-dependencies between estimation/control and communication layers. To tackle this problem, in this work, we investigate the applicability of Age-of-Information (AoI) for solving control/estimation problems in an NCS under i.i.d. transmission times. Our motivation for this investigation stems from the following facts: 1) recent results indicate that AoI can be tackled under relatively sophisticated communication models, and 2) a lower AoI in an NCS may result in a lower estimation/control cost. We study a joint optimization of sampling and scheduling for a single-loop stochastic LTI networked system with the objective of minimizing the time-average squared norm of the estimation error. We first show that, under mild assumptions on information structure the optimal control policy can be designed independently from the sampling and scheduling policies. We then derive a key result that minimizing the estimation error is equivalent to minimizing a non-negative and non-decreasing function of AoI. The parameters of this function include the LTI matrix and the covariance of exogenous noise in the LTI system. Noting that the formulated problem is a stochastic combinatorial optimization problem and is hard to solve, we resort to heuristic algorithms by extending existing algorithms in the AoI literature. We also identify a class of LTI system dynamics for which minimizing the estimation error is equivalent to minimizing the expected AoI.

  • 220.
    Champati, Jaya Prakash
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Information Science and Engineering. IMDEA Networks Inst, Madrid 28918, Spain..
    Skoglund, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Information Science and Engineering.
    Jansson, Magnus
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Information Science and Engineering.
    Gross, James
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Information Science and Engineering.
    Detecting State Transitions of a Markov Source: Sampling Frequency and Age Trade-off2022In: IEEE Transactions on Communications, ISSN 0090-6778, E-ISSN 1558-0857, Vol. 70, no 5, p. 3081-3095Article in journal (Refereed)
    Abstract [en]

    We consider a finite-state Discrete-Time Markov Chain (DTMC) source that can be sampled for detecting the events when the DTMC transits to a new state. Our goal is to study the trade-off between sampling frequency and staleness in detecting the events. We argue that, for the problem at hand, using Age of Information (AoI) for quantifying the staleness of a sample is conservative and therefore, study another freshness metric age penalty, which is defined as the time elapsed since the first transition out of the most recently observed state. We study two optimization problems: minimize average age penalty subject to an average sampling frequency constraint, and minimize average sampling frequency subject to an average age penalty constraint; both are Constrained Markov Decision Problems. We solve them using the Lagrangian MDP approach, where we also provide structural results that reduce the search space. Our numerical results demonstrate that the computed Markov policies not only outperform optimal periodic sampling policies, but also achieve sampling frequencies close to or lower than that of an optimal clairvoyant (non-causal) sampling policy, if a small age penalty is allowed.

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  • 221.
    Charalambous, Themistoklis
    et al.
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Kalyviannaki, Evangelia
    City University London.
    Hadjicostis, Christoforos N.
    Electrical and Computer Engineering Department, University of Cyprus.
    Johansson, Mikael
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Distributed Offline Load Balancing in MapReduce Networks2013In: 2013 IEEE 52ND ANNUAL CONFERENCE ON DECISION AND CONTROL (CDC), IEEE conference proceedings, 2013, p. 835-840Conference paper (Refereed)
    Abstract [en]

    In this paper we address the problem of balancing the processing load of MapReduce tasks running on heterogeneous clusters, i.e., clusters with different capacities and update cycles. We present a fully decentralized algorithm, based on ratio consensus, where each mapper decides the amount of workload data to handle for a single user job using only job specific local information, i.e., information that can be collected from directly connected neighboring mappers, regarding their current workload and capacity. In contrast to other algorithms in the literature, the proposed algorithm can be deployed in heterogeneous networks and can operate asynchronously in both directed and undirected communication topologies. The performance of the proposed algorithm is demonstrated via simulation experiments on large-scale strongly connected topologies. 

  • 222.
    Chen, Chen
    et al.
    Middleware System Research Group, University of Toronto.
    Tock, Yoav
    IBM Research - Haifa.
    Girdzijauskas, Sarunas
    KTH, School of Electrical Engineering and Computer Science (EECS).
    BeaConvey: Co-Design of Overlay and Routing for Topic-basedPublish/Subscribe on Small-World Networks2018Conference paper (Refereed)
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  • 223.
    Chen, DeJiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    IMBSA 2017: Model-Based Safety and Assessment2017In: Model-Based Safety and Assessment - 5th International Symposium, Trento, Italy, September 11–13, 2017 / [ed] Marco Bozzano, Yiannis Papadopoulos, Springer, 2017, Vol. LNCS 10437, p. 227-240Conference paper (Refereed)
    Abstract [en]

    Modern automotive vehicles represent one category of CPS (Cyber-Physical Systems) that are inherently time- and safety-critical. To justify the actions for quality-of-service adaptation and safety assurance, it is fundamental to perceive the uncertainties of system components in operation, which are caused by emergent properties, design or operation anomalies. From an industrial point of view, a further challenge is related to the usages of generic purpose COTS (Commercial-Off-The-Shelf) components, which are separately developed and evolved, often not sufficiently verified and validated for specific automotive contexts. While introducing additional uncertainties in regard to the overall system performance and safety, the adoption of COTS components constitutes a necessary means for effective product evolution and innovation. Accordingly, we propose in this paper a novel approach that aims to enable advanced operation monitoring and self-assessment in regard to operational uncertainties and thereby automated performance and safety awareness. The emphasis is on the integration of several modeling technologies, including the domain-specific modeling framework EAST-ADL, the A-G contract theory and Hidden Markov Model (HMM). In particular, we also present some initial concepts in regard to the usage performance and safety awareness for quality-of-service adaptation and dynamic risk mitigation.

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  • 224. Chen, K. -CJ.
    et al.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Routing algorithm design for power- and temperature-aware NoCs2022In: Advances in Computers, Elsevier BV , 2022, p. 117-150Conference paper (Refereed)
    Abstract [en]

    The Network-on-Chip (NoC) interconnection is a popular way to build up contemporary large-scale multi-processor System-on-Chip (MPSoC) systems. However, due to the high integration density with high operation frequency, the larger power density leads to serious temperature problems. The thermal issue limits the performance and results in higher leakage power and lower system reliability. The thermal and power issues become worsen in the modern 3D stacking NoC structure and become the primary design challenge. In this chapter, we first investigate the correlation between power and temperature in NoC systems and introduce a thermal model for such systems. With this thermal model, we introduce novel routing design methodologies for power- and temperature-aware NoCs by using Game theory and reinforcement learning.

  • 225. Chen, Kun-Chih (jimmy)
    et al.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Wang, Ting-Yi
    Yang, Yuch-Chi
    Liao, Yuan-Hao
    A NoC-based simulator for design and evaluation of deep neural networks2020In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 77, article id 103145Article in journal (Refereed)
    Abstract [en]

    The astonishing development in the field of artificial neural networks (ANN) has brought significant advancement in many application domains, such as pattern recognition, image classification, and computer vision. ANN imitates neuron behaviors and makes a decision or prediction by learning patterns and features from the given data set. To reach higher accuracies, neural networks are getting deeper, and consequently, the computation and storage demands on hardware platforms are steadily increasing. In addition, the massive data communication among neurons makes the interconnection more complex and challenging. To overcome these challenges, ASIC-based DNN accelerators are being designed which usually incorporate customized processing elements, fixed interconnection, and large off-chip memory storage. As a result, DNN computation involves large memory accesses due to frequent load/off-loading data, which significantly increases the energy consumption and latency. Also, the rigid architecture and interconnection among processing elements limit the efficiency of the platform to specific applications. In recent years, Network-on-Chip-based (NoC-based) DNN becomes an emerging design paradigm because the NoC interconnection can help to reduce the off-chip memory accesses while offers better scalability and flexibility. To evaluate the NoC-based DNN in the early design stage, we introduce a cycle-accurate NoC-based DNN simulator, called DNNoC-sim. To support various operations such as convolution and pooling in the modern DNN models, we first propose a DNN flattening technique to convert diverse DNN operation into MAC-like operations. In addition, we propose a DNN slicing method to evaluate the large-scale DNN models on a resource-constraint NoC platform. The evaluation results show a significant reduction in the off-chip memory accesses compared to the state-of-the-art DNN model. We also analyze the performance and discuss the trade-off between different design parameters. 

  • 226.
    Chen, Kun-Chih
    et al.
    Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Kaohsiung 804, Taiwan..
    Tsai, Cheng-Kang
    Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Kaohsiung 804, Taiwan..
    Liao, Yi-Sheng
    Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Kaohsiung 804, Taiwan..
    Xu, Han-Bo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    A Lego-Based Neural Network Design Methodology With Flexible NoC2021In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, ISSN 2156-3357, E-ISSN 2156-3365, Vol. 11, no 4, p. 711-724Article in journal (Refereed)
    Abstract [en]

    Deep Neural Networks (DNNs) have shown superiority in solving the problems of classification and recognition in recent years. However, DNN hardware implementation is challenging due to the high computational complexity and diverse dataflow in different DNN models. 'lb mitigate this design challenge, a large body of research has focused on accelerating specific DNN models or layers and proposed dedicated designs. However, dedicated designs for specific DNN models or layers limit the design flexibility. In this work, we take advantage of the similarity among different DNN models and propose a novel Lego-based Deep Neural Network on a Chip (DNNoC) design methodology. We work on common neural computing units (e.g., multiply-accumulation and pooling) and create some neuron computing units called NeuLego processing elements (NeuLego(PE)(s)). These NeuLego(PE)(s) are then interconnected using a flexible Network-on-Chip (NoC), allowing to construct different DNN models. To support large-scale DNN models, we enhance the reusability of each NeuLego(PE) by proposing a Lego placement method. The proposed design methodology allows leveraging different DNN model implementations, helping to reduce implementation cost and time-to-market. Compared with the conventional approaches, the proposed approach can improve the average throughput by 2,802% for given DNN models. Besides, the corresponding hardware is implemented to validate the proposed design methodology, showing on average 12,523% hardware efficiency improvement by considering the throughput and area overhead simultaneously.

  • 227. Chen, S.
    et al.
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Hardware acceleration of multilayer perceptron based on inter-layer optimization2019In: Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019, Institute of Electrical and Electronics Engineers Inc. , 2019, p. 164-172Conference paper (Refereed)
    Abstract [en]

    Multilayer Perceptron (MLP) is used in a broad range of applications. Hardware acceleration of MLP is one most promising way to provide better performance-energy efficiency. Previous works focused on the intra-layer optimization and layer-after-layer processing, while leaving the inter-layer optimization never studied. In this paper, we propose hardware acceleration of MLPs based on inter-layer optimization which allows us to overlap the execution of MLP layers. First we describe the inter-layer optimization from software and mathematical perspectives. Then, a reference Two-Neuron architecture which is efficient to support the inter-layer optimization is proposed and implemented. Discussions about area cost, performance and energy consumption are carried out to explore the scalability of the Two-Neuron architecture. Results show that the proposed MLP design optimized across layers achieves better performance and energy efficiency than the conventional intra-layer optimized designs. As such, the inter-layer optimization provides another possible direction other than the intra-layer optimization to gain further performance and energy improvements for the hardware acceleration of MLPs.

  • 228. Chen, X.
    et al.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Li, Y.
    Jantsch, A.
    Zhao, Xueqian
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Chen, S.
    Guo, Y.
    Liu, Z.
    Lu, J.
    Wan, J.
    Sun, S.
    Chen, H.
    Achieving memory access equalization via round-trip routing latency prediction in 3D many-core NoCs2015In: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, IEEE , 2015, p. 398-403Conference paper (Refereed)
    Abstract [en]

    3D many-core NoCs are emerging architectures for future high-performance single chips due to its integration of many processor cores and memories by stacking multiple layers. In such architecture, because processor cores and memories reside in different locations (center, corner, edge, etc.), memory accesses behave differently due to their different communication distances, and the performance (latency) gap of different memory accesses becomes larger as the network size is scaled up. This phenomenon may lead to very high latencies suffered from by some memory accesses, thus degrading the system performance. To achieve high performance, it is crucial to reduce the number of memory accesses with very high latencies. However, this should be done with care since shortening the latency of one memory access can worsen the latency of another as a result of shared network resources. Therefore, the goal should focus on narrowing the latency difference of memory accesses. In the paper, we address the goal by proposing to prioritize the memory access packets based on predicting the round-trip routing latencies of memory accesses. The communication distance and the number of the occupied items in the buffers in the remaining routing path are used to predict the round-trip latency of a memory access. The predicted round-trip routing latency is used as the base to arbitrate the memory access packets so that the memory access with potential high latency can be transferred as early and fast as possible, thus equalizing the memory access latencies as much as possible. Experiments with varied network sizes and packet injection rates prove that our approach can achieve the goal of memory access equalization and outperforms the classic round-robin arbitration in terms of maximum latency, average latency, and LSD1. In the experiments, the maximum improvement of the maximum latency, the average latency and the LSD are 80%, 14%, and 45% respectively.

  • 229.
    Chen, Xiaowen
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Efficient Memory Access and Synchronization in NoC-based Many-core Processors2019Doctoral thesis, monograph (Other academic)
    Abstract [en]

    In NoC-based many-core processors, memory subsystem and synchronization mechanism are always the two important design aspects, since mining parallelism and pursuing higher performance require not only optimized memory management but also efficient synchronization mechanism. Therefore, we are motivated to research on efficient memory access and synchronization in three topics, namely, efficient on-chip memory organization, fair shared memory access, and efficient many-core synchronization.

    One major way of optimizing the memory performance is constructing a suitable and efficient memory organization. A distributed memory organization is more suitable to NoC-based many-core processors, since it features good scalability. We envision that it is essential to support Distributed Shared Memory (DSM) because of the huge amount of legacy code and easy programming. Therefore, we first adopt the microcoded approach to address DSM issues, aiming for hardware performance but maintaining the flexibility of programs. Second, we further optimize the DSM performance by reducing the virtual-to-physical address translation overhead. In addition to the general-purpose memory organization such as DSM, there exists special-purpose memory organization to optimize the performance of application-specific memory access. We choose Fast Fourier Transform (FFT) as the target application, and propose a multi-bank data memory specialized for FFT computation.

    In 3D NoC-based many-core processors, because processor cores and memories reside in different locations (center, corner, edge, etc.) of different layers, memory accesses behave differently due to their different communication distances. As the network size increases, the communication distance difference of memory accesses becomes larger, resulting in unfair memory access performance among different processor cores. This unfair memory access phenomenon may lead to high latencies of some memory accesses, thus negatively affecting the overall system performance. Therefore, we are motivated to study on-chip memory and DRAM access fairness in 3D NoC-based many-core processors through narrowing the round-trip latency difference of memory accesses as well as reducing the maximum memory access latency.

    Barrier synchronization is used to synchronize the execution of parallel processor cores. Conventional barrier synchronization approaches such as master-slave, all-to-all, tree-based, and butterfly are algorithm oriented. As many processor cores are networked on a single chip, contended synchronization requests may cause large performance penalty. Motivated by this, different from the algorithm-based approaches, we choose another direction (i.e., exploiting efficient communication) to address the barrier synchronization problem. We propose cooperative communication as a means and combine it with the master-slave algorithm and the all-to-all algorithm to achieve efficient many-core barrier synchronization. Besides, a multi-FPGA implementation case study of fast many-core barrier synchronization is conducted.

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  • 230.
    Chen, Yizhi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Nevarez, Yarib
    University of Bremen, Institute of Electrodynamics and Microelectronics (ITEM.ids), Bremen, Germany.
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Garcia-Ortiz, Alberto
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Accelerating Non-Negative Matrix Factorization on Embedded FPGA with Hybrid Logarithmic Dot-Product Approximation2022In: Proceedings: 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022, Institute of Electrical and Electronics Engineers (IEEE) , 2022, p. 239-246Conference paper (Refereed)
    Abstract [en]

    Non-negative matrix factorization (NMF) is an ef-fective method for dimensionality reduction and sparse decom-position. This method has been of great interest to the scien-tific community in applications including signal processing, data mining, compression, and pattern recognition. However, NMF implies elevated computational costs in terms of performance and energy consumption, which is inadequate for embedded applications. To overcome this limitation, we implement the vector dot-product with hybrid logarithmic approximation as a hardware optimization approach. This technique accelerates floating-point computation, reduces energy consumption, and preserves accuracy. To demonstrate our approach, we employ a design exploration flow using high-level synthesis on an embedded FPGA. Compared with software solutions on ARM CPU, this hardware implementation accelerates the overall computation to decompose matrix by 5.597 × and reduces energy consumption by 69.323×. Log approximation NMF combined with KNN(k-nearest neighbors) has only 2.38% decreasing accuracy compared with the result of KNN processing the matrix after floating-point NMF on MNIST. Further on, compared with a dedicated floating-point accelerator, the logarithmic approximation approach achieves 3.718× acceleration and 8.345× energy reduction. Compared with the fixed-point approach, our approach has an accuracy degradation of 1.93% on MNIST and an accuracy amelioration of 28.2% on the FASHION MNIST data set without pre-knowledge of the data range. Thus, our approach has better compatibility with the input data range.

  • 231.
    Cheng, Lihong
    et al.
    School of Electro-Mechanical Engineering, Xidian University, Xi’an, China.
    Feng, Lei
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Model abstraction for discrete-event systems using a SAT solver2023In: IEEE Access, E-ISSN 2169-3536, Vol. 11, p. 17334-17347Article in journal (Refereed)
    Abstract [en]

    Model abstraction for finite state automata is beneficial to reduce the complexity of discrete-event systems (DES), enhances the readability and facilitates the control synthesis and verification of DES. Supremal quasi-congruence computation is an effective way for reducing the state space of DES. Effective algorithms on the supremal quasi-congruence relation have been developed based on the graph theory. This paper proposes a new approach to translate the supremal quasi-congruence computation into a satisfiability (SAT) problem that determines whether there exists an assignment for Boolean variables in the state-to-coset allocation matrix. If the result is satisfied, then the supremal quasi-congruence relation exists and the minimum equivalence classes is obtained. Otherwise, it indicates that there is no such supremal quasi-congruence relation, and a new set of observable events needs to be modified or reselected for the original system model. The satisfiability problem on the computation of supremal quasi-congruence relation is solved by different methods, which are respectively implemented by mixed integer linear programming (MILP) in MATLAB, binary linear programming (BLP) in CPLEX, and a SAT-based solver (Z3Py). Compared with the MILP and BLP methods, the SAT method is more efficient and stable. The computation time of model abstraction for large-scale systems by Z3Py solver is significantly reduced.

  • 232.
    Chenine, Moustafa
    et al.
    KTH, School of Electrical Engineering (EES), Industrial Information and Control Systems.
    Kabilan, Vandana
    Department of Computer and Systems Sciences, Faculty of Social Sciences, Stockholm University. .
    Garcia Lozano, Marianela
    FOI, Swedish Defence Research Agency, Department of Systems Modelling.
    A Pattern for Designing Distributed Heterogeneous Ontologies for Facilitating Application Interoperability2006In: EMOI - INTEROP'06, Enterprise Modelling and Ontologies for Interoperability, Proceedings of the Open Interop Workshop on Enterprise Modelling and Ontologies for Interoperability / [ed] Michele Missikoff, Antonio De Nicola, Fulvio D'Antonio, CEUR-WS.org , 2006Conference paper (Refereed)
    Abstract [en]

    The role of ontologies in knowledge base systems is gradually increasing. Along with the growth of Internet based applications and e- commerce, the need for easy interoperability between ontologies is paramount. Today methodologies and design guidelines for building and developing ontologies from scratch exist, and others have focused on evolving step-by-step growth of ontologies as shall be discussed in this paper. However, we find inadequate aid in the design of distributed, heterogeneous and multi-functioned, application ontology, primarily aimed to be the central hub for interoperability between a number of other applications which may or may not be ontology based. In this paper, we present a logical context based ontology design architecture in the form of Principle-Subject-Support(PSS) pattern. The PSS pattern has been used as a guide to analyze and model   several perspectives involved in a practical case study carried out in a military network simulation project to build a distributed repository ontology (DRONT) for interoperability.

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  • 233. Chfouka, Hind
    et al.
    Nemati, Hamed
    KTH, School of Computer Science and Communication (CSC), Theoretical Computer Science, TCS.
    Guanciale, Roberto
    KTH, School of Computer Science and Communication (CSC), Theoretical Computer Science, TCS.
    Dam, Mads
    KTH, School of Computer Science and Communication (CSC), Theoretical Computer Science, TCS.
    Ekdahl, P.
    Ericsson AB.
    Trustworthy prevention of code injection in Linux on embedded devices2015In: 20th European Symposium on Research in Computer Security, ESORICS 2015, Springer, 2015, p. 90-107Conference paper (Refereed)
    Abstract [en]

    We present MProsper, a trustworthy system to prevent code injection in Linux on embedded devices. MProsper is a formally verified run-time monitor, which forces an untrusted Linux to obey the executable space protection policy; a memory area can be either executable or writable, but cannot be both. The executable space protection allows the MProsper’s monitor to intercept every change to the executable code performed by a user application or by the Linux kernel. On top of this infrastructure, we use standard code signing to prevent code injection. MProsper is deployed on top of the Prosper hypervisor and is implemented as an isolated guest. Thus MProsper inherits the security property verified for the hypervisor: (i) Its code and data cannot be tampered by the untrusted Linux guest and (ii) all changes to the memory layout is intercepted, thus enabling MProsper to completely mediate every operation that can violate the desired security property. The verification of the monitor has been performed using the HOL4 theorem prover and by extending the existing formal model of the hypervisor with the formal specification of the high level model of the monitor.

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  • 234.
    Chien, Steven W.D.
    et al.
    University of Edinburgh, United Kingdom.
    Sato, Kento
    RIKEN Center for Computational Science Japan.
    Podobas, Artur
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS.
    Jansson, Niclas
    KTH, School of Electrical Engineering and Computer Science (EECS), Centres, Centre for High Performance Computing, PDC.
    Markidis, Stefano
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
    Honda, Michio
    University of Edinburgh, United Kingdom.
    Improving Cloud Storage Network Bandwidth Utilization of Scientific Applications2023In: Proceedings of the 7th Asia-Pacific Workshop on Networking, APNET 2023, Association for Computing Machinery (ACM) , 2023, p. 172-173Conference paper (Refereed)
    Abstract [en]

    Cloud providers began to provide managed services to attract scientific applications, which have been traditionally executed on supercomputers. One example is AWS FSx for Lustre, a fully managed parallel file system (PFS) released in 2018. However, due to the nature of scientific applications, the frontend storage network bandwidth is left completely idle for the majority of its lifetime. Furthermore, the pricing model does not match the scalability requirement. We propose iFast, a novel host-side caching mechanism for scientific applications that improves storage bandwidth utilization and end-to-end application performance: by overlapping compute and data writeback through inexpensive local storage. iFast supports the Massage Passing Interface (MPI) library that is widely used by scientific applications and is implemented as a preloaded library. It requires no change to applications, the MPI library, or support from cloud operators. We demonstrate how iFast can accelerate the end-to-end time of a representative scientific application Neko, by 13-40%.

  • 235.
    Chien, Wei Der
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST). KTH, School of Electrical Engineering and Computer Science (EECS), Centres, Centre for High Performance Computing, PDC.
    An Evaluation of TensorFlow as a Programming Framework for HPC Applications2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In recent years, deep-learning, a branch of machine learning gained increasing popularity due to their extensive applications and performance. At the core of these application is dense matrix-matrix multiplication. Graphics Processing Units (GPUs) are commonly used in the training process due to their massively parallel computation capabilities. In addition, specialized low-precision accelerators have emerged to specifically address Tensor operations. Software frameworks, such as TensorFlow have also emerged to increase the expressiveness of neural network model development. In TensorFlow computation problems are expressed as Computation Graphs where nodes of a graph denote operation and edges denote data movement between operations. With increasing number of heterogeneous accelerators which might co-exist on the same cluster system, it became increasingly difficult for users to program efficient and scalable applications. TensorFlow provides a high level of abstraction and it is possible to place operations of a computation graph on a device easily through a high level API. In this work, the usability of TensorFlow as a programming framework for HPC application is reviewed. We give an introduction of TensorFlow as a programming framework and paradigm for distributed computation. Two sample applications are implemented on TensorFlow: tiled matrix multiplication and conjugate gradient solver for solving large linear systems. We try to illustrate how such problems can be expressed in computation graph for distributed computation. We perform scalability tests and comment on performance scaling results and quantify how TensorFlow can take advantage of HPC systems by performing micro-benchmarking on communication performance. Through this work, we show that TensorFlow is an emerging and promising platform which is well suited for a particular class of problem which requires very little synchronization.

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  • 236.
    Chien, Wei Der
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Theoretical Computer Science, TCS.
    Peng, Ivy B.
    Lawrence Livermore National LaboratoryLivermoreUSA.
    Markidis, Stefano
    KTH, Centres, SeRC - Swedish e-Science Research Centre. KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
    Posit NPB: Assessing the precision improvement in HPC scientific applications2020In: Lecture Notes in Computer Science, Springer , 2020, p. 301-310Conference paper (Refereed)
    Abstract [en]

    Floating-point operations can significantly impact the accuracy and performance of scientific applications on large-scale parallel systems. Recently, an emerging floating-point format called Posit has attracted attention as an alternative to the standard IEEE floating-point formats because it could enable higher precision than IEEE formats using the same number of bits. In this work, we first explored the feasibility of Posit encoding in representative HPC applications by providing a 32-bit Posit NAS Parallel Benchmark (NPB) suite. Then, we evaluate the accuracy improvement in different HPC kernels compared to the IEEE 754 format. Our results indicate that using Posit encoding achieves optimized precision, ranging from 0.6 to 1.4 decimal digit, for all tested kernels and proxy-applications. Also, we quantified the overhead of the current software implementation of Posit encoding as 4×–19× that of IEEE 754 hardware implementation. Our study highlights the potential of hardware implementations of Posit to benefit a broad range of HPC applications. 

  • 237.
    Chien, Wei Der
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Theoretical Computer Science, TCS.
    Peng, Ivy
    Markidis, Stefano
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
    Performance evaluation of advanced features in CUDA unified memory2019In: Proceedings of MCHPC 2019: Workshop on Memory Centric High Performance Computing - Held in conjunction with SC 2019: The International Conference for High Performance Computing, Networking, Storage and Analysis, Institute of Electrical and Electronics Engineers Inc. , 2019, p. 50-57Conference paper (Refereed)
    Abstract [en]

    CUDA Unified Memory improves the GPU pro- grammability and also enables GPU memory oversubscription. Recently, two advanced memory features, memory advises and asynchronous prefetch, have been introduced. In this work, we evaluate the new features on two platforms that feature different CPUs, GPUs, and interconnects. We derive a benchmark suite for the experiments and stress the memory system to evaluate both in-memory and oversubscription performance. The results show that memory advises on the Intel-Volta/Pascal- PCIe platform bring negligible improvement for in-memory exe- cutions. However, when GPU memory is oversubscribed by about 50%, using memory advises results in up to 25% performance improvement compared to the basic CUDA Unified Memory. In contrast, the Power9-Volta-NVLink platform can substantially benefit from memory advises, achieving up to 34% performance gain for in-memory executions. However, when GPU memory is oversubscribed on this platform, using memory advises increases GPU page faults and results in considerable performance loss. The CUDA prefetch also shows different performance impact on the two platforms. It improves performance by up to 50% on the Intel-Volta/Pascal-PCI-E platform but brings little benefit to the Power9-Volta-NVLink platform.

  • 238.
    Chiesa, Marco
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS, Network Systems Laboratory (NS Lab).
    Verdi, Fabio L.
    Fed Univ Sao Carlos UFSCar, Rod Joao Leme dos Santos,Km 110, BR-18052780 Sorocaba, Brazil..
    Network Monitoring on Multi-Pipe Switches2023In: PROCEEDINGS OF THE ACM ON MEASUREMENT AND ANALYSIS OF COMPUTING SYSTEMS, ISSN 2476-1249, Vol. 7, no 1, p. 1-31, article id 3-ART8Article in journal (Refereed)
    Abstract [en]

    Programmable switches have been widely used to design network monitoring solutions that operate in the fast data-plane level, e.g., detecting heavy hitters, super-spreaders, computing flow size distributions and their entropy. Many existing works on networking monitoring assume switches deploy a single memory that is accessible by each processed packet. However, high-speed ASIC switches increasingly deploy multiple independent pipes, each equipped with its own independent memory that cannot be accessed by other pipes. In this work, we initiate the study of deploying existing heavy-hitter data-plane monitoring solutions on multi-pipe switches where packets of a "flow" may spread over multiple pipes, i.e., stored into distinct memories. We first quantify the accuracy degradation due to splitting a monitoring data structure across multiple pipes (e.g., up to 3000xworse flow-size estimation average error). We then present PipeCache, a system that adapts existing data-plane mechanisms to multi-pipe switches by carefully storing all the monitoring information of each traffic class into exactly one specific pipe (as opposed to replicate the information on multiple pipes). PipeCache relies on the idea of briefly storing monitoring information into a per-pipe cache and then piggybacking this information onto existing data packets to the correct pipe entirely at data-plane speed. We implement PipeCache on ASIC switches and we evaluate it using a real-world trace. We show that existing data-plane mechanisms achieves accuracy levels and memory requirements similar to single-pipe deployments when augmented with PipeCache (i.e., up to 16x lower memory requirements).

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  • 239.
    Chiesa, Marco
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS.
    Verdi, Fabio L.
    Federal University of São Carlos, Sorocaba, Brazil.
    Network Monitoring on Multi-Pipe Switches2023In: Performance Evaluation Review, ISSN 0163-5999, E-ISSN 1557-9484, Vol. 51, no 1, p. 49-50Article in journal (Refereed)
    Abstract [en]

    Programmable switches have been widely used to design network monitoring solutions that operate in the fast data-plane level, e.g., detecting heavy hitters, super-spreaders, computing flow size distributions and their entropy. Existing works assume packets access the same memory region in a switch. However, high-speed ASIC switches deploy multiple packet processing pipes, each equipped with its own independent memory. In this work, we first quantify the accuracy degradation due to splitting a monitoring data structure across multiple pipes (e.g., up to 3000x worse flow-size estimation average error). We then present PipeCache, a system that adapts existing data-plane mechanisms to multi-pipe switches by storing monitoring information for a traffic class into a single pipe. PipeCache stores monitoring information into a cache and piggybacks this information onto existing data packets to the correct pipe. Our implementation shows a 2-20x memory reduction to achieve an accuracy similar to single-pipe deployments.

  • 240.
    Chiesa, Marco
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS.
    Verdi, Fabio L.
    Federal University of Sao Carlos, Sorocaba, Brazil.
    Network Monitoring on Multi-Pipe Switches2023In: SIGMETRICS 2023 - Abstract Proceedings of the 2023 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, Association for Computing Machinery (ACM) , 2023, p. 49-50Conference paper (Refereed)
    Abstract [en]

    Programmable switches have been widely used to design network monitoring solutions that operate in the fast data-plane level, e.g., detecting heavy hitters, super-spreaders, computing flow size distributions and their entropy. Existing works assume packets access the same memory region in a switch. However, high-speed ASIC switches deploy multiple packet processing pipes, each equipped with its own independent memory. In this work, we first quantify the accuracy degradation due to splitting a monitoring data structure across multiple pipes (e.g., up to 3000x worse flow-size estimation average error). We then present PipeCache, a system that adapts existing data-plane mechanisms to multi-pipe switches by storing monitoring information for a traffic class into a single pipe. PipeCache stores monitoring information into a cache and piggybacks this information onto existing data packets to the correct pipe. Our implementation shows a 2-20x memory reduction to achieve an accuracy similar to single-pipe deployments.

  • 241.
    Chodnicki, Marek
    et al.
    Gdańsk University of Technology, Gdańsk, Poland.
    Deja, Mariusz
    Gdańsk University of Technology, Gdańsk, Poland.
    Vosniakos, George Christopher
    National Technical University of Athens, Athens, Greece.
    Benardos, Panorios
    National Technical University of Athens, Athens, Greece.
    Wang, Lihui
    KTH, School of Industrial Engineering and Management (ITM), Production engineering.
    Wang, Xi Vincent
    KTH, School of Industrial Engineering and Management (ITM), Production engineering.
    Braun, Thomas
    Technische Universität Berlin, Berlin, Germany.
    Reimann, Robert
    Technische Universität Berlin, Berlin, Germany.
    Project-Based Collaborative Research and Training Roadmap for Manufacturing Based on Industry 4.02024In: Flexible Automation and Intelligent Manufacturing: Establishing Bridges for More Sustainable Manufacturing Systems, Springer Nature , 2024, p. 708-715Conference paper (Refereed)
    Abstract [en]

    The importance of the economy being up to date with the latest developments, such as Industry 4.0, is more evident than ever before. Successful implementation of Industry 4.0 principles requires close cooperation of industry and state authorities with universities. A paradigm of such cooperation is described in this paper stemming from university partners with partly overlapping and partly complementary areas of expertise in manufacturing. Specific areas that are targeted include Additive Manufacturing, cloud computing and control, Virtual Reality, Digital Twins, and Artificial Intelligence. The manufacturing system domains that are served pertaining to process planning and optimization, process and system monitoring, and innovative / precision manufacturing. The described collaborative research and training framework involves a combination of pertinent targeted individual exploratory innovation projects as well as a synthetic multifaceted common research project. Based on these, the research and innovation project knowledge will be transferred to the industry by building a Cluster of Excellence, i.e., a network consisting of academic and industrial stakeholders.

  • 242. Chollet, M.
    et al.
    Stefanov, Kalin
    KTH, School of Computer Science and Communication (CSC), Speech, Music and Hearing, TMH.
    Prendinger, H.
    Scherer, S.
    Public Speaking Training with a Multimodal Interactive Virtual Audience Framework2015In: ICMI '15 Proceedings of the 2015 ACM on International Conference on Multimodal Interaction, ACM Digital Library, 2015, p. 367-368Conference paper (Refereed)
    Abstract [en]

    We have developed an interactive virtual audience platform for public speaking training. Users' public speaking behavior is automatically analyzed using multimodal sensors, and ultimodal feedback is produced by virtual characters and generic visual widgets depending on the user's behavior. The flexibility of our system allows to compare different interaction mediums (e.g. virtual reality vs normal interaction), social situations (e.g. one-on-one meetings vs large audiences) and trained behaviors (e.g. general public speaking performance vs specific behaviors).

  • 243. Ciccozzi, F.
    et al.
    Corcoran, Diarmuid
    Seceleanu, T.
    Scholle, D.
    SMARTCore: Boosting Model-Driven Engineering of Embedded Systems for Multicore2015In: 2015 12th International Conference on Information Technology - New Generations, 2015Conference paper (Refereed)
    Abstract [en]

    Thanks to continuous advances in both software and hardware technologies the power of modern embedded systems is ever increasing along with their complexity. Among the others, Model-Driven Engineering has grown consideration for mitigating this complexity through its ability to shift the focus of the development from hand-written code to models from which correct-by-construction implementation is automatically generated. However, the path towards correctness-by-construction is often twisted by the inability of current MDE approaches to preserve certain extra-functional properties such as CPU and memory usage, execution time and power consumption. With SMART Core we address open challenges, described in this paper together with an overview of possible solutions, in modelling, generating code from models, and exploiting back-propagated extra-functional properties observed at runtime for deployment optimisation of embedded systems on multicore. SMART Core brings together world leading competence in software engineering, model-driven engineering for embedded systems (Mälardalen University), and market leading expertise in the development of these systems in different business areas (ABB Corporate Research, Ericsson AB, Alten Sweden AB).

  • 244. Ciccozzi, F.
    et al.
    Seceleanu, T.
    Corcoran, Diarmuid
    Ericsson AB, Kista, Sweden.
    Scholle, D.
    UML-Based Development of Embedded Real-Time Software on Multi-Core in Practice: Lessons Learned and Future Perspectives2016In: IEEE Access, 2016Conference paper (Refereed)
    Abstract [en]

    Model-driven engineering has got a foothold in industry as an effective way to tame the complexity of modern software, which is meant to run on embedded systems with real-time constraints by promoting abstraction, in terms of prescriptive models, and automation, in terms of model manipulations. In the plethora of modeling languages, the unified modeling language (UML) has emerged and established itself as a de facto standard in industry, the most widely used architectural description language and an ISO/IEC standard. In the SMARTCore project, we have provided solutions for the UML-based development of software to run on multicore embedded real-time systems with the specific focus of automating the generation of executable code and the optimization of task allocation based on a unique combination of model-based and execution-based mechanisms. In this paper, we describe the lessons learned in the research work carried out within SMARTCore and provide a set of perspectives that we consider to be highly relevant for the forthcoming future of this research area to enable a wider adoption of UML-based development in industry in general, and in the multicore embedded real-time domain in particular.

  • 245.
    Clerc, Anthony
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Tracking of railroads for autonomous guidance of UAVs: using Vanishing Point detection2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    UAVs have gained in popularity and the number of applications has soared over the past

    years, ranging from leisure to commercial activities. This thesis is discussing specifically

    railroad applications, which is a domain rarely explored. Two different aspects are analysed.

    While developing a new application or migrating a ground-based system to UAV platform,

    the different challenges encountered are often unknown. Therefore, this thesis highlights the

    most important ones to take into consideration during the development process.

    From a more technical aspect, the implementation of autonomous guidance for UAVs

    over railroads using vanishing point extraction is studied. Two different algorithms are

    presented and compared, the first one is using line extraction method whereas the second

    uses joint activities of Gabor filters. The results demonstrate that the applied methodologies

    provide good results and that a significant difference exists between both algorithms in terms

    of computation time.

    A second implementation tackling the detection of railway topologies to enable the

    use on multiple rail road configurations is discussed. A first technique is presented using

    exclusively vanishing points for the detection, however, the results for complex images are

    not satisfactory. Therefore, a second method is studied using line characteristics on top of

    the previous algorithm. This second implementation has proven to give good results.

    Download full text (pdf)
    fulltext
  • 246.
    Cllasun, Hüsrev
    et al.
    University of Minnesota, USA.
    MacAraeg, Chris
    Lawrence Livermore National Lab, USA.
    Peng, Ivy Bo
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
    Sarkar, Abhik
    Lawrence Livermore National Lab, USA.
    Gokhale, Maya
    KTH.
    FPGA-accelerated simulation of variable latency memory systems2022In: MEMSYS 2022 - Proceedings of the International Symposium on Memory Systems, Association for Computing Machinery (ACM) , 2022, article id 8Conference paper (Refereed)
    Abstract [en]

    With the growing complexity of memory types, organizations, and placement, efficient use of memory systems remains a key objective to processing data-rich workloads. Heterogeneous memories including HBM, conventional DRAM, and persistent memory, both locally and network-attached, exhibit a wide range of latencies and bandwidths. The delivered performance to an application may vary widely depending on workload and interference from competing clients. Evaluating the impact on applications to these emerging memory systems challenges traditional simulation techniques. In this work, we describe VLD-sim, an FPGA-accelerated simulator designed to evaluate application performance in the presence of varying non-deterministic latency. VLD-sim implements a statistical approach in which memory system access latency is non-deterministic, as would occur when request traffic is generated from a large collection of possibly unrelated threads and compute nodes. VLD-sim runs on a Multi-Processor System on Chip with hard CPU plus configurable logic to enable fast evaluation of workloads or of individual applications. We evaluate VLD-sim with CPU-only and near memory accelerator-enabled applications and compare against an idealized fixed latency baseline. Our findings reveal and quantify performance impact on applications due to non-deterministic latency. With high flexibility and and fast execution time, VLD-sim enables system level evaluation of a large memory architecture design space.

  • 247.
    Collin, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Brorsson, Mats
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Low Power Instruction Fetch using Profiled Variable Length Instructions2003Conference paper (Refereed)
    Abstract [en]

    Computer system performance depends on high access rate and low miss rate in the instruction cache, which also affects energy consumed by fetching instructions. Simulation of a small computer typical for embedded systems show that up to 20% of the overall processor energy is consumed in the instruction fetch path and as much as 23% of the execution time is spent on instruction fetch. One way to increase the instruction memory bandwidth is to fetch more instructions each access without increasing the bus width. We propose an extension to a RISC ISA, with variable length instructions, yielding higher information density without compromising programmability. Based on profiling of dynamic instruction usage and argument locality of a set of SPEC CPU2000 applications, we present a scheme using 8- 16- and 24-bit instructions accompanied by lookup tables inside the processor. Our scheme yields a 20-30% reduction in static memory usage, and experiments show that up to 60% of all executed instructions consist of short instructions. The overall energy savings are up to 15% for the entire data path and memory system, and up to 20% in the instruction fetch path.

  • 248.
    Collin, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Brorsson, Mats
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Low Power Instruction Fetch using Variable Length Instructions2003Conference paper (Refereed)
  • 249. Colombo, Leonardo J.
    et al.
    Dimarogonas, Dimos V.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Decision and Control Systems (Automatic Control). KTH, School of Electrical Engineering and Computer Science (EECS), Centres, Centre for Autonomous Systems, CAS. KTH, School of Electrical Engineering and Computer Science (EECS), Centres, ACCESS Linnaeus Centre.
    Motion Feasibility Conditions for Multiagent Control Systems on Lie Groups2020In: IEEE Transactions on Control of Network Systems, E-ISSN 2325-5870, Vol. 7, no 1, p. 493-502Article in journal (Refereed)
    Abstract [en]

    We study the problem of motion feasibility for multiagent control systems on Lie groups with collision-avoidance constraints. We first consider the problem for kinematic left-invariant control systems and next, for dynamical control systems given by a left-trivialized Lagrangian function. Solutions of the kinematic problem give rise to linear combinations of the control inputs in a linear subspace, annihilating the collision-avoidance constraints. In the dynamical problem, motion feasibility conditions are obtained by using techniques from variational calculus on manifolds, given by a set of equations in a vector space, and Lagrange multipliers annihilating the constraint force that prevents the deviation of solutions from a constraint submanifold.

  • 250. Comanducci, Dario
    et al.
    Maki, Atsuto
    Toshiba Research Europe Cambridge CB4 0GZ, UK.
    Colombo, Carlo
    Cipolla, Roberto
    2D-3D Photo Rendering for 3D Displays2010Conference paper (Refereed)
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