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  • 251.
    Lobov, Gleb
    et al.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Optics and Photonics, OFO.
    Zhao, Yichen
    KTH, School of Information and Communication Technology (ICT).
    Marinins, Aleksandrs
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Optics and Photonics, OFO.
    Yan, Min
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Optics and Photonics, OFO.
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT).
    Sugunan, A.
    Thylén, Lars
    KTH, School of Biotechnology (BIO). Hewlett-Packard Laboratories, United States.
    Wosinski, L.ech
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Photonics and Microwave Engineering , FMI.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Toprak, Muhammet
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM.
    Popov, Sergei
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Optics and Photonics, OFO.
    Dynamic Manipulation of Optical Anisotropy of Suspended Poly-3-hexylthiophene Nanofibers2016In: Advanced Optical Materials, ISSN 2195-1071, Vol. 4, no 10, p. 1651-1656Article in journal (Refereed)
    Abstract [en]

    Poly-3-hexylthiophene (P3HT) nanofibers are 1D crystalline semiconducting nanostructures, which are known for their application in photovoltaics. Due to the internal arrangement, P3HT nanofibers possess optical anisotropy, which can be enhanced on a macroscale if nanofibers are aligned. Alternating electric field, applied to a solution with dispersed nanofibers, causes their alignment and serves as a method to produce solid layers with ordered nanofibers. The transmission ellipsometry measurements demonstrate the dichroic absorption and birefringence of ordered nanofibers in a wide spectral range of 400–1700 nm. Moreover, the length of nanofibers has a crucial impact on their degree of alignment. Using electric birefringence technique, it is shown that external electric field applied to the solution with P3HT nanofibers can cause direct birefringence modulation. Dynamic alignment of dispersed nanofibers changes the refractive index of the solution and, therefore, the polarization of transmitted light. A reversible reorientation of nanofibers is organized by using a quadrupole configuration of poling electrodes. With further development, the described method can be used in the area of active optical fiber components, lab-on-chip or sensors. It also reveals the potential of 1D conducting polymeric structures as objects whose highly anisotropic properties can be implemented in electro-optical applications.​

  • 252.
    Loiko, Pavel
    et al.
    ITMO Univ, Kronverkskiy Pr 49, St Petersburg 197101, Russia..
    Maria Serres, Josep
    URV, Dept Quim Fis & Inorgan, Fis & Cristal Lografia Mat & Nanomat FiCMA FiCNA, EMaS, E-43007 Tarragona, Spain..
    Delekta, Szymon Sollami
    KTH, School of Information and Communication Technology (ICT).
    Kifle, Esrom
    URV, Dept Quim Fis & Inorgan, Fis & Cristal Lografia Mat & Nanomat FiCMA FiCNA, EMaS, E-43007 Tarragona, Spain..
    Boguslawski, Jakub
    Wroclaw Univ Sci & Technol, Fac Elect, Laser & Fiber Elect Grp, Wybrzeze S Wyspianskiego 27, PL-50370 Wroclaw, Poland.;Polish Acad Sci, Inst Phys Chem, Kasprzaka 44-52, PL-01224 Warsaw, Poland..
    Kowalczyk, Maciej
    Wroclaw Univ Sci & Technol, Fac Elect, Laser & Fiber Elect Grp, Wybrzeze S Wyspianskiego 27, PL-50370 Wroclaw, Poland..
    Sotor, Jaroslaw
    Wroclaw Univ Sci & Technol, Fac Elect, Laser & Fiber Elect Grp, Wybrzeze S Wyspianskiego 27, PL-50370 Wroclaw, Poland..
    Aguilo, Magdalena
    URV, Dept Quim Fis & Inorgan, Fis & Cristal Lografia Mat & Nanomat FiCMA FiCNA, EMaS, E-43007 Tarragona, Spain..
    Diaz, Francesc
    URV, Dept Quim Fis & Inorgan, Fis & Cristal Lografia Mat & Nanomat FiCMA FiCNA, EMaS, E-43007 Tarragona, Spain..
    Griebner, Uwe
    Max Born Inst Nonlinear Opt & Short Pulse Spect, Max Born Str 2a, D-12489 Berlin, Germany..
    Petrov, Valentin
    Max Born Inst Nonlinear Opt & Short Pulse Spect, Max Born Str 2a, D-12489 Berlin, Germany..
    Popov, Sergei
    KTH, School of Information and Communication Technology (ICT).
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT).
    Mateos, Xavier
    URV, Dept Quim Fis & Inorgan, Fis & Cristal Lografia Mat & Nanomat FiCMA FiCNA, EMaS, E-43007 Tarragona, Spain..
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Inkjet-printing of graphene saturable absorbers for similar to 2 mu m bulk and waveguide lasers2018In: Optical Materials Express, ISSN 2159-3930, E-ISSN 2159-3930, Vol. 8, no 9, p. 2803-2814Article in journal (Refereed)
    Abstract [en]

    A technique for inkjet-printing of graphene saturable absorbers (SAs) for similar to 2-mu m bulk and waveguide lasers is presented. Based on distillation-assisted solvent exchange to fabricate high-concentration graphene inks, this technique is capable of producing few-layer graphene films of arbitrary shape. Absorption saturation of graphene printed on glass is demonstrated at similar to 1.56 mu m for picosecond and femtosecond pulses indicating a large fraction of the saturable losses. Inkjet-printed transmission-type graphene SAs are applied in passively Q-switched nanosecond thulium (Tm) microchip and planar waveguide lasers. The Tm microchip laser generates 136 ns / 1.2 mu J pulses at 1917 nm with a repetition rate of 0.37 MHz with a Q-switching conversion efficiency reaching 65%. The planar waveguide laser generates 98 ns / 21 nJ pulses at 1834 nm at a repetition rate in the MHz-range. The inkjet-printing technique is promising for production of patterned SAs for waveguide lasers.

  • 253.
    Loiko, Pavel
    et al.
    ITMO Univ, 49 Kronverkskiy Pr, St Petersburg 197101, Russia..
    Maria Serres, Josep
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Delekta, Szymon Sollami
    KTH, School of Information and Communication Technology (ICT).
    Kifle, Esrom
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Mateos, Xavier
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain.;Max Born Inst Nonlinear Opt & Short Pulse Spect, 2A Max Born Str, D-12489 Berlin, Germany..
    Baranov, Alexander
    ITMO Univ, 49 Kronverkskiy Pr, St Petersburg 197101, Russia..
    Aguilo, Magdalena
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Diaz, Francesc
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Griebner, Uwe
    Max Born Inst Nonlinear Opt & Short Pulse Spect, 2A Max Born Str, D-12489 Berlin, Germany..
    Petrov, Valentin
    Max Born Inst Nonlinear Opt & Short Pulse Spect, 2A Max Born Str, D-12489 Berlin, Germany..
    Popov, Sergei
    KTH, School of Engineering Sciences (SCI), Applied Physics, Photonics.
    Li, Jiantong
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Inkjet-Printing of Graphene Saturable Absorbers for similar to 2 mu m Bulk and Waveguide Lasers2017In: 2017 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    We report on inkjet-printing of graphene saturable absorbers (SAs) suitable for passive Q-switching of similar to 2-mu m bulk and waveguide lasers. Using graphene-SA in a microchip Tm:KLu(WO4)(2) laser, 1.2 mu J/136 ns pulses are generated at 1917 nm.

  • 254. Lu, Jun
    et al.
    Luo, Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hultman, Lars
    Kinetics and morphology of Ni1-xPtx-silicide epitaxy on Si(001)In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775Article in journal (Other academic)
  • 255. Lu, Jun
    et al.
    Luo, Jun
    KTH, School of Information and Communication Technology (ICT), Material Physics.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Material Physics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Hultman, Lars
    On Epitaxy of Ultrathin Ni1-xPtx Silicide Films on Si(001)2010In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775, Vol. 13, no 10, p. H360-H362Article in journal (Refereed)
    Abstract [en]

    Epitaxial Ni(Pt)Si2-y (y < 1) films readily grow upon thermal treatment of 2 nm thick Ni and Ni0.96Pt0.04 films deposited on Si(001). For annealing at 500 degrees C, the films are 5.4-5.6 nm thick with 61-70 mu cm in resistivity. At 750 degrees C, the epitaxial Ni(Pt)Si2-y films become 6.1-6.2 nm thick with a resistivity of 42-44 mu cm. Structural analysis reveals twins, facet wedges, and thickness inhomogeneities in the films grown at 500 degrees C. For higher temperature, an almost defect-free NiSi2-y film with a flat and sharp interface is formed. The presence of Pt makes the aforementioned imperfections more persistent.

  • 256. Lundberg, N.
    et al.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tagtstrom, P.
    Jansson, U.
    CVD-based tungsten carbide Schottky contacts to 6H-SiC for very high-temperature operation2000In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 29, no 3, p. 372-375Article in journal (Refereed)
    Abstract [en]

    In this study, tungsten carbide, with its hardness, chemical inertness, thermal stability and low resistivity (25 mu Omega cm)(1) is shown as a reliable contact material to n- and p-type 6H-SiC for very high temperature applications. WC films with thicknesses of 100-150 nm were deposited by chemical vapor deposition (CVD) from a WF6/C3H8/H-2 mixture at 1173 K. A method to pattern CVD-tungsten carbide is suggested. TEM analysis of as deposited samples displayed a clear and unreacted interface. The electrical investigations of the p-type 6H-SiC Schottky contacts revealed a high rectification ratio and a low reverse current density (6.1 x 10(-5) A cm(-2), -10 V) up to 713 K. On n-type, a low barrier (Phi(Bn) = 0.79 eV) at room temperature was observed. The low Phi(Bn) value suggests WC to be promising as an ohmic contact material on highly doped n-type epi-layers. We will show a temperature dependence for the barrier height of tungsten carbide contacts that can be related to the simultaneous change in the energy bandgap, which should be considered when designing SiC devices intended for high temperature operation.

  • 257. Lundberg, Nils
    et al.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Temperature stability of cobalt Schottky contacts on n- and p-type 6H silicon carbide1993In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Vol. 73, no C, p. 316-321Article in journal (Refereed)
    Abstract [en]

    Rectifying Schottky contacts have been manufactured on n- and p-type 6H silicon carbide using e-beam evaporation of cobalt. Heat treatments in the 300 to 1100°C temperature range have been made to study the feasibility of high temperature contacts in this material system. Rutherford backscattering spectrometry and X-ray diffraction have revealed the formation of different cobalt silicides (Co2Si, CoSi, and CoSi2) at higher temperatures than for the Co/Si system. No evidence of silicidation was found below 600°C and SEM micrographs revealed carbon agglomerates at the surface after silicidation. Electrical properties have been examined using I-V and C-V measurements, and the barrier heights of cobalt and Co2Si were evaluated. The contacts displayed excellent forward I-V characteristics with good linearity over 3-6 decades and were rectifying even after heat treatments at 800°C. © 1993.

  • 258.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    Deng, Jian
    Zhao, Chao
    Li, Junfeng
    Wang, Wenwu
    Chen, Dapeng
    Wu, Dongping
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ye, Tianchun
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effects of carbon pre-silicidation implant into Si substrate on NiSi2014In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 120, p. 178-181Article in journal (Refereed)
    Abstract [en]

    In this work, the effects of carbon pre-silicidation implant into Si(1 0 0) substrate on NiSi were investigated. NiSi films with carbon pre-silicidation implant to different doses were characterized by means of sheet resistance measurements, X-ray diffraction, scanning electron microscopy (SEM), planar view transmission electron microscopy (TEM) and second ion mass spectroscopy (SIMS). The presence of C is found to indeed significantly improve the thermal stability of NiSi as well as tends to change the preferred orientations of polycrystalline NiSi. The homogeneously distributed C at NiSi grain boundaries and C peak at NiSi/Si interface is ascribed to the improved thermal stability of NiSi. More importantly, the dose of carbon pre-silicidation implant also plays a key role in the formation of NiSi, which is suggested not to exceed a critical value about 5 x 10(15) cm(-2) in practical application in accordance with the results achieved in this work.

  • 259.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    Deng, Jian
    Zhao, Chao
    Li, Junfeng
    Wang, Wenwu
    Chen, Dapeng
    Wu, Dongping
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ye, Tianchun
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Variation of Schottky barrier height induced by dopant segregation monitored by contact resistivity measurements2014In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 120, p. 174-177Article in journal (Refereed)
    Abstract [en]

    Change of contact resistivity (rho(c)) is monitored for evaluation of Schottky barrier height (SBH) variation induced by dopant segregation (DS). This method is particularly advantageous for metal-semiconductor contacts of small SBH, as it neither requires low-temperature measurement needed in current-voltage characterization of Schottky diodes nor is affected by reverse leakage current often troubling capacitance-voltage characterization. With PtSi contact to both n- and p-type diffusion regions, and the use of opposite or alike dopants implant into pre-formed PtSi films followed by drive-in anneal at different temperatures to induce DS at PtSi/Si interface, the formation of interfacial dipole is confirmed as the responsible cause for modification of effective SBHs thus the increase or decrease of rho(c). A tentative explanation for the change of contact resistivity based on interfacial dipole theory is provided in this work. Influences and interplay of interfacial dipole and space charge on effective SBH are also discussed.

  • 260.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    Zha, Chaolin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Dongping
    Lu, Jun
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hultman, Lars
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1-xPtx silicide films2010In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 96, no 3Article in journal (Refereed)
    Abstract [en]

    The formation of ultrathin silicide films of Ni1-xPtx at 450-850 degrees C is reported. Without Pt (x=0) and for t(Ni)< 4 nm, epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 degrees C. For t(Ni)>= 4 nm, polycrystalline NiSi films form and agglomerate at lower temperatures for thinner films. Without Ni (x=1) and for t(Pt)=1-20 nm, the annealing behavior of the resulting PtSi films follows that for the NiSi films. The results for Ni1-xPtx of other compositions support the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability.

  • 261.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    Zhang, David Wei
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östrling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effect of carbon on Schottky barrier heights of NiSi modified by dopant segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 6Article in journal (Refereed)
    Abstract [en]

    The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased ∅bn from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600°C. Above this temperature, B-DS at this interface is evident thus keeping φbn high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning ∅bp above 1.0 eV by As-DS.

  • 262.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Qiu, Zhi-Jun
    Zhang, David Wei
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    Effects of Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 6, p. 608-610Article in journal (Refereed)
    Abstract [en]

    The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased phi(bn) from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600 degrees C. Above this temperature, B-DS at this interface is evident thus keeping phi(bn) high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning phi(bn) above 1.0 eV by As-DS.

  • 263.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interaction of NiSi with dopants for metallic source/drain applications2010In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 28, no 1, p. C1I1-C1I11Article in journal (Refereed)
    Abstract [en]

    This work has a focus on NiSi as a possible metallic contact for aggressively scaled complementary metal oxide semiconductor devices. As the bulk work function of NiSi lies close to the middle of Si bandgap, the Schottky barrier height (SBH) of NiSi is rather large for both electron (similar to 0.65 eV) and hole (similar to 0.45 eV). Different approaches have therefore been intensively investigated in the literature aiming at reducing the effective SBH: dopant segregation (DS), surface passivation (SP), and alloying, in order to improve the carrier injection into the conduction channel of a field-effect transistor. The present work explores DS using B and As for the NiSi/Si contact system. The effects of C and N implantation into Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. A combined use of DS or SP with alloying could be considered for more effective control of effective SBH, but an examination of undesired compound formation and its probable consequences is necessary. Furthermore, an analysis of the metal silicides that have a small "intrinsic" SBH reveals that only a very small number of them are of practical interest as most of the silicides require either a high formation temperature or possess a high specific resistivity.

  • 264.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Dongping
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Qiu, Zhijun
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    Lu, Jun
    Department of Physics, Chemistry and Biology, Linköping University.
    Hultman, Lars
    Department of Physics, Chemistry and Biology, Linköping University.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    State Key Lab of ASIC and Systems, School of Microelectronics, Fudan University, Shanghai .
    On Different Process Schemes for MOSFETs With a Controllable NiSi-Based Metallic Source/Drain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 1898-1906Article in journal (Refereed)
    Abstract [en]

    This paper focuses on different silicidation schemes toward a controllable NiSi-based metallic source/drain (MSD) process with restricted lateral encroachment of NiSi. These schemes include thickness control of Ni, Ni-Pt alloying, and two-step annealing. Experimental results show that all the three process schemes can give rise to effective control of lateral encroachment during Ni silicidation. By controlling t(Ni), NiSi-based MSD metal-oxide-semiconductor field-effect transistors (MOSFETs) of gate length L-G = 55 nm are readily realized on ultrathin-body silicon-on-insulator substrates with 20-nm surface Si thickness. With the aid of dopant segregation (DS) to modifying the Schottky barrier heights of NiSi, both n- and p-type MSD MOSFETs show significant performance improvement, compared to reference devices without DS.

  • 265.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wu, Donping
    Qiu, Zhijun
    Lu, Jun
    Hultman, Lars
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    On different process schemes for a controllable NiSi-based metallic source/drainMOSFETs with dopant segregationIn: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646Article in journal (Other academic)
  • 266. Lupina, Grzegorz
    et al.
    Kitzmann, Julia
    Costina, Ioan
    Lukosius, Mindaugas
    Wenger, Christian
    Wolff, Andre
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pasternak, Iwona
    Krajewska, Aleksandra
    Strupinski, Wlodek
    Kataria, Satender
    Gahoi, Amit
    Lemme, Max C.
    Ruhl, Guenther
    Zoth, Guenther
    Luxenhofer, Oliver
    Mehr, Wolfgang
    Residual Metallic Contamination of Transferred Chemical Vapor Deposited Graphene2015In: ACS Nano, ISSN 1936-0851, E-ISSN 1936-086X, Vol. 9, no 5, p. 4776-4785Article in journal (Refereed)
    Abstract [en]

    Integration of graphene with Si microelectronics is very appealing by offering a potentially broad range of new functionalities. New materials to be integrated with the Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etching and electrochemical delamination methods with respect to residual submonolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection X-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10(13) atoms/cm(2). These metal impurities appear to be partially mobile upon thermal treatment, as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics, these results reveal that further progress in synthesis, handling, and cleaning of graphene is required to advance electronic and optoelectronic applications.

  • 267. Ma, P. X.
    et al.
    Linder, M.
    Sanden, M.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Chang, M. C. F.
    An analytical model for space-charge region capacitance based on practical doping profiles under any bias conditions2001In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 45, no 1, p. 159-167Article in journal (Refereed)
    Abstract [en]

    An analytical model is presented For quasi-static capacitance of the space-charge region in a p-n junction. The model is valid for realistic junction doping profiles under any bias conditions. It consists of local models in three bias regions. For the high-reverse bias region, a novel analytical model is derived. For the moderate-bias region, an empirical model commonly used in SPICE is adopted. Finally, for the high-forward bias region, the junction profiles are approximated by linearly-graded junctions. Existing analytical models are then modified appropriately to characterize both high-injection and heavy-doping effects for advanced bipolar transistors. Compared to previously developed analytical models or existing empirical models, as well as numerical simulation results, the analytical model presented here shows an improved accuracy and therefore provides a better tool For both device and circuit simulations.

  • 268.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Östling,
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Gated base structure for improved current gain in SiC bipolar technology2017In: 2017 47th European Solid-State Device Research Conference (ESSDERC) 11-14 Sept. 2017, Editions Frontieres , 2017, p. 122-125Conference paper (Refereed)
    Abstract [en]

    Silicon Carbide (SiC) bipolar integrated circuits are a promising technology for extreme environment applications. SiC bipolar technology shows stable operation over a wide range of temperature. However, the current gain of the devices is suffering from high surface recombination, due to poor oxide passivation. In this paper we propose a gated base structure that offers improved current gain control. A polysilicon gate is formed on the passivation oxide on top of the base-link region. We investigate the current gain as a function of gate bias and temperature. A negative gate bias improves the gain at low collector current by more than 30% by suppressing the surface recombination. Measurements are presented at temperatures ranging from 300 K to 550 K and the gain is consistently improved. The proposed structure is also useful as a process monitor for the passivation oxide quality.

  • 269.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grahn, J. V.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Influence of transient enhanced diffusion of the intrinsic base dopant profile on SiGeHBT DC and HF characteristics2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 10, p. 1747-1752Article in journal (Refereed)
    Abstract [en]

    The influence of transient enhanced boron out-diffusion from the intrinsic base, caused by excess silicon interstitials created during the extrinsic base implantation, has been investigated for a non-selective SiGe HBT process. Devices with different designs of the extrinsic base region were fabricated, where some designs allowed part of the epitaxial base to be implanted with a high boron dose, hereby increasing the number of silicon interstitials close to the intrinsic device. These devices showed a marked degradation of DC characteristics and HF performance. 2D-device simulations were used to investigate the sensitivity in DC and HF parameters to vertical base profile changes. Good agreement was obtained between measured and simulated DC and HF characteristics.

  • 270.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Grahn, Jan V.
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Bipolar technology2016In: The VLSI Handbook: Second Edition, CRC Press , 2016, p. 1.3-1.25Chapter in book (Other academic)
  • 271.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Haralson, E.
    Johansson, T.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Self-heating effects in a BiCMOS on SOI technology for RFIC applications2005In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 52, no 7, p. 1423-1428Article in journal (Refereed)
    Abstract [en]

    Self-heating in a 0.25 mu m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In, the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.

  • 272.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Haralson, E.
    Suvar, E.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base2005In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 26, no 4, p. 246-248Article in journal (Refereed)
    Abstract [en]

    A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R-B was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity. of the Ni(SiGe:C) silicide layer was 24 mu Omega (.) cm. About 50-100 nm of lateral growth of silicide,. underneath the emitter pedestal was observed. DC and HF results with balanced f(T)/f(MAX) values of 41/42 GHz were demonstrated for 0.5 X 10 mu m(2) transistors.

  • 273.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Noise Properties of High-Mobility, 80 nm Gate Length MOSFETs on Supercritical Virtual Substrates2008In: SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES   : MATERIALS, PROCESSING, AND DEVICES / [ed] Harame D; Caymax M; Koester S; Miyazaki S; Rim K; Tillack B; Boquet J; Cressier J; Masini G; Reznicek A; Takagi S, 2008, Vol. 16, no 10, p. 529-537Conference paper (Refereed)
    Abstract [en]

    It was found that for strained Si channel layers of supercritical thickness oil relaxed SiGe virtual substrates, the 1/f noise oil,average is maintained at the same level as in unstrained devices. Short gate length nMOSFETs were analyzed statistically and the noise level variation, across a large number of samples, was similar in strained and unstrained devices. The obtained noise level variation was partly related to gate length fluctuations across the wafer, which was evident from a small V-T fluctuation.

  • 274.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Johansson, T.
    Arnborg, T.
    Norstrom, H.
    Grahn, J. V.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Implanted collector profile optimization in a SiGeHBT process2001In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 45, no 3, p. 399-404Article in journal (Refereed)
    Abstract [en]

    Optimization of implanted collector doping profiles for a high-speed, low-voltage SiGe HBT process has been investigated experimentally and by device simulations. A low-energy antimony implantation has been combined with a standard selectively implanted collector using phosphorous, to achieve improved control of the collector doping profile. The simulations indicate that the narrow n-type doping peak formed by the antimony implantation allows the cut-off frequency f(T) to be increased without degrading the collector emitter breakdown voltage BVCEO. The fabricated devices demonstrate a highest f(T) of 60 GHz. Depending on the collector profile BVCEO values between 1.5 and 2 V were obtained.

  • 275.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Comprehensive temperature modeling of strained epitaxial silicon-germanium alloy thermistors2009In: 2009 International Semiconductor Device Research Symposium, ISDRS '09, 2009, p. 5378337-Conference paper (Refereed)
  • 276.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ge-profile design for improved linearity of SiGe double HBTs2002In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 23, no 1, p. 19-21Article in journal (Refereed)
    Abstract [en]

    The influence of Ge-profile design on SiGe HBT linearity-harmonic distortion has been quantified using finite element physical device simulation. It was demonstrated that proper Ge-profile tailoring allows the linearity to be improved for both low- and high-current operation. High injection heterojunction barrier effects are shown to have a significant influence on the higher order harmonies. The influence of the Ge-profile design on linearity was found to be comparable to the influence from the epitaxial collector doping profile.

  • 277.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Mixed mode circuit and device simulation of RF harmonic distortion for high-speed SiGeHBTs2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 10, p. 1567-1571Article in journal (Refereed)
    Abstract [en]

    Mixed mode circuit and device simulation has been used to investigate the linearity properties-harmonic distortion of high-speed low voltage SiGe heterojunction bipolar transistors (HBTs). The simulation test-circuit included the active device, modeled by finite element simulation, as well as passive elements in a SPICE circuit for DC-feed and AC-coupling of the RF-signal. Different Ge-profiles for reduced harmonic distortion have been investigated and compared to a conventional high-speed graded Ge-profile. To find an optimized Ge-profile for RF-applications other figure-of-merits, such as maximum cut-off frequency and minimum noise figure were also simulated. Using the same mixed mode simulation approach the design of the epitaxial collector doping profile for high breakdown voltage, high cut-off frequency and reduced harmonic distortion was investigated.

  • 278.
    Malm, Bengt Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of dislocations on low frequency noise in nMOSFETs fabricated on tensile strained virtual substrates2007In: Noise and Fluctuations / [ed] Tacano, M; Yamamoto, Y; Nakao, M, 2007, Vol. 922, p. 133-136Conference paper (Refereed)
    Abstract [en]

    In this work sSi nMOSFETs with 13 run sSi thickness on 27% Ge virtual substrates (VS) are investigated and an increased LF noise level with a characteristic gate bias dependence is found. High off-state leakage of the MOSFETs indicates the presence of misfit dislocations in the channel region. A channel conductance based model is proposed to analyse the noise originating from a highly localized defect in the channel.

  • 279.
    Malm, Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Olyaei, Maryam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Low-frequency noise in FinFETs with PtSi Schottky-barrier source/drain contacts2011In: Proceedings of the IEEE 21st International Conference on Noise and Fluctuations, ICNF 2011, IEEE Computer Society, 2011, p. 135-138Conference paper (Refereed)
    Abstract [en]

    Schottky-barrier source/drain (SB-S/D) is a promising solution for low-resistive contact formation in fully depleted SOI ultra-thin body (UTB) FETs, or FinFETs. In this study the low-frequency noise of FinFETs and UTB-FETs, with platinum-silicide based source/drain contacts with low barrier height was characterized. The barrier height was tuned by means of segregation of implanted As or B. In the linear region of operation the noise power spectral density of devices with different barrier heights was not significantly affected for a given drain current. This suggests that channel noise dominates the behavior and that the low effective Schottky barrier height in dopant segregated devices does not introduce additional noise.

  • 280.
    Malm, Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Network analyzer measurements and physically based analysis of amplitude and phase distortion in SiGeC HBTs2005In: 2005 International Semiconductor Device Research Symposium, 2005, p. 74-75Conference paper (Refereed)
    Abstract [en]

    We have investigated the linearity of advanced SiGeC bipolar transistors for different bias and input power conditions. The SiGeC HBTs were fabricated in an advanced process, with low base resistance, a minimum emitter area of 10 × 0.4 μm2, and balanced fT/fMAX values of 40-50 GHz. The BVCEO is approximately 2 V. For RF integrated circuits the linearity, i.e. distortion is an important issue. Harmonic and intermodulation distortion in Si and SiGe bipolar transistors has been discussed by several authors from a modelling perspective. However, the experimental studies on high-performance SiGe devices are limited so far. In this work the RF harmonic distortion was characterized by a novel approach using a 2-port network analyzer with a frequency offset option for the receiver port. Both amplitude and phase distortion results could be obtained in a fast and efficient manner. At each port of the network analyzer the power and the phase of the signal (A/B) a reference (R1/R2) are available. When port 2 is tuned to the fundamental frequency the S-parameters are directly obtained and standard 12-term error correction techniques (SOLT/TRL) can be applied. In the case where the port 2 is tuned to another frequency only direct power measurements of A and B are possible and the response at the 2ND and 3RD harmonic frequency has to be adjusted for the attenuation between the DUT and the network analyzer ports using a thru-structure measurement. Figure 1. shows typical output vs. input power characteristics at a DC collector current I C close to peak RF-gain. Due to the relatively low VCE of 1 V saturation will influence both gain compression and linearity. Since the load and source impedance of 50 Ω is the same for the direct power and S-parameter measurements we can compare uncorrected gain and the gain calculated from the corrected S-parameters using |S21| 2. In Figure 2 it observed that the gain difference is 1 - 2 dB. The harmonic distortion vs. IC is shown in Fig. 3 for three different input power levels. Characteristic minima are observed in the 2ND harmonics at 4 mA and the third harmonic at 0.6 mA. Previous studies have indicated that this effect is caused by cancellation between different non-linear, bias dependent effects, such as the collector-base capacitance CBC and transit time τEC. The cancellation occurs due to the phase difference in the non-linear components. To examine this effect we have plotted the phase of the measured output signal at the fundamental and harmonic frequencies, as shown in Fig. 4. The phase of the fundamental shows an expected change at high current due to increased transit time caused by base push-out. The behaviour at the 2ND harmonic shows a drastic phase turn close to 4 mA, which corresponds neatly to the minimum in Fig 3. Since the phase is almost constant at lower IC this suggests that two separate effects dominate the 2ND harmonic at low and high IC respectively. The rapid phase turn is similar to a resonance and thus complete cancellation could occur for a specific current, given that no other non-linear effects were contributing. The minima in the power and the phase turn of the 3RD harmonic are mainly related to the derivative of the 2ND harmonic. The most important non-linear element in the transistor at high IC and VCE close to saturation is CBC, which can be extracted from the S-parameters after standard open-pad de-embedding. In Fig. 5 it is observed that CBC increases strongly for IC larger than 10 mA. As a result the non-linear current generated by CBC will change in both amplitude and phase. Finally, the phase difference between different non-linear effects in the transistor depends on the transit time τEC. The τEC of the SiGeC HBT can be obtained from the phase of S21. Figure 6 shows the change in τEC in for different input power levels. Under large signal conditions the minimum τEC is higher and starts to increase at a lower IC since the transistor is driven into saturation by the large output signal swing. In conclusion, the analysis, using a 2-port network analyzer, of the phase behaviour at harmonic frequencies is useful to find the origin of the distortion in the SiGeC bipolar device structure.

  • 281.
    Malm, Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Grahn, Jan
    Chalmers.
    Bipolar Technology2006In: VLSI Handbook / [ed] Wai-Kai Chen, CRC Press, 2006, 2Chapter in book (Other academic)
  • 282. Mehr, Wolfgang
    et al.
    Dabrowski, Jarek
    Scheytt, J. Christoph
    Lippert, Gunther
    Xie, Ya-Hong
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lupina, Grzegorz
    Vertical Graphene Base Transistor2012In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 33, no 5, p. 691-693Article in journal (Refereed)
    Abstract [en]

    We present a novel graphene-based-device concept for a high-frequency operation: a hot-electron graphene base transistor (GBT). Simulations show that GBTs have high current on/off ratios and high current gain. Simulations and small-signal models indicate that it potentially allows terahertz operation. Based on energy-band considerations, we propose a specific material solution that is compatible with SiGe process lines.

  • 283. Mitrovic, I. Z.
    et al.
    Althobaiti, M.
    Weerakkody, A. D.
    Sedghi, N.
    Hall, S.
    Dhanak, V. R.
    Chalker, P. R.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interface engineering of Ge using thulium oxide: Band line-up study2013In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 109, p. 204-207Article in journal (Refereed)
    Abstract [en]

    This paper investigates the band line-up and optical properties (dielectric function) of Tm2O3/Ge gate stacks deposited by atomic layer deposition. X-ray photoelectron spectroscopy has been performed to ascertain the shallow core levels (Ge3d and Tm4d) in ultra-thin and bulk Tm2O3/Ge stacks as well as valence band maxima in Ge and bulk Tm2O3. The valence band offset of Tm2O3/Ge has been found to be 2.95 +/- 0.08 eV. Vacuum ultra violet variable angle spectroscopic ellipsometry studies reveal the indirect band gap nature of Tm2O3, with the value extracted from the Tauc method of 5.3 +/- 0.1 eV. A distinct absorption feature is observed at similar to 3.2 eV below the band gap of Tm2O3, and clearly distinguished from the Si and Ge critical points. A dielectric constant of 14 to 15 has been derived from the electrical measurements on 5 nm Tm2O3/epi Ge/Si gate stacks. The band line-up study of Tm2O3/Ge implies an acceptable barrier for holes (2.95 eV) and electrons (greater than 1.7 eV) for Ge MOSFET engineering.

  • 284. Mitrovic, I. Z.
    et al.
    Althobaiti, M.
    Weerakkody, A. D.
    Sedghi, N.
    Hall, S.
    Dhanak, V. R.
    Mather, S.
    Chalker, P. R.
    Tsoutsou, D.
    Dimoulas, A.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Litta, Eugenio D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interface engineering routes for a future cmos ge-based technology2014In: ECS Transactions, 2014, no 2, p. 73-88Conference paper (Refereed)
    Abstract [en]

    We present an overview study of two germanium interface engineering routes, firstly a germanate formation via La2O3 and Y2O3, and secondly a barrier layer approach using Al2O3 and Tm2O3. The interfacial composition, uniformity, thickness, band gap, crystallinity, absorption features and valence band offset are determined using X-ray photoelectron spectroscopy, ultra violet variable angle spectroscopic ellipsometry, and high resolution transmission electron microscopy. The correlation of these results with electrical characterization data make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS.

  • 285. Mitrovic, I. Z.
    et al.
    Hall, S.
    Althobaiti, M.
    Hesp, D.
    Dhanak, V. R.
    Santoni, A.
    Weerakkody, A. D.
    Sedghi, N.
    Chalker, P. R.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. X-FAB Semiconductor Foundries AG, Germany.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tan, H.
    Schamm-Chardon, S.
    Atomic-layer deposited thulium oxide as a passivation layer on germanium2015In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 117, no 21, article id 214104Article in journal (Refereed)
    Abstract [en]

    A comprehensive study of atomic-layer deposited thulium oxide (Tm2O3) on germanium has been conducted using x-ray photoelectron spectroscopy (XPS), vacuum ultra-violet variable angle spectroscopic ellipsometry, high-resolution transmission electron microscopy (HRTEM), and electron energy-loss spectroscopy. The valence band offset is found to be 3.05±0.2eV for Tm2O3/p-Ge from the Tm 4d centroid and Ge 3p3/2 charge-corrected XPS core-level spectra taken at different sputtering times of a single bulk thulium oxide sample. A negligible downward band bending of ∼0.12eV is observed during progressive differential charging of Tm 4d peaks. The optical band gap is estimated from the absorption edge and found to be 5.77eV with an apparent Urbach tail signifying band gap tailing at ∼5.3eV. The latter has been correlated to HRTEM and electron diffraction results corroborating the polycrystalline nature of the Tm2O3 films. The Tm2O3/Ge interface is found to be rather atomically abrupt with sub-nanometer thickness. In addition, the band line-up of reference GeO2/n-Ge stacks obtained by thermal oxidation has been discussed and derived. The observed low reactivity of thulium oxide on germanium as well as the high effective barriers for holes (∼3eV) and electrons (∼2eV) identify Tm2O3 as a strong contender for interfacial layer engineering in future generations of scaled high-κ gate stacks on Ge.

  • 286.
    Moeen, Mahdi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammad Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Tehran, Iran.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Improved designs of Si-based quantum wells and Schottky diodes for IR detection2016In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 613, p. 19-23Article in journal (Refereed)
    Abstract [en]

    Novel structures of intrinsic or carbon-doped multi quantum wells (MQWs) and intrinsic or carbon-doped Si Schottky diodes (SD), individually or in combination, have been manufactured to detect the infrared (IR) radiation. The carbon concentration in the structures was 5 × 1020 cm− 3 and the MQWs are located in the active part of the IR detector. A Schottky diode was designed and formed as one of the contacts (based on NiSi(C)/TiW) to MQWs where on the other side the structure had an Ohmic contact. The thermal response of the detectors is expressed in terms of temperature coefficient of resistance (TCR) and the quality of the electrical signal is quantified by the signal-to-noise ratio. The noise measurements provide the K1/f parameter which is obtained from the power spectrum density. An excellent value of TCR = − 6%/K and K1/f = 4.7 × 10− 14 was measured for the detectors which consist of the MQWs in series with the SD. These outstanding electrical results indicate a good opportunity to manufacture low cost Si-based IR detectors in the near future.

  • 287.
    Moeen, Mahdi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Abedin, Ahmad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Enhanced device designs for Si-based infrared detectors2015In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118Article in journal (Other academic)
  • 288.
    Moeen, Mahdi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Combined Si Schottky barriers and SiGe/Si multi quantum wells for infrared detection2011In: Int. Semicond. Device Res. Symp., ISDRS, 2011Conference paper (Refereed)
    Abstract [en]

    Un-cooled bolometer arrays have been considered as good choices for detection of infrared waves in the ranges of 3-5m (MWIR: mid wavelength infrared) and 8-12m (LWIR: long wavelength infrared). Advantages are found in their relative simplicity of mechanism and design, hence, fabrication cost, when compared to detectors working based on photon detection mechanisms. A temperature dependent resistor (or thermistor) is the core element of a bolometer. The rate of resistance dependency to temperature is a figure-of-merit for thermistor material, acting as the active element in a bolometer. This property is characterized by temperature coefficient of resistance (TCR). At the same time, for the better IR detection and imaging quality, high signal-to-noise ratio (SNR) is also sought. Different materials have been proposed and/or implemented commercially to work as thermistor materials. Among them are VOx, amorphous silicon, amorphous and poly SiGe.

  • 289.
    Moeen, Mahdi
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, M.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of SiGe/Si multi-quantum wells for infrared sensing2013In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 103, no 25, p. 251609-Article in journal (Refereed)
    Abstract [en]

    SiGe epitaxial layers are integrated as an active part in thermal detectors. To improve their performance, deeper understanding of design parameters, such as thickness, well periodicity, quality, and strain amount, of the layers/interfaces is required. Oxygen (2-2500 × 10-9 Torr) was exposed prior or during epitaxy of SiGe/Si multilayers. In this range, samples with 10 nTorr oxygen were processed to investigate layer quality and noise measurements. Temperature coefficient of resistance was also measured to evaluate the thermal response. These results demonstrate sensitivity of SiGe-based devices to size and location of defects in the structure.

  • 290. Moller, P.
    et al.
    Fredenberg, M.
    Dainese, M.
    Aronsson, C.
    Leisner, P.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Metal printing ECPR of copper interconnects down to 500 nm using - Electrochemical pattern replication2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 09-apr, p. 1410-1413Article in journal (Refereed)
    Abstract [en]

    Printing of copper patterns with dimensions from 100 mu m down to 500 nm lines and 280 run space was demonstrated using electrochemical pattern replication with a master electrode (template) having a pattern depth of 2500 nm. SEM measurements were done to measure the mean line width as well as CD variations on the master and the replicated copper lines. It was found that accurate replication of 500 nm thick metal patterns was enabled by the process and that CD variations in the master were dominating compared to the variations introduced by the electrochemical pattern transfer itself.

  • 291. Nagatsuma, H.
    et al.
    Kuroki, S. I.
    de Silva, M.
    Ishikawa, S.
    Maeda, T.
    Sezaki, H.
    Kikkawa, T.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Michael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    4H-SiC nMOSFETs with As-Doped S/D and NbNi silicide ohmic contacts2016In: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015, Trans Tech Publications Ltd , 2016, p. 573-576Conference paper (Refereed)
    Abstract [en]

    4H-SiC nMOSFETs with As-doped S/D and NbNi silicide ohmic contacts were demonstrated for radiation-hard CMOS electronics. The threshold voltage Vth was designed to be 3.0 V by TCAD simulation, and was 3.6 – 3.8 V at the fabricated devices. On / off ratio was approximately 105.

  • 292.
    Naiini, Maziar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    ALD high-k layer grating couplers for single and double slot on-chip SOI photonics2011In: 41st European Solid-State Device Research Conference, ESSDERC 2011, 2011, p. 191-194Conference paper (Refereed)
    Abstract [en]

    State of the art grating couplers for horizontal single and double slot waveguides are presented; in these devices the input signal is transmitted from a single mode optical fiber to silicon on insulator slot waveguides. In the waveguides, atomic layer deposited (ALD) high-k dielectrics form the low refractive index slot. It is demonstrated that the new fully etched design combined with precision of ALD result in highly reproducible devices with efficiency variations less than 1%. Devices have a peak coupling efficiency of 24% at 1.55 &#x03BC;m. In order to achieve the optimal design, optical properties of high-k films are studied with spectroscopic ellipsometry. Measured refractive indices show variations from reference values, originated from film densities.

  • 293.
    Naiini, Maziar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Low loss high-k slot waveguides for silicon photonics2013In: Dev. Res. Conf. Conf. Dig., IEEE conference proceedings, 2013, p. 95-96Conference paper (Refereed)
    Abstract [en]

    Silicon photonic integrated circuits are promising solutions for high speed on-chip data communication. Producing crystalline silicon optical waveguides at the backend of the IC process flow requires wafer-bonding and a deep substrate etching of an SOI wafer. Fabrication of optical interconnects is less complex and more cost effective if deposited amorphous silicon can be used instead. Amorphous silicon on the other hand suffers from a high absorption. Slot waveguide is a suitable solution for integration of alternative materials with silicon waveguides. Active devices with slot waveguides have been reported by Ramirez et al where the slot layer is doped with rare-earth metals to generate light. In this work successful fabrication and characterization of CMOS compatible low loss high-k amorphous silicon slot waveguides is reported.

  • 294.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    ALD high-k layer grating couplers for single and double slot on-chip SOI photonics2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 58-63Article in journal (Refereed)
    Abstract [en]

    State of the art grating couplers for horizontal single and double slot waveguides are presented; in these devices the input signal is transmitted from a single mode optical fiber to silicon on insulator slot waveguide. In the waveguides, atomic layer deposited (ALD) high-k dielectrics form the low refractive index slot. It is demonstrated that a fully etched design combined with precision of ALD result in highly reproducible devices with theoretical efficiency variations less than 1%. Devices have a peak calculated coupling efficiency of 24% at 1.55 mu m. In order to achieve an optimal design, optical properties of high-k films are studied by spectroscopic ellipsometry. Measured refractive indices show variations from reference values, originated from film variation in densities. Chips with a test slot material are fabricated and the optical efficiency of the couplers is characterized. The maximum measured coupling efficiency of the couplers is 18.5%.

  • 295.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    CMOS compatible ALD high-k double slot grating couplers for on-chip optical interconnects2012In: Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European, IEEE , 2012, p. 93-96Conference paper (Refereed)
    Abstract [en]

    Silicon-on-insulator(SOI) novel on-chip grating couplers for double slot high-k waveguides are experimentally demonstrated. The devices were fabricated with standard CMOS process technology. The grating couplers were designed for the best performance at the C-band communication range. Two thin layers of aluminum oxide formed the slot region of the waveguide. The high-k layers were deposited using the atomic layer deposition (ALD) method. A reliable process was realized by etching the structures to the buried oxide. Effect of the top oxide cladding layer on the efficiency was studied. The grating couplers had a measured efficiency of 22% at 1.55μm wavelength. This efficiency is competitive to other results reported by other groups.

  • 296.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Double slot high-k waveguide grating couplers for silicon photonics2012In: Device Research Conference (DRC), 2012 70th Annual, IEEE , 2012, p. 69-70Conference paper (Refereed)
    Abstract [en]

    Novel on-chip double slot high-k waveguide grating couplers have been successfully fabricated, and characterized. Silicon cannot yet be directly used for light generation and modulation in photonic devices because of its weak nonlinear optical effects. Slot waveguide is a solution to this problem, this structure consists of silicon and low refractive index material layers as the active material[1, 2]. Previously, grating couplers were demonstrated for horizontal single slot SiO 2 waveguides [3, 4]. Double slot waveguide is of great interest since the confinement of the optical power in the active material is significantly larger. Atomic layer deposited (ALD) high-k aluminum oxide (Al 2O 3) was used as the slot layer because of a superior layer quality and thickness uniformity. The ultimate goal of this work is the demonstration of the highly reproducible on-chip photonic devices.

  • 297.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integrating 3D PIN germanium detectors with high-k ALD fabricated slot waveguides2014In: ULIS 2014 - 2014 15th International Conference on Ultimate Integration on Silicon, IEEE Computer Society, 2014, p. 45-48Conference paper (Refereed)
    Abstract [en]

    A novel device technology for photonics integrated circuits (PICs) is presented. In this work germanium PIN photodetectors are embedded in back-end deposited high-k slot waveguides. The waveguides are fabricated using chemical vapor deposited amorphous silicon and atomic layer deposition of Al 2O3 thin films. The germanium PIN stack is selectively grown on a bulk silicon substrate. The detectors are butt coupled to the slot waveguides. Using our selective germanium growth and interconnect technology we study a 3D multilayer photonic integration for CMOS back-end of the line (BEOL) process. Finally we demonstrate the fabrication of a photonic chip deploying this technology platform.

  • 298.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    University of Siegen, Germany .
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Embedded Graphene Photodetectors for Silicon Photonics2014In: Device Research Conference (DRC), 2014 72nd Annual, IEEE conference proceedings, 2014, p. 43-44Conference paper (Refereed)
    Abstract [en]

    Graphene has extraordinary electronic and optoelectronic properties such as high carrier mobility, large charge-carrier concentrations, tunability via electrostatic doping, wavelength-independent absorption, and relatively low dissipation rates [1]. The combination of its electro-optical properties with its manufacturability and CMOS integrability makes graphene an extremely promising candidate for active photonic devices [2,3]. Because of its two-dimensional appearance, graphene has a limited light absorption, which is not enough to fulfill the requirements of silicon photonics technology. Recently, the integration of graphene with silicon waveguides [4,5] has been shown for on-chip applications [6]. In these solutions graphene is placed on top and outside of the waveguide yielding only limited light-graphene interaction. We introduce novel photo-detector architecture by embedding CVD-graphene inside the slot layer of deposited high-k slot waveguides that are compatible with back-end-of-the-line manufacturing of photonic integrated circuits (PICs). This approach leads to a high light-graphene interaction due to the high mode concentration in the slot region[7]. This results in enhanced absorption and enables a very compact photodetector design.

  • 299.
    Naiini, Maziar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fully etched grating couplers for atomic layer deposited horizontal slot waveguides2011In: 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011, 2011, p. 126-129Conference paper (Refereed)
    Abstract [en]

    Compact broadband grating couplers are designed and studied utilizing Atomic Layer Deposited Horizontal Slot waveguides, with four well-known material layers as the slot. Fabrication process conditions are experimentally studied to obtain more optimized designs. With the precision of the film thickness and refractive index provided by ALD, fabrication of reproducible grating couplers is feasible. An overview of design guidelines regarding the slot size and slot material is provided by 2D Finite Element Method calculations.

  • 300. Nawaz, M.
    et al.
    Zaring, C.
    Bource, J.
    Schupbach, M.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, H. -S
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Assessment of High and Low Temperature Performance of SiC BJTs2009In: SILICON CARBIDE AND RELATED MATERIALS 2008, STAFA-ZURICH: TRANS TECH PUBLICATIONS LTD , 2009, Vol. 615-617, p. 825-828Conference paper (Refereed)
    Abstract [en]

    This paper addresses the performance of SiC NPN Bipolar Junction Transistors (BJTs) at high and low temperature. A current gain of 50 at room temperature was obtained which decreases to 25 at 275 degrees C. A maximum current gain (beta) of 111 has been reported at -86 degrees C. At low temperature (below -86 degrees C), the current gain drops rapidly because of carrier freezout effect. At room temperature, a minimum on-resistance of 7 m Omega-cm(2) was obtained. This increases to 28 m Omega-cm(2) at 275 degrees C. The on-resistance of BJTs is approximately unaffected by lowering the temperature down to -86 degrees C front room temperature. Below -86 degrees C, the on-reststance JUMPS up rapidly because of carrier freezeout. Electrical performance of BJTs have been fairly stable during stress measurement at high temperature (120 hours at 100 degrees C) at a collector bias of 1000V (with open base) for devices with a breakdown voltage of 1200VA. The devices have been stressed further at low (i.e., 6) and high gain (i.e., 15) at room temperature. Initial degradation within first hour of stress test has been reported and then degradation stabilizes out. Packaged devices were tested Lip to 550 degrees C and performed admirably well up to that temperature.

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