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  • 251.
    Latif, K.
    et al.
    University of Turku and Turku Centre for Computer Science (TUCS).
    Rahmani, Amir Mohammad
    University of Turku and Turku Centre for Computer Science (TUCS).
    Guang, Liang
    University of Turku.
    Seceleanu, Tiberiu
    ABB Corporate Research.
    Tenhunen, Hannu
    University of Turku and Turku Centre for Computer Science (TUCS).
    PVS-NoC: Partial Virtual Channel Sharing NoC Architecture2011Inngår i: Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011, IEEE , 2011, s. 470-477Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead. We propose sharing the VC buffers among dual inputs, which provides the performance advantage as conventional VC-based router with minimized overhead. We reason theoretically and demonstrate quantitatively the benefits of proposed architecture by comparing to state-of-the-art NoC routers, with various traffic patterns. Extensive experiments with synthetic and real benchmarks show significant area and power saving with similar performance compared to latest VC based NoC architectures.

  • 252.
    Latif, K.
    et al.
    Turku Centre for Computer Science (TUCS) and University of Turku.
    Rahmani, Amir Muhammad
    Turku Center for Computer Science (TUCS) and University of Turku.
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS) and University of Turku.
    Tenhunen, Hannu
    Turku Centre for Computer Science (TUCS) and University of Turku.
    Seceleanu, T.
    ABB Corporate Research.
    A Cluster-Based Core Protection Technique for Networks-on-Chip2012Inngår i: Proceedings International Computer Software & Applications Conference, 2012, s. 360-361Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, a cluster based processing core protection technique for NoC systems using PVS approach is presented. In case of network level faults, the processing core of faulty node can use any other router in the cluster for transmission or reception of data packets with proposed architecture. Simulation results show significant reduction in average packet latency at the expense of negligible area overhead.

  • 253.
    Latif, K.
    et al.
    University of Turku and Turku Centre for Computer Science (TUCS).
    Rahmani, Amir Muhammad
    University of Turku and Turku Centre for Computer Science (TUCS).
    Seceleanu, T.
    Mälardalen University and ABB Corporate Research.
    Tenhunen, Hannu
    University of Turku and Turku Centre for Computer Science (TUCS).
    Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy2012Inngår i: Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012, 2012, s. 34-41Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, we present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5X6 crossbar is used for the proposed architecture which requires one more 5X1 multiplexer without increasing the critical path delay of the router as compared to the 5X5 crossbar. The proposed router has been simulated for uniform and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

  • 254.
    Latif, K.
    et al.
    University of Turku.
    Rahmani, Amir
    University of Turku.
    Vaddina, K. R.
    University of Turku.
    Seceleanu, T.
    University of Turku.
    Liljeberg, P.
    University of Turku.
    Tenhunen, Hannu
    University of Turku.
    Enhancing Performance of NoC-Based Architectures Using Heuristic Virtual-Channel Sharing Approach2011Inngår i: 2011 35TH IEEE ANNUAL INTERNATIONAL COMPUTER SOFTWARE AND APPLICATIONS CONFERENCE (COMPSAC), IEEE Computer Society, 2011, s. 442-447Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a novel virtual-channel (VC) sharing technique for NoC architecture. The proposed architecture improves the utilization of resources to enhance the performance with minimal overheads. A heuristic approach towards the proper VC sharing strategy is proposed, which is performed by an adaptive algorithm that configures the VC sharing based on link load parameters. Architectural design to realize the adaptive VC sharing in generic router is elaborated. The technique can be applied to any NoC architecture, including 3-D NoCs. Extensive quantitative experiments with synthetic and real benchmarks, including an integrated video conference application, demonstrate considerable improvement in area and power efficiency compared to existing VC-based 2D/3D NoC architectures.

  • 255.
    Latif, K.
    et al.
    University of Turku and Turku Centre for Computer Science (TUCS).
    Rahmani, Amir-Muhammad
    University of Turku and Turku Centre for Computer Science (TUCS).
    Nigussie, E.
    University of Turku.
    Tenhunen, Hannu
    University of Turku and Turku Centre for Computer Science (TUCS).
    Seceleanu, T.
    ABB Corporate Research.
    A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip2011Inngår i: Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on, IEEE Computer Society, 2011, s. 454-462Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We present the partial virtual-channel sharing (PVS) NoC architecture which reduces the impact of fault on system performance and can also tolerate the faults on routing logic. A fault in one component makes the fault-free connected components out of use and this in turn leads to considerable performance degradation. Improving utilization of resources is a key to either enhance or sustain performance with minimal overheads in case of fault or overloading. In the proposed architecture autonomic virtual-channel buffer sharing is implemented. The runtime allocation of the buffers depends on incoming load and fault occurrence. This technique can be used in any NoC topology and for both 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate significant reduction in average packet latency compared to existing VC-based NoC architecture. Extensive quantitative simulation results for synthetic benchmarks are also carried out. Furthermore, the simulation results reveal that the PVS architecture improves the performance significantly under fault free conditions compared to other VC architectures.

  • 256.
    Latif, K.
    et al.
    University of Turku and Turku Centre for Computer Science (TUCS).
    Rahmani, Amir-Muhammad
    University of Turku and Turku Centre for Computer Science (TUCS).
    Seceleanu, T.
    ABB Corporate Research.
    Tenhunen, Hannu
    University of Turku and Turku Centre for Computer Science (TUCS).
    Power- and performance-aware IP mapping for NoC-based MPSoC platforms2010Inngår i: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, 2010, s. 758-761Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we address the performance of MPSoC platforms with homogeneous processing nodes, where the cores generate and consume the large amount of data, thus the system approaches congestion. Mostly, the time dependent media applications are time critical, where traffic must be delivered on time in order to operate properly. Proper task allocation or placement of IP cores at layout time is very important to meet such application requirements. Apart from meeting the application requirements, it also lowers the traffic congestion, power consumption and Average Packet Latency (APL). For task allocation or IP placement, the prioritization criteria has been proposed, which is used in next step to map the application on MPSoC platform. The proposed technique shows significant improvement in system performance and reduction in power consumption. To estimate the efficiency, the video conference encoding application and MPEG4 video encoder were mapped to 5x5 and 4x4 NoC mesh. Up to 11% reduction in power consumption and 20% reduction in APL has been observed as compared to other proposed mapping techniques.

  • 257. Latif, K.
    et al.
    Seceleanu, T.
    Seceleanu, C.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Resource-aware task allocation and scheduling for SegBus platform2010Inngår i: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, 2010, s. 523-526Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this work, we propose an integrated task allocation and scheduling mechanism to minimize the resource contention and the processing latency for application running on the SegBus platform. The transactions are classified as local and cross border SPLIT transactions. The hybrid scheduling approach implemented by hierarchal arbiter code structure shows significant improvement in system performance. The interrupt scheduling has been implemented to further enhance system performance. A H.264 video encoder application has been used to verify the proposed technique, showing a large improvement in system throughput.

  • 258. Latif, K.
    et al.
    Seceleanu, T.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers2010Inngår i: Proceedings of the 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, ECBS 2010, IEEE , 2010, s. 131-138Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.

  • 259. Latif, K.
    et al.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Seceleanu, T.
    Application specific IP placement for on-chip distributed architectures2009Inngår i: 2009 NORCHIP, 2009, s. 1-4Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper we approach the performance aspects of MPSoC platforms, from the point of view of IP placement with the focus on Network-on-Chip(NoC). Proper IP placement is important for several time-dependent applications such as video and voice where traffic must be delivered on time in order to operate properly. Proper placement of IPs can lower the traffic congestion, improve overall execution time and power consumption. We have suggested a new criteria for the prioritization of IPs regarding placement. Based on that criteria, we implemented an algorithm for IP placement.The running example is represented by mapping of H.264 encoder application on a NoC mesh. Allocation of processing elements on the platform, topology and communication mechanism are the main topics described here.

  • 260. Latif, K.
    et al.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Seceleanu, T.
    Multicast protocol for SegBus platform2009Inngår i: 2009 NORCHIP, 2009, s. 1-6Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The task is to analyze, how different services can be designed for the SegBus multiprocessor platform and observe the improvement in system performance. In this paper, we utilize the concept of broadcasting and multicasting service from standard data bus for multiprocessor systems to enhance the performance of SegBus platform. The running example is represented by the H.264 encoder. The SegBus platform architecture, the communication mechanism, the arbitration scheme, the allocation of processing elements on the platform, and the broadcasting services and their implementation are the main topics analyzed here.

  • 261.
    Latif, Khaled
    et al.
    University of Turku and Turku Centre for Computer Science (TUCS).
    Rahmani, Amir-Mohammad
    University of Turku and Turku Centre for Computer Science (TUCS).
    Vaddina, K. R.
    University of Turku and Turku Centre for Computer Science (TUCS).
    Seceleanu, Tiberiu
    ABB Corporate Research.
    Liljeberg, P.
    University of Turku.
    Tenhunen, Hannu
    University of Turku.
    Enhancing performance sustainability of fault tolerant routing algorithms in NoC-based architectures2011Inngår i: Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, 2011, s. 626-633Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Reliability of embedded systems and devices is becoming a challenge with technology scaling. To deal with the reliability issues, fault tolerant solutions are needed. The design paradigm for future System-on-Chip (SoC) implementation is Network-on-Chip (NoC). Fault tolerance in NoC can be achieved at many abstraction levels. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. In this paper, we propose a NoC architecture, which sustains the overall system performance by utilizing resources, which cannot be used by other architectures under faults. An approach towards a proper virtual-channel (VC) sharing strategy is proposed, based on communication bandwidth requirements. The technique can be applied to any NoC architecture, including 3-D NoCs. Extensive quantitative experiments with synthetic benchmarks, including uniform, transpose and negative exponential distribution (NED), demonstrate considerable improvement in terms of performance sustainability under faulty conditions compared to existing VC-based NoC architectures.

  • 262.
    Latif, Khalid
    et al.
    University of Turku, Finland.
    Rahmani, Amir-Mohammad
    University of Turku, Finland.
    Seceleanu, Tiberiu
    University of Turku, Finland.
    Tenhunen, Hannu
    University of Turku, Finland.
    A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip2011Inngår i: Proc. NORCHIP, IEEE , 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A fault in one component of Networks-on-Chip (NoC) based system makes the fault-free connected units out of use and this in turn leads to considerable performance degradation. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. It is indispensable step needed to be taken in order to implement the reliable on-chip systems especially with nano-scale technologies. In this paper, we present a technique to recover healthy processing elements for NoC architectures in case of associated routers failure by using the Partial Virtual-Channel Sharing (PVS) approach. The proposed architecture divides the network into cluster regions, where each cluster comprises of two nodes. Each node in a cluster provides a backup data-path for other node in the cluster. Each processing element can use the backup data-path to transmit and receive the packets in case of corresponding router failure. The simulation results show that the proposed architecture has low hardware overheads.

  • 263.
    Latif, Khalid
    et al.
    Turku Centre for Computer Science (TUCS).
    Rahmani, Amir-Mohammad
    Turku Centre for Computer Science (TUCS).
    Vaddina, Kameswar Rao
    Turku Centre for Computer Science (TUCS).
    Seceleanu, Tiberiu
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Processing Element Core Protection Using PVS-NoC Architecture2012Inngår i: Work in Progress Session of the Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (WiP-PDP'12), 2012, s. 21-22Konferansepaper (Fagfellevurdert)
  • 264.
    Lazraq, Tawfiq
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    FPGA Basic ATM Traffic Shaper for Event-Building Networks1995Inngår i: Annual IEEE International ASIC Conference and Exhibit, 1995, s. 177-180Konferansepaper (Fagfellevurdert)
  • 265.
    Lazraq, Tawfiq
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Östman, Fredrik
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    ATM Switching System Performance Analysis via Modelling and Simulation1994Inngår i: Proceedings of SIMS, 1994, s. 326-332Konferansepaper (Fagfellevurdert)
  • 266.
    Li, B. X.
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A second order multi-bit Sigma Delta modulator with single-bit feedback2004Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, nr 1, s. 63-72Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 mum CMOS process, achieving 82 dB dynamic range at OSR 128 and a peak SNDR of 73.1 dB.

  • 267. Li, B. X.
    et al.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Design of semi-uniform quantizers and their application in sigma delta A/D converters2004Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, nr 03-feb, s. 253-267Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper a new type of non-uniform quantizer, semi-uniform quantizer, is introduced. A k-bit semi-uniform quantizer uses the thresholds defined by a (k+1)-bit uniform quantizer and arranges them in such a way that small-amplitude inputs will be quantized by small quantization steps and large-amplitude inputs by large quantization steps. Therefore the total quantization error power could be reduced and the modulator's dynamic range could be increased by 1-bit. The condition for a semi-uniform quantizer to achieve a better performance than a uniform quantizer is analyzed and verified using a second order 3-bit sigma delta modulator prototype chip, fabricated in 0.35 mum CMOS process. At 32 x oversampling ratio the modulator achieves 81 dB dynamic range and 63.8 dB peak SNDR with 3-bit semi-uniform quantizer. With 3-bit uniform quantizer the dynamic range is 70 dB and the peak SNDR is 54.1 dB.

  • 268.
    Li, Li
    et al.
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    A high-linearity SiGe mixer ICs for 5-6GHz wireless applications2004Inngår i: 2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, NEW YORK: IEEE , 2004, s. 193-196Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A high-linearity SiGe monolithic downconversion mixer for 5-6GHz wireless applications is implemented. The mixer offers a high-linearity thanks to taking the MIROMIXER topology with an inductive degeneration transconductance stage. IM3 products are largely cancelled so as to exhibit the state-of-the-art high input IP3. The performances of the mixer are 5.8dBm input 1P(3), -7dBm 1-dB compression point, 6.8dB conversion power gain and 12.9dB noise figure, respectively. Its power consumption is only 8.7mW from a single 3V power supply. The chip size is 991 x 989 mum(2).

  • 269.
    Liu, Jian
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Weerasekera, Roshan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Exploration of autonomous error-tolerant (AET) celluar networks in system-on-a package (SoP) for future nanoscle electronic systems2006Inngår i: 2006 INTERNATIONAL CONFERENCE ON INDUSTRIAL AND INFORMATION SYSTEMS, VOLS 1 AND 2, NEW YORK: IEEE , 2006, s. 93-98Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a Nanocore/CMOS Hybrid System-on-Package (SoP) architecture that is suitable for any emerging nanotechnology. It combines the high density of nanoscale devices and some excellent properties of current CMOS technology including high voltage gain and interconnection bandwidth and speed. The local computing cell is autonomous and error-tolerant (AET cell), interconnected with nearest neighbors through crossbar interconnect arrangement. Some key issues are studied in more detail: a possible communication network adopting time-division-multiplexing scheme; power distribution network; sensor and control network.

  • 270.
    Liu, Jian
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Weerasekera, Roshan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Nano scale autonomous error-tolerant (AET) cellular network2005Inngår i: 2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings, 2005, s. 748-752Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, the nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture, which integrates today's mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits. The overall network is homogenous. These imply strict constraints for intercellular connection schemes and routing policies. Depending on the communication requirement between two nodes, different routing methods apply.

  • 271.
    Liu, Jian
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Weerasekera, Roshan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Nanocore/CMOS hybrid system-on-package (SoP) architecture for autonomous error-tolerant (AET) cellular array network2005Inngår i: 2005 5th IEEE Conference on Nanotechnology, 2005, s. 353-356Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, the nanocore/CMOS hybrid system-on-package (SoP) autonomous error-tolerant (AET) cellular network architecture, which integrates today’s mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits in a silicon platform. The overall network is homogeneous. These imply strict constraints for intercellular connection schemes and routing policies. Depending on the communication requirement between two nodes.

  • 272.
    Liu, Jian
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A circuit-switched network architecture for network-on-chip2004Inngår i: IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, NEW YORK: IEEE , 2004, s. 55-58Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a circuit-switched network architecture for Network-on-Chip. It uses time-division-multiplexing (TDM) scheme to realize the circuits. The global routing (slot assignment) is done centrally, while the slot mapping is done locally by the switches. The switches support multicast operation, which enables multicast traffic. Furthermore, the delay in the network is predictable before a circuit is established and in-order data delivery is guaranteed.

  • 273.
    Liu, Jian
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Global routing for multicast-supporting TDM network-on-chip2004Inngår i: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi, J; Takala, J; Hamalainen, TD, NEW YORK: IEEE , 2004, s. 17-20Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents a circuit-switched network architecture for Network-on-Chip. It uses the time-division-multiplexing (TDM) scheme to realize the circuits. The global routing (slot assignment at each switch) is done centrally, while the slot mapping is done locally by the switches. The switches support multicast operation, which enables multicast traffic. Furthermore, the delay in the network is predictable before a circuit is established and in-order data delivery is guaranteed

  • 274.
    Liu, Jian
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Interconnect intellectual property for Network-on-Chip (NoC)2004Inngår i: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 50, nr 2-3, s. 65-79Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation Conference, 2001, Proceedings, p. 684; Network on chip: an architecture for billion transistor era, in: Proceeding of the IEEE NorChip Conference, November 2000; Network on chip, in: Proceedings of the Conference Radio vetenskap och Kommunication, Stockholm, June 2002]. NoC uses Interconnect Intellectual Property (IIP) to connect different resources. Within an IIP, the switch has the central function. Depending on the network core of the NoC, the switch will have different architectures and implementations. This paper first briefly introduces the concept of NoC. It then studies NoC from an interconnect point of view and makes projections on future NoC parameters. At last, the IIP and its components are described, the switch is studied in more detail and a time-space-time (TST) switch designed for a circuit switched time-division multiplexing (TDM) NoC is proposed. This switch supports multicast traffic and is implemented with random access memory at the input and output. The input and output are then connected by a fully connected interconnect network.

  • 275.
    Ma, Ning
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Pang, Zhibo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Chen, Jun
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A 5Mgate/414mW Networked Media SoC in 0.13um CMOS with 720p Multi-Standard Video Decoding2009Inngår i: 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), IEEE Solid-State Circuits Society, 2009, s. 385-388Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet network interface and coarse-grained configurable video decoding unit. Real-time 1280x720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with core size of 6.4mm * 6.4mm. To achieve low power design, flexible power management strategy is implemented for dynamically control of computational capabilities with various workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280x720@25fps) video streams are decoded. When the SoC decodes real-time CIF (352x288@25fps) video streams, it requires 27MHz system frequency and consumes 95mW.

  • 276.
    Ma, Ning
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Pang, Zhibo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    An ASIC-Design-Based Configurable SOC Architecture for Networked Media2008Inngår i: 2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi J, Takala J, Vainio O, NEW YORK: IEEE , 2008, s. 41-44Konferansepaper (Fagfellevurdert)
    Abstract [en]

    An ASIC-design-based configurable SOC architecture, which is high performance, flexible, programmable, and compiler-independent, is designed for networked media applications. A coarse-grained parallel computing mechanism is employed in this architecture. Mapping this architecture to a specific application is demonstrated through an example in multimedia application. The design is validated in a powerful FPGA, consisting of two CPUs, working at 81MHz and five function units, working at 40.5MHz.

  • 277. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A Flexible Register Access Control for Programmable Protocol Processors2001Inngår i:  , 2001Konferansepaper (Fagfellevurdert)
  • 278. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A Group of Subword Instructions and Design Issues for Network Processing RISC Cores2003Inngår i:  , 2003Konferansepaper (Fagfellevurdert)
  • 279. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A Programmable Protocol Processor Architecture for High Speed Internet Protocol Processing2000Inngår i:  , 2000Konferansepaper (Fagfellevurdert)
  • 280. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A Simple Transition Control for FSM Programmable Protocol Processors2000Inngår i:  , 2000Konferansepaper (Fagfellevurdert)
  • 281. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Load/Store Unit Design of a Programmable Internet Protocol Processor2002Inngår i:  , 2002Konferansepaper (Fagfellevurdert)
  • 282. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Two special register addressing modes for internet protocol processing2002Inngår i:  , 2002Konferansepaper (Fagfellevurdert)
  • 283.
    Maguire Jr., Gerald Q.
    et al.
    KTH, Tidigare Institutioner, Teleinformatik.
    Ottersten, Björn
    KTH, Tidigare Institutioner, Signaler, sensorer och system.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zander, Jens
    KTH, Tidigare Institutioner, Teleinformatik.
    Future Wireless Computing & Communications1994Inngår i: NRS-Seminarium Radiokommunikationsnät Konferensdokumentation, 1994, s. 57-61Konferansepaper (Fagfellevurdert)
    Abstract [en]

    With the advent of mass produced cellular telephony, wireless communication is about to revolutionize the way we think about information systems. In the near future it is generally believed that entertainment, personal computing and communication industries will merge and that the organizations and consumers will demand their services `on the move´. This paper will address how new technologies will enable future mobile distributed computing and communication systems and discuss what their impact may be on the behavior of users and their organizations. We will focus on some important trends in future mobile[21] and wearable/implantable computing[10]. Some of the limiting factors and key research and engineering problems are outlined. This paper demonstrates that future wireless applications and systems have to cope with a wide variety of heterogenous infrastructures ranging from short range local area high speed (100Mbit/s) systems to low speed long range and wide area satellite based systems.

  • 284. Majd, Amin
    et al.
    Abdollahi, Mandi
    Sahebi, Golnaz
    Abdollahi, Davoud
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Plosila, Juha
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik. Univ Turku, Finland.
    Multi-Population Parallel Imperialist Competitive Algorithm for Solving Systems of Nonlinear Equations2016Inngår i: 2016 INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS 2016), IEEE, 2016, s. 767-775Konferansepaper (Fagfellevurdert)
    Abstract [en]

    the widespreadimportance of optimization and solving NP-hard problems, like solving systems of nonlinear equations, is indisputable in a diverse range of sciences. Vast uses of non-linear equations are undeniable. Some of their applications are in economics, engineering, chemistry, mechanics, medicine, and robotics. There are different types of methods of solving the systems of nonlinear equations. One of the most popular of them is Evolutionary Computing (EC). This paper presents an evolutionary algorithm that is called Parallel Imperialist Competitive Algorithm (PICA) which is based on a multi population technique for solving systems of nonlinear equations. In order to demonstrate the efficiency of the proposed approach, some well-known problems are utilized. The results indicate that the PICA has a high success and a quick convergence rate.

  • 285. Majd, Amin
    et al.
    Sahebi, Golnaz
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System. Univ. of Turku, Finland.
    Plosila, Juha
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik. University of Turku, Finland.
    Placement of Smart Mobile Access Points in Wireless Sensor Networks and Cyber-Physical Systems using Fog Computing2016Inngår i: Proceedings - 13th IEEE International Conference on Ubiquitous Intelligence and Computing, 13th IEEE International Conference on Advanced and Trusted Computing, 16th IEEE International Conference on Scalable Computing and Communications, IEEE International Conference on Cloud and Big Data Computing, IEEE International Conference on Internet of People and IEEE Smart World Congress and Workshops, UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld 2016Proceedings - 13th IEEE International Conference on Ubiquitous Intelligence and Computing, 13th IEEE International Conference on Advanced and Trusted Computing, 16th IEEE International Conference on Scalable Computing and Communications, IEEE International Conference on Cloud and Big Data Computing, IEEE International Conference on Internet of People and IEEE Smart World Congress and Workshops, UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld 2016, IEEE conference proceedings, 2016, s. 680-689Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Increasingly sophisticated, complex, and energy-efficient cyber-physical systems and wireless sensor networks are emerging, facilitated by recent advances in computing and sensor technologies. Integration of cyber-physical systems and wireless sensor networks with other contemporary technologies, such as unmanned aerial vehicles and fog or edge computing, enable creation of completely new smart solutions. We present the concept of a Smart Mobile Access Point (SMAP), which is a key building block for a smart network, and propose an efficient placement approach for such SMAPs. SMAPs predict the behavior of the network, based on information collected from the network, and select the best approach to support the network at any given time. When needed, they autonomously change their positions to obtain a better configuration from the network performance perspective. Therefore, placement of SMAPs is an important issue in such a system. Initial placement of SMAPs is an NP problem, and evolutionary algorithms provide an efficient means to solve it. Specifically, we present a parallel implementation of the imperialistic competitive algorithm and an efficient evaluation or fitness function to solve the initial placement of SMAPs in the fog computing context.

  • 286.
    Meincke, Thomas
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    Ellervee, Peeter
    Öberg, Johnny
    Kumar, Shashi
    Lindqvist, Dan
    Ericsson AB.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Postula, Adam
    Univ. of Queensland.
    Evaluating benefits of Globally Asynchronous Locally Synchronous VLSI Architecture1998Konferansepaper (Fagfellevurdert)
  • 287.
    Meincke, Thomas
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Kumar, Shashi
    KTH, Skolan för informations- och kommunikationsteknik (ICT).
    Ellervee, Peeter
    KTH, Skolan för informations- och kommunikationsteknik (ICT).
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Olsson, Thomas
    Dept. of Applied Electronics, Univ. of Lund.
    Nilsson, Peter
    Dept. of Applied Electronics, Univ. of Lund.
    Lindqvist, Dan
    Dept. of Computer Science, IIT New Delhi.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Globally asynchronous locally synchronous architecture for large high-performance ASICs1999Inngår i:  , 1999, Vol. 2, s. 512-515Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%

  • 288. Meincke, Thomas
    et al.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Ellervee, Peeter
    Hemani, Ahmed
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    A Generic Scheme for Communication Representation and Mapping1999Inngår i:  , 1999Konferansepaper (Fagfellevurdert)
  • 289.
    Michielsen, Wim
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Shen, Meigen
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Performance and cost estimations of packaged single band Voltage Controlled Oscillators2004Inngår i: PROCEEDINGS OF THE IEEE 6TH CIRCUITS AND SYSTEMS SYMPOSIUM ON EMERGING TECHNOLOGIES: FRONTIERS OF MOBILE AND WIRELESS COMMUNICATION, VOLS 1 AND 2, NEW YORK: IEEE , 2004, s. 53-56Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper reports the performance and cost estimations in the early stage of a LC tank based Voltage Controlled Oscillator (VCO) design. System-on-Chip (SoC) versus System-on-package (SoP) configurations is compared for electrical performance and cost of a 1.25 GHz voltage controlled oscillator. It is found that a single chip design is not always the best solution. We obtained the best figure of merit for a SoP implementation where only the inductors were put off-chip.

  • 290. Mohamed, S. A. S.
    et al.
    Haghbayan, M. -H
    Westerlund, T.
    Heikkonen, J.
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar. Department of Future Technologies, University of Turku (UTU), Turku, 20500, Finland.
    Plosila, J.
    A Survey on Odometry for Autonomous Navigation Systems2019Inngår i: IEEE Access, E-ISSN 2169-3536, Vol. 7, s. 97466-97486, artikkel-id 8764393Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The development of a navigation system is one of the major challenges in building a fully autonomous platform. Full autonomy requires a dependable navigation capability not only in a perfect situation with clear GPS signals but also in situations, where the GPS is unreliable. Therefore, self-contained odometry systems have attracted much attention recently. This paper provides a general and comprehensive overview of the state of the art in the field of self-contained, i.e., GPS denied odometry systems, and identifies the out-coming challenges that demand further research in future. Self-contained odometry methods are categorized into five main types, i.e., wheel, inertial, laser, radar, and visual, where such categorization is based on the type of the sensor data being used for the odometry. Most of the research in the field is focused on analyzing the sensor data exhaustively or partially to extract the vehicle pose. Different combinations and fusions of sensor data in a tightly/loosely coupled manner and with filtering or optimizing fusion method have been investigated. We analyze the advantages and weaknesses of each approach in terms of different evaluation metrics, such as performance, response time, energy efficiency, and accuracy, which can be a useful guideline for researchers and engineers in the field. In the end, some future research challenges in the field are discussed.

  • 291. Moosavi, S. R.
    et al.
    Gia, T. N.
    Nigussie, E.
    Rahmani, A. M.
    Virtanen, S.
    Tenhunen, Tenhunen
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Isoaho, J.
    End-to-end security scheme for mobility enabled healthcare Internet of Things2016Inngår i: Future generations computer systems, ISSN 0167-739X, E-ISSN 1872-7115Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    We propose an end-to-end security scheme for mobility enabled healthcare Internet of Things (IoT). The proposed scheme consists of (i) a secure and efficient end-user authentication and authorization architecture based on the certificate based DTLS handshake, (ii) secure end-to-end communication based on session resumption, and (iii) robust mobility based on interconnected smart gateways. The smart gateways act as an intermediate processing layer (called fog layer) between IoT devices and sensors (device layer) and cloud services (cloud layer). In our scheme, the fog layer facilitates ubiquitous mobility without requiring any reconfiguration at the device layer. The scheme is demonstrated by simulation and a full hardware/software prototype. Based on our analysis, our scheme has the most extensive set of security features in comparison to related approaches found in literature. Energy-performance evaluation results show that compared to existing approaches, our scheme reduces the communication overhead by 26% and the communication latency between smart gateways and end users by 16%. In addition, our scheme is approximately 97% faster than certificate based and 10% faster than symmetric key based DTLS. Compared to our scheme, certificate based DTLS consumes about 2.2 times more RAM and 2.9 times more ROM resources. On the other hand, the RAM and ROM requirements of our scheme are almost as low as in symmetric key-based DTLS. Analysis of our implementation revealed that the handover latency caused by mobility is low and the handover process does not incur any processing or communication overhead on the sensors.

  • 292. Moosavi, S. R.
    et al.
    Gia, T. N.
    Nigussie, E.
    Rahmani, Amir
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Virtanen, S.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Isoaho, J.
    Session resumption-based end-to-end security for healthcare internet-of-things2015Inngår i: Proceedings - 15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, s. 581-588Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, a session resumption-based end-toend security scheme for healthcare Internet of things (IoT) is proposed. The proposed scheme is realized by employing certificatebased DTLS handshake between end-users and smart gateways as well as utilizing DTLS session resumption technique. Smart gateways enable the sensors to no longer need to authenticate and authorize remote end-users by handing over the necessary security context Session resumption technique enables end-users and medical sensors to directly communicate without the need for establishing the communication from the initial handshake. Session resumption technique has an abbreviated form of DTLS handshake and neither requires certificate-related nor public-key funtionalities. This alleviates some burden of medical sensors to no longer need to perform expensive operations. The energyperformance evaluations of the proposed scheme are evaluated by developing a remote patient monitoring prototype based on healthcare IoT. The energy-performance evaluation results show that our scheme is about 97% and 10% faster than certificatebased and symmetric key-based DTLS, respectively. Also, the certificate-based DTLS consumes about 2.2X more RAM and 2.9X more ROM resources required by our scheme. While, our scheme and symmetric key-based DTLS have almost similar RAM and ROM requirements. The security analysis reveals that the proposed scheme fulfills the requirements of end-to-end security and provides higher security level than related approaches found in the literature. Thus, the presented scheme is a wellsuited solution to provide end-to-end security for healthcare IoT.

  • 293. Naqvi, S. I.
    et al.
    Khan, A.
    Azam, M. A.
    Amin, Y.
    Loo, J.
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    A planar flexible quad-band antenna for WLAN/WiMAX/LTE applications2019Inngår i: 2019 2nd International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2019, Institute of Electrical and Electronics Engineers Inc. , 2019Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this work a quad-band, planar, low-profile and compact antenna envisioned for incorporation into portable wireless devices is presented. The antenna is modeled on flexible Rogers RT/Duroid 5880 substrate of 0.127mm thickness. The proposed antenna structure consists of symmetrically placed F-shaped slits and a curved rectangular shaped ground plane with a CPW feed line. The four bands obtained for the radiator operates at the resonant frequencies 2.8, 3.9, 5.45 and 6.2 GHz with impedance bandwidths of 14%, 14.5%, 5.7%, and 5% respectively. Thus the proposed antenna supports WLAN, LTE, WiMAX, and C-band applications. The peak gain achieved for the antenna is 3.4 dB.

  • 294.
    Naqvi, Syeda, I
    et al.
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Naqvi, Aqeel H.
    Chung Ang Univ, Sch Elect & Elect Engn, Seoul 06974, South Korea..
    Arshad, Farzana
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Riaz, Muhammad A.
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Azam, Muhammad A.
    Univ Engn & Technol, Dept Comp Engn, Taxila 47050, Pakistan..
    Khan, Mansoor S.
    COMSATS Univ Islamabad, Math Dept, Islamabad 45550, Pakistan..
    Amin, Yasar
    Univ Engn & Technol, Telecommun Engn Dept, ACTSENA Res Grp, Taxila 47050, Pakistan..
    Loo, Jonathan
    Univ West London, Sch Comp & Engn, London W5 5RF, England..
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik. Univ Turku, TUCS, Dept Informat Technol, FIN-20520 Turku, Finland..
    An Integrated Antenna System for 4G and Millimeter-Wave 5G Future Handheld Devices2019Inngår i: IEEE Access, E-ISSN 2169-3536, Vol. 7, s. 116555-116566Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this work, an integrated antenna system with Defected Ground Structure (DGS) is presented for Fourth Generation (4G) and millimeter (mm)-wave Fifth Generation (5G) wireless applications and handheld devices. The proposed design with overall dimensions of 110 mm x 75 mm is modeled on 0.508 mm thick Rogers RT/Duroid 5880 substrate. Radiating structure consists of antenna arrays excited by the T-shape 1 x 2 power divider/combiner. Dual bands for 4G centered at 3.8 GHz and 5.5 GHz are attained, whereas the 10-dB impedance bandwidth of 24.4 - 29.3 GHz is achieved for the 5G antenna array. In addition, a peak gain of 5.41 dBi is demonstrated across the operating bandwidth of the 4G antenna array. Similarly, for the 5G mm-wave configuration the attained peak gain is 10.29 dBi. Moreover, significant isolation is obtained between the two antenna modules ensuring efficient dual-frequency band operation using a single integrated solution. To endorse the concept, antenna prototype is fabricated and far-field measurements are procured. Simulated and measured results exhibit coherence. Also the proposed design is investigated for the beam steering capability of the mm-wave 5G antenna array using CST(R)MWS(R). The demonstrated structure offers various advantages including compactness, wide bandwidth, high gain, and planar configuration. Hence, the attained radiation characteristics prove the suitability of the proposed design for the current and future wireless handheld devices.

  • 295. Negash, B.
    et al.
    Westerlund, T.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH. Department of Information Technology, University of Turku, Turku, Finland.
    Rethinking ‘Things’ - Fog layer interplay in IoT: A mobile code approach2018Inngår i: 11th IFIP WG 8.9 Working Conference on Research and Practical Issues of Enterprise Information Systems, CONFENIS 2017, Springer, 2018, Vol. 310, s. 159-167Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A client-server architecture style is one of the common approaches enabling separation of concerns in distributed systems. In the Internet of Things architecture, this approach exists in different configuration of sensors, actuators, gateways in the Fog layer and servers in the Cloud. This configuration affects the degree of interoperability, scalability and other functional and non-functional system requirements. In this paper, we reflect on best practices in the web and REST style to address IoT challenges; one of the constraints in REST, Code on Demand, is used for IoT to enhance the flexibility and interoperability of resource constrained clients at the perception layer. Scripts written in a domain specific language, DoS-IL, are organized and stored at the Fog layer for sensor and actuators nodes to request and execute the incoming script. A generic application layer protocol and RESTful server are presented along with experimental results.

  • 296. Negash, B.
    et al.
    Westerlund, T.
    Rahmani, A. M.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar. University of Turku, Finland.
    DoS-IL: A Domain Specific Internet of Things Language for Resource Constrained Devices2017Inngår i: 8th International Conference on Ambient Systems, Networks and Technologies, ANT-2017 and the 7th International Conference on Sustainable Energy Information Technology, SEIT 2017, 16-19 May 2017, Madeira, Portugal, Elsevier, 2017, Vol. 109, s. 416-423Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The common approach enabling a resource constrained device to get connected to the Internet is through programming instructions and transferring it to an embedded device. This procedure involves various tools and cross-compiling of the code depending on the platform architecture. In practical IoT applications, where a huge number of nodes exist, this process becomes almost impossible due to the heterogeneous platforms and protocols involved and the deployment conditions. This paper introduces a flexible and scalable approach that enhances modifiability and programmability through client-server-server-client architecture. It allows changing the behavior of the system after deployment through a lightweight script written with a domain specific language, DoS-IL, and stored in a gateway at the fog layer. An embedded resource browser is used to request and execute the script. The results of analysis for this model and the tools developed along the way are discussed.

  • 297. Negash, B.
    et al.
    Westerlund, T.
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    Towards an interoperable Internet of Things through a web of virtual things at the Fog layer2019Inngår i: Future generations computer systems, ISSN 0167-739X, E-ISSN 1872-7115, Vol. 91, s. 96-107Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A wide range of Internet of Things devices, platforms and applications have been implemented in the past decade. The variation in platforms, communication protocols and data formats of these systems creates islands of applications. Many organizations are working towards standardizing the technologies used at different layers of communication in these systems. However, interoperability still remains one of the main challenges towards realizing the grand vision of IoT. Intergration approaches proven in the existing Internet or enterprise applications are not suitable for the IoT, mainly due to the nature of the devices involved; the majority of the devices are resource constrained. To address this problem of interoperability, our work considers various types of IoT application domains, architecture of the IoT and the works of standards organizations to give a holistic abstract model of IoT. According to this model, there are three computing layers, each with a different level of interoperability needs — technical, syntactic or semantic. This work presents a Web of Virtual Things (WoVT) server that can be deployed at the middle layer of IoT (Fog layer) and Cloud to address the problem of interoperability. It exposes a REST like uniform interface for syntactic integration of devices at the bottom layer of IoT (perception layer). An additional RESTful api is used for integration with other similar WoVT servers at the Fog or the Cloud layer. The server uses a state of the art architecture to enable this integration pattern and provides means towards semantic interoperability. The analysis and evaluation of the implementation, such as performance, resource utilization and security perspectives, are presented. The simulation results demonstrate that an integrated and scalable IoT through the web of virtual things can be realized.

  • 298. Negash, Behailu
    et al.
    Rahmani, Amir M.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Westerlund, Tomi
    Liljeberg, Pasi
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    LISA 2.0: lightweight internet of things service bus architecture using node centric networking2016Inngår i: Journal of Ambient Intelligence and Humanized Computing, ISSN 1868-5137, E-ISSN 1868-5145, Vol. 7, nr 3, s. 305-319Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Internet of things (IoT) technologies are advancing rapidly and a wide range of physical networking alternatives, communication standards and platforms are introduced. However, due to differences in system requirements and resource constraints in devices, there exist variations in these technologies, standards, and platforms. Consequently, application silos are formed. In contrast to the freedom of choice attained by a range of options, the heterogeneity of the technologies is a critical interoperability challenge faced by IoT systems. Moreover, IoT is also limited to address new requirements that arise due to the nature of the majority of smart devices. These requirements, such as mobility and intermittent availability, are hardly satisfied by the current IoT technologies following the end-to-end model inherited from the Internet. This paper introduces a lightweight, distributed, and embedded service bus called LISA which follows a Node Centric Networking architecture. LISA is designed to provide interoperability for resource-constrained devices in IoT. It also enables a natural way of embracing the new IoT requirements, such as mobility and intermittent availability, through node centric networking. LISA provides a simple application programming interface for developers, hiding the variations in platform, protocol or physical network, thus facilitating interoperability in IoT systems. LISA is inspired by network on terminal architecture (NoTA), a service centric open architecture originated by Nokia Research Center. Our extensive experimental results show the efficiency and scalability of LISA in providing a lightweight interoperability for IoT systems.

  • 299.
    Negash, Behailu
    et al.
    University of Turku, Finland.
    Rahmani, Amir-Mohammad
    University of Turku.
    Westerlund, Tomi
    University of Turku, Finland.
    Liljeberg, Pasi
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    LISA: Lightweight Internet of Things Service Bus Architecture2015Inngår i: Procedia Computer Science, ISSN 1877-0509, E-ISSN 1877-0509, Vol. 52, s. 436-443Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A critical challenge faced in Internet of Things (IoT) is the heterogeneous nature of its nodes from the network protocol and platform point of view. To tackle the heterogeneous nature, we introduce a distributed and lightweight service bus, LISA, which fits into network stack of a real-time operating system for constrained nodes in IoT. LISA provides an application programming interface for developers of IoT on tiny devices. It hides platform and protocol variations underneath it, thus facilitating interoperability challenges in IoT implementations. LISA is inspired by the Network on Terminal Architecture (NoTA), a service centric open architecture by Nokia Research Center. Unlike many other interoperability frameworks, LISA is designed specifically for resource constrained nodes and it provides essential features of a service bus for easy service oriented architecture implementation.

  • 300.
    Nejad, Majid Baghaei
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Chen, Cairong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hanuu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    An innovative semi-UWB passive transponder for wireless sensor and RFID applications2006Inngår i: 2006 International Conference on Industrial and Information Systems, Vols 1 and 2, NEW YORK: IEEE , 2006, s. 310-315Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we present a self-powered CMOS impulse-based ultra wideband radio system for RFIDs and Wireless sensor networks (WSN) applications. It is integrated in a Liquid-Crystal Polymer (LCP) based System on Package (SoP) module with an embedded small antenna. Our contribution includes using two different standards in up and downstream link. In downstream link, due to demand of low complex, low cost and low power circuit, a very simple and extremely low power pulse width demodulator is used to extract the data from received RF signal. An IR-UWB transmitter is used to transmit the data in upstream link. Power supply is taken from the received RF electromagnetic wave with help of a Schottky diode voltage multiplier. Unlike traditional wireless systems, due to great advantages of UWB communication this Transponder does not suffer from multipath fading, collision problem and multi-user interference. The front-end circuit consists of the power converter; PWM receiver, IR-UWB transmitter, and embedded UWB antenna are designed for integration on Liquid-Crystal Polymer (LCP) substrate.

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