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• 301. Koo, S.-M.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Characteristics of PZT/Al2O3 stack on SiC demonstrated in a NVFET2003In: 34th IEEE Semicondctor Interface Specialists Conference, 2003, 2003Conference paper (Refereed)
• 302. Koo, S.-M.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Metal-oxide-semiconductor structures in inductively coupled plasma etch damaged 6H- and 4H-SiC2001In: 32nd IEEE Semiconductor Interface Specialists Conference, 2001, 2001Conference paper (Refereed)
• 303. Koo, S.-M.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Multifunction Integration of Junction-MOSFETs and Nonvolatile FETs on a Single 4H-SiC Substrate for 300°C Operation2003In: Proc. IEEE International Electron Devices Meeting (IEDM) 2003, IEEE conference proceedings, 2003, p. 575-578Conference paper (Refereed)
• 304. Kundozerova, T. V.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Binary anodic oxides for memristor-type nonvolatile memory2012In: Physica Status Solidi. C, Current topics in solid state physics, ISSN 1610-1634, E-ISSN 1610-1642, Vol. 9, no 7, p. 1699-1701Article in journal (Refereed)

The temperature dependence of the optical properties of InGaAs/GaAs double quantum wells (QWs) grown by molecular beam epitaxy (MBE) on (100) and (311)A GaAs substrates has been studied by photoluminescence (PL). It is found that for an excitation of 50 mW, the PL quenching for (100) and (311)A QWs occurs at 220 K and 300 K, respectively. This suggests that the high index plane (311)A has superior structural properties and less non-radiative defect centers than the conventional (100) plane. The better optical quality of the QWs grown on (311)A is also confirmed by the narrowing of the full width at half-maximum (FWHM) of the PL emission: 10 nm for (311)A and 20 nm for (100). From these findings it is expected that optical devices grown on (311)A GaAs planes should have better performances than those grown on conventional (100) orientation. We have also carried out a systematic study to investigate the effect of post-growth thermal annealing on the optical quality of the QWs. We observed a substantial improvement of the PL efficiency with annealing temperatures in the range 500-700 Â°C for all samples. However, this PL enhancement is accompanied by a blueshift. These energy shifts can be explained by interdiffusion or intermixing of In and Ga atoms at the interfaces between the QWs and the barriers. A noticeable narrowing of the PL linewidth with higher annealing temperatures could be explained by a homogenisation of the quantum well interfaces.

• 305. Kuroki, S. I.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Characterization of 4H-SiC nMOSFETs in harsh environments, high-temperature and high gamma-ray radiation2016In: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015, Trans Tech Publications Ltd , 2016, p. 864-867Conference paper (Refereed)

Characteristics of 4H-SiC nMOSFETs with arsenic-doped S/D and NbNi silicide contacts in harsh environments of high-temperature up to 450°C, and high gamma-ray radiation up to over 100 Mrad, were investigated. At high temperature, field effect mobility increased as proportional to T3/2, and threshold voltage was shifted with temperature coefficients of -4.3 mV/K and -2.6 mV/K for oxide thicknesses of 10 nm and 20 nm, respectively. After Co60 gamma-ray exposure of 113 Mrad, the field effect mobility was varied within 8% for oxide thickness of 10 nm, however for 20 nm oxide thickness, this variation was 26%. The threshold voltage shifts were within 6%.

• 306. Lanner, Johanna T.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Knockdown of TRPC3 with siRNA coupled to carbon nanotubes results in decreased insulin-mediated glucose uptake in adult skeletal muscle cells2009In: The FASEB Journal, ISSN 0892-6638, E-ISSN 1530-6860, Vol. 23, no 6, p. 1728-1738Article in journal (Refereed)

The involvement of Ca2+ in the insulin-mediated signaling cascade, resulting in glucose uptake in skeletal muscle, is uncertain. Here, we test the hypothesis that Ca2+ influx through canonical transient receptor potential 3 (TRPC3) channels modulates insulin-mediated glucose uptake in adult skeletal muscle. Experiments were performed on adult skeletal muscle cells of wild-type (WT) and obese, insulin-resistant ob/ob mice. Application of the diacylglycerol analog 1-oleyl-2-acetyl-sn-glycerol (OAG) induced a nonselective cation current, which was inhibited by the addition of anti-TRPC3 antibody in the patch pipette and smaller in ob/ob than in WT cells. Knockdown of TRPC3, using a novel technique based on small interfering RNA (siRNA) coupled to functionalized carbon nanotubes, resulted in pronounced (similar to 70%) decreases in OAG-induced Ca2+ influx and insulin-mediated glucose uptake. TRPC3 and the insulin-sensitive glucose transporter 4 (GLUT4) coimmunoprecipitated, and immunofluorescence staining showed that they were colocalized in the proximity of the transverse tubular system, which is the predominant site of insulin-mediated glucose transport in skeletal muscle. In conclusion, our results indicate that TRPC3 interacts functionally and physically with GLUT4, and Ca2+ influx through TRPC3 modulates insulin-mediated glucose uptake. Thus, TRPC3 is a potential target for treatment of insulin-resistant conditions.-Lanner, J. T., Bruton, J. D., Assefaw-Redda, Y., Andronache, Z., Zhang, S.- J., Severa, D., Zhang, Z.- B., Melzer, W., Zhang, S.-L., Katz, A., Westerblad, H. Knockdown of TRPC3 with siRNA coupled to carbon nanotubes results in decreased insulin-mediated glucose uptake in adult skeletal muscle cells. FASEB J. 23, 1728-1738 (2009)

• 307.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Silicon Carbide Bipolar Integrated Circuits for High Temperature Applications2012Licentiate thesis, comprehensive summary (Other academic)

Silicon carbide (SiC) is a semiconductor that provides significant advantages for high-power and high-temperature applications thanks to its wide bandgap, which is several times larger than silicon. The resulting high breakdown field, high thermal conductivity and high intrinsic temperature (well above 600 °C) allow high temperature operation of SiC devices and relaxed cooling requirements. In particular, SiC bipolar junction transistors (BJTs) are suitable for high temperature integrated circuits (ICs), due to the absence of a gate oxide.

This work focuses on design, fabrication and characterization of the first 4H-SiC integrated circuits realized at KTH. It deals with basic bipolar ICs suitable for high temperature and low voltage applications. Operation up to 300 °C of low-voltage 4H-SiC NPN bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) has been demonstrated. In the temperature range 27 - 300 °C stable noise margins of about 1 V have been achieved for a 2-input OR-NOR gate operated on -15 V supply voltage, and an oscillation frequency of about 2 MHz has been observed for a 3-stage ring oscillator.

The possibility of realizing PNP transistors and passive devices in the same process technology has also been investigated.

• 308.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Silicon Carbide BipolarTechnology for High Temperature Integrated Circuits2014Doctoral thesis, comprehensive summary (Other academic)

The availability of integrated circuits (ICs) capable of 500 or 600° C operation can be extremely beneficial for many important applications, such as transportation and energy sector industry. It can in fact enable the realization of improved sensing and control of turbine engine combustion leading to better fuel efficiency and reduced pollution. In addition, the possibility of placing integrated circuits in engine hot-sections can significantly reduce the weight and improve the reliability of automobiles and aircrafts, eliminating extra wires and cooling systems.

In order to develop such electronics semiconductors with superior high temperature characteristics compared to Si are required. Thanks to its wide bandgap,  almost three times that of Si, Silicon carbide (SiC) has been suggested for this purpose. Its low intrinsic carrier concentration, orders of magnitude lower than that of Si, makes SiC devices capable of operating at much higher temperatures than Si devices.

In this thesis solutions for 600° C SiC bipolar ICs have been investigated in depth at device physics, circuit and process integration level. Successful operation of devices and circuits  has been proven from -40 up to 600° C.

The developed technology features NPN and lateral PNP transistors, two levels of interconnects and one extra metal level acting as over-layer metallization for device contacts. The improved SiC etching and passivation procedures have provided NPN transistors with high current gain of approximately 200. Furthermore, non-monotonous current gain temperature dependences have been observed for NPN and PNP transistors. The current gain of NPN transistors increases with temperature at high enough temperatures above 300° C  depending on the base doping concentration. The current gain of lateral PNP transistors has, instead, shown a maximum of approximately 37 around 0° C.

Finally, high-temperature operation of 2-input ECL-based OR-NOR gates and  3- and 11-stage ring oscillators has been demonstrated. For the OR-NOR gates stable noise margins of approximately 1 or 1.5 V, depending on the gate design, have been observed up to 600° C with a delay-power consumption product of approximately 100 nJ in the range -40 to 500° C.  Ring oscillators with different designs, including more than 100 devices, have been  successfully tested in the range 27 to 300° C. Non-monotonous and almost constant temperature dependences have been observed for the oscillation frequency of 3- and 11-stage ring oscillator, respectively. In addition, room temperature propagation delays of a single inverter stage have been estimated to be approximately 100 and 40 ns for 3- and 11-stage ring oscillators, respectively.

• 309.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Bipolar Integrated OR-NOR Gate in 4H-SiC2011In: Proceedings of International Conference on Silicon Carbibe and Related Materials 2011, 2011Conference paper (Refereed)
• 310.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Measurements and simulations of lateral PNP transistors in a SiC NPN BJT technology for high temperature integrated circuits2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 758-761Article in journal (Refereed)

In this work, a 4H-SiC lateral PNP transistor fabricated in a high voltage NPN technology has been simulated and characterized. The possibility of fabricating a lateral PNP with a current gain larger than 1 has been investigated. Device and circuit level solutions have been performed.

• 311.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 4, p. 1076-1083Article in journal (Refereed)

Operation up to 300 degrees C of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter-coupled logic is demonstrated. Stable noise margins of about 1 V are reported for a two-input OR-NOR gate operated on - 15 V supply voltage from 27 degrees C up to 300 degrees C. In the same temperature range, an oscillation frequency of about 2 MHz is also reported for a three-stage ring oscillator.

• 312.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Bipolar integrated OR-NOR gate in 4H-SiC2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1257-1260Article in journal (Refereed)

An integrated bipolar OR-NOR gate based on emitter coupled logic (ECL) is demonstrated in 4H-SiC. Operated from 27 up to 300 Â°C on -15 V supply voltage the logic gate exhibits stable noise margins (NMs) of about 1 V in the entire temperature range, and high and low output voltage levels that move towards positive voltages when the temperature increases: from -3 up to -2.7 V and from -5.4 up to -5.1 V respectively. In the same temperature range transistor current gain (Î²) goes from 46 down to 21.

• 313.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits2013In: Journal of Microelectronics and Electronic Packaging, ISSN 1551-4897, E-ISSN 1555-8037, Vol. 10, no 4, p. 155-162Article in journal (Refereed)

A 4H-SiC bipolar technology suitable for hightemperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27Â°C up to 500Â°C for both the metallization systems. When operated on -15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300Â°C with current density of about 1 MA/cmÂ² on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

• 314.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Improved surface passivation by enhanced N2O annealing for high gain 4H-SiC BJTsManuscript (preprint) (Other academic)
• 315.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
SiC Etching and Sacrificial Oxidation Effects on the Performance of 4H-SiC BJTs2014In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 778-780, p. 1005-1008Article in journal (Refereed)

Performance of 4H-SiC BJTs fabricated on a single 100mm wafer with different SiC etching and sacrificial oxidation procedures is compared in terms of peak current gain in relation to base intrinsic sheet resistance. The best performance was achieved when device mesas were defined by inductively coupled plasma etching and a dry sacrificial oxide was grown at 1100 °C.

• 316.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
High-temperature characterization of 4H-SiC darlington transistors for low voltage applications2013In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 740-742, p. 966-969Article in journal (Refereed)

4H-SiC bipolar Darlington transistors (D-BJTs) for low voltage applications have been fabricated, simulated and characterized up to 300 °C, where they exhibit a current gain of 460. The influence on D-BJT current gain of relative current capability of driver and output BJTs has been investigated, and the collector resistance has been identified as the main limitation for the D-BJTs.

• 317.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
500 degrees C Bipolar Integrated OR/NOR Gate in 4H-SiC2013In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 34, no 9, p. 1091-1093Article in journal (Refereed)

Successful operation of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter coupled logic is reported from -40 degrees C to 500 degrees C. Nonmonotonous temperature dependence (previously predicted by simulations but now measured) was observed for the transistor current gain; in the range -40 degrees C - 300 degrees C it decreased when the temperature increased, while it increased in the range 300 degrees C-500 degrees C. Stable noise margins of similar to 1 V were measured for a 2-input OR/NOR gate operated on -15 V supply voltage from 0 degrees C to 500 degrees C for both OR and NOR output.

• 318.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
ECL-based SiC logic circuits for extreme temperatures2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821-823, p. 910-913Article in journal (Refereed)
• 319.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 1, p. 11-13Article in journal (Refereed)

The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50-150 nm were deposited prior to the same annealing process in N2O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, similar to 60% higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of similar to 200 at room temperature and >100 at 300 degrees C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains.

• 320.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Lateral p-n-p Transistors and Complementary SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 4, p. 428-430Article in journal (Refereed)

Lateral p-n-p transistors and a complementary bipolar technology have been demonstrated for analog integrated circuits. Besides vertical n-p-n's, this technology provides lateral p-n-p's at the cost of one additional lithographic and dry etching step. Both devices share the same epitaxial layers and feature topside contacts to all terminals. The influence on p-n-p current gain of contact topology (circular versus rectangular), effective base width, base/emitter doping ratio, and temperature was studied in detail. In the range -40 degrees C to 300 degrees C, the current gain of the p-n-p transistor shows a maximum of similar to 37 around 0 degrees C and decreases to similar to 8 at 300 degrees C, whereas in the same range, the gain of n-p-n transistors exhibits a negative temperature coefficient.

• 321. Lansåker, Pia C.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Characterization of gold nanoparticle films: Rutherford backscattering spectroscopy, scanning electron microscopy with image analysis, and atomic force microscopy2014In: AIP Advances, ISSN 2158-3226, E-ISSN 2158-3226, Vol. 4, no 10, p. 107101-Article in journal (Refereed)

Gold nanoparticle films are of interest in several branches of science and technology, and accurate sample characterization is needed but technically demanding. We prepared such films by DC magnetron sputtering and recorded their mass thickness by Rutherford backscattering spectroscopy. The geometric thickness d(g)-from the substrate to the tops of the nanoparticles-was obtained by scanning electron microscopy (SEM) combined with image analysis as well as by atomic force microscopy (AFM). The various techniques yielded an internally consistent characterization of the films. In particular, very similar results for d(g) were obtained by SEM with image analysis and by AFM.

• 322.
KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. Univ Gothenburg, Sweden. Faculty of Physics, Amirkabir University of Technology. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University. Center for Spintronics Integrated Systems, Tohoku University. Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University. Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. Univ Gothenburg, Sweden; NanOsc AB, Sweden.
Ultra-high frequency tunability in low-current and low-field spin-torque oscillators based on perpendicular magnetic tunnel junctionsManuscript (preprint) (Other (popular science, discussion, etc.))

We demonstrate ultra-high frequency tunability of up to 4.4 GHz/mA, and low threshold currents of about -21 $\mu$A, in spin-torque oscillators based on CoFeB/MgO/CoFeB magnetic tunnel junctions, in which both free and fixed layers have perpendicular magnetic anisotropy (PMA). By using different thicknesses of the two CoFeB layers, their individual PMA strengths can be tailored to achieve significant relative misalignment of their respective magnetizations in moderate in-plane fields. We observe a broad maximum in both the device resistance and the generated microwave power around maximum misalignment. Maximum frequency tunability is observed at low-to-moderate fields and decrease rapidly after maximum misalignment.

• 323.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 8, p. 1894-1898Article in journal (Refereed)

This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 x 1.8 nun (with an active area of 3.24 mm') showed a common emitter current gain 0 of 42, specific on-resistance Rsp ON of 9 mQ - em', and open-base breakdown voltage BVcEO of-1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the p+ regrown layer from the surface of the emitter-base junction. The BJT with p+ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs; with only etched flat-surface JTE.

• 324.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Low-forward-voltage-drop 4H-SiC BJTs without base contact implantation2008In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, no 8, p. 1907-1911Article in journal (Refereed)

Bipolar junction transistors (BJTs) of 4H-SiC, with a low collector--emitter forward voltage drop YCE, have been fabricated without base contact implantation. A comparison of BJTs on the same wafer with and without base contact implantation shows less than 10% higher VcE for the BJTs without base contact implantation. Omitting the base contact implantation eliminates high concentrations of implantation-induced defects that act as recombination centers. This is advantageous because it allows a shorter distance Wp+ between the emitter edge and the base contact, without affecting the current gain when no base contact implantation is used. The BJTs without contact implantation show a constant current gain as Wp+ was reduced from 3 to I pm, whereas the gain decreased by 45% for the BJTs with base contact implantation for the same reduction of Wp+. A key to the successful fabrication of low-forward-voltage-drop SiC BJTs without base contact implantation is the formation of low-resistivity Ni/Ti/Al ohmic contacts to the base. The contact resistivity on the base region (N-A approximate to 4 x 10(17) cm(-3)) was measured with linear transmission line method structures to PC = 1.9 X 10(-3) Omega cm(2), whereas the contact resistivity with the base contact implantation was PC = 1.3 x 10-4 Omega cm(2), both after rapid thermal processing annealing at 800 degrees C.

• 325.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Material Physics, Semiconductor Materials, HMA. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Department of Microtechnology and Nanoscience, Chalmers University of Technology. Department of Microtechnology and Nanoscience, Chalmers University of TechnologyDepartment of Microtechnology and Nanoscience, Chalmers University of Technology.
1200-V 5.2-m Omega center dot cm(2) 4H-SiC BJTs with a high common-emitter current gain2007In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 11, p. 1007-1009Article in journal (Refereed)

This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BVCEO approximate to 1200 V, a low specific ON-resistance R-SP_ON approximate to 5.2 m Omega . cm(2), and a high common-emitter current. gain beta approximate to 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N2O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.

• 326. Lee, J. -H
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Local anodic oxidation of phosphorus-implanted 4H-SiC by atomic force microscopy2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 905-908Article in journal (Refereed)

In this work, local oxidation behavior in phosphorus ion-implanted 4H-SiC has been investigated by using atomic force microscopy (AFM). The AFM-local oxidation (LO) has been performed on the implanted samples, with and without activation anneal, using varying applied bias (15/20/25 V). It has been clearly shown that the post-implantation annealing process at 1650 Â°C has a great impact on the local oxidation rate by electrically activating the dopants and by modulating the surface roughness. In addition, the composition of resulting oxides changes depending on the doping level of SiC surfaces.

• 327. Lee, K. P.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Comparison of F2 plasma chemistries for deep etching of SiC2001In: Materials Research Society Symposium - Proceedings, Boston, MA, 2001, Vol. 640, p. H7.7.1-H7.7.6Conference paper (Refereed)

A number of F2-based plasma chemistries (NF3, SF6, PF5 and BF3) were investigated for high rate etching of SiC. The most advantageous of these is SF6, based on the high rate (0.6 ÎŒmÂ·min-) it achieves and its relatively low cost compared to NF3. The changes in electrical properties of the near-surface region are relatively minor when the incident ion energy is kept below approximately 75 eV. At a process pressure of 5 m Torr, the SiC etch rate falls-off by âˆŒ15% in 30 ÎŒm diameter via holes compared to larger diameter holes (&gt; 60 ÎŒm diameter) or open areas on the mask.

• 328. Lee, S. -K
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
The formation and characterization of epitaxial titanium carbide contacts to 4H-SiC2000In: Materials Research Society Symposium - Proceedings, San Francisco, CA, 2000, Vol. 622, p. T691-T696Conference paper (Refereed)

Epitaxial TiC Ohmic and Schottky contacts to 4H-SiC were formed by a new deposition method, UHV co-evaporation with Ti and C60, at low temperature (&lt; 500Â°C). We achieved a contact resistivity of 2 Ã— 10-5 Î©cm2 at 25Â°C for as deposited Ohmic contacts on Al ion implanted 4H-Silicon carbide. The rectifying behavior of TiC Schottky contacts was also investigated using I-V and C-V. The measured Schottky barrier height (SBH) was 1.26 eV for n-type and 1.65 eV for p-type 4H-SiC using C-V measurements for frequencies ranging from 1kHz to 1MHz. LEED, RBS, XPS, and XRD measurements were performed to analyze composition ratio, interface reaction, and structural properties of the TiC epitaxial layer.

• 329. Lee, S. -K
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Titanium tungsten (TiW) for Ohmic contacts to n-and p-type 4H-SiC2001In: Materials Research Society Symposium - Proceedings, Boston, MA, 2001, Vol. 640, p. H7.2.1-H7.2.6Conference paper (Refereed)

In the present work, we investigated sputtered titanium tungsten (TiW) contacts for Ohmic contacts to both n- and p-type 4H-SiC with long-term stability under high temperature (500Â°C). Epitaxial layers with a doping concentration of 1.3Ã—1019 and 6Ã—1018 cm-3 were used. After high temperature annealing (&gt;950Â°C) sputtered TiW contacts showed Ohmic behavior with good uniform distribution of the specific contact resistance. We obtained an average specific contact resistance (Ïc) of 4Ã—10-5 Î©cm2 and 1.2-1.7Ã—10-4 Î©cm2 for p- and n-type, respectively from linear TLM measurement. We also found some variation of the specific contact resistance and the sheet resistance from our TLM measurement for p-type contacts. We will discuss this behavior with the measurement of SIMS. Long-term stability with a top-cap layer is also discussed.

• 330. Lee, S. -K
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Reduction of the barrier height and enhancement of tunneling current of titanium contacts using embedded Au nano-particles on 4H and 6H silicon carbide2002In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 389-393, no 2, p. 937-940Article in journal (Refereed)

We have investigated the electrical characteristics of Ti Schottky contacts with embedded Au nano-particles on various types of epilayers of SiC (4H- and 6H-SiC). From our current-voltage (I-V) and capacitance-voltage (C-V) measurements, we observed that Ti Schottky contacts with embedded Au nano-particles had 0.19 eV (n-4H-SiC) and 0.15 eV (n-6H-SiC) lower barrier height than those of particle free Ti Schottky contacts. In order to understand this reduction of the Schottky barrier height (SBH) for Ti Schottky contacts with embedded Au nano-particles, it has been proposed that SBH lowering is caused by an enhanced electric field due to the small size of the Au nano-particles and the large SBH difference. We have also tested these contacts on highly doped n-and p-type SiC material to study ohmic contacts using linear TLM measurements.

• 331. Leerungnawarat, P.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Via-hole etching for SiC1999In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 17, p. 2050-2054Article in journal (Refereed)

Four different F2-based plasma chemistries for high-rate etching of SiC under inductively coupled plasma (ICP) conditions were examined. Much higher rates (up to 8000 #x2009; #xc5; #x2009;min-1) were achieved with NF3 and SF6 compared with BF3 and PF5, in good correlation with their bond energies and their dissociation efficiency in the ICP source. Three different materials (Al, Ni, and indium #x2013;tin oxide) were compared as possible masks during deep SiC etching for through-wafer via holes. Al appears to produce the best etch resistance, particularly when O2 is added to the plasma chemistry. With the correct choice of plasma chemistry and mask material, ICP etching appears to be capable of producing via holes in SiC substrates. #xa9; 1999 American Vacuum Society.

• 332.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Graphene for microelectronics: Can it make a difference?2012In: 2012 Proceedings of the ESSCIRC (ESSCIRC), IEEE , 2012, p. 25-27Conference paper (Refereed)

Benchmarking figures for graphene show remarkable properties like ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs [1, 2]. When graphene is integrated and processed, however, defects in the graphene and its dielectric environment dominate device performance [3, 4]. Furthermore, the lack of a band gap limits the applicability of graphene field effect transistors (GFETs) for logic applications. Yet, there are many options for graphene to make a difference in the future of microelectronics, many of which can be attributed to the More than Moore domain defined in the ITRS. These will be discussed in this talk.

• 333.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Graphene for microelectronics: Can it make a difference?2012In: Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European, IEEE conference proceedings, 2012, p. 25-27Conference paper (Refereed)

Benchmarking figures for graphene show remarkable properties like ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs [1, 2]. When graphene is integrated and processed, however, defects in the graphene and its dielectric environment dominate device performance [3, 4]. Furthermore, the lack of a band gap limits the applicability of graphene field effect transistors (GFETs) for logic applications. Yet, there are many options for graphene to make a difference in the future of microelectronics, many of which can be attributed to the More than Moore domain defined in the ITRS. These will be discussed in this talk.

• 334.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Graphene for More Moore and More Than Moore applications2012In: IEEE Silicon Nanoelectronics Workshop, SNW, IEEE , 2012, p. 6243322-Conference paper (Refereed)

Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm 2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment [1, 2] and high contact resistance [3, 4]. In addition, graphene has no energy band gap (Figure 1) and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour [5]. This has steered interest away from logic to analog radio frequency (RF) applications [6, 7]. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology [8]. GFETs slightly lag behind in maximum cut-off frequency F T,max (Figure 2) up to a carrier mobility of 3000 cm 2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves.

• 335.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Alternative graphene devices: Beyond field effect transistors2012In: Device Research Conference (DRC), 2012 70th Annual, IEEE , 2012, p. 24a-24bConference paper (Refereed)

The future manufacturability of graphene devices depends on the availability of large-scale graphene fabrication methods. While chemical vapor deposition and epitaxy from silicon carbide both promise scalability, they are not (yet) fully compatible with silicon technology. Direct growth of graphene on insulating substrates would be a major step, but is still at a very early stage [1]. This has implications on potential entry points of graphene as an add-on to mainstream silicon technology, which will be discussed in the talk.

• 336.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Ink-jet printing of thin film transistors based on carbon nanotubes2010Doctoral thesis, comprehensive summary (Other academic)

The outstanding electrical and mechanical properties of single-walled carbon nanotubes (SWCNTs) may offer solutions to realizing high-mobility and high-bendability thin-film transistors (TFTs) for the emerging flexible electronics. This thesis aims to develop low-cost ink-jet printing techniques for high-performance TFTs based on pristine SWCNTs. The main challenge of this work is to suppress the effects of “metallic SWCNT contamination” and improve the device electrical performance. To this end, this thesis entails a balance between experiments and simulations.

First, TFTs with low-density SWCNTs in the channel region are fabricated by utilizing standard silicon technology. Their electrical performance is investigated in terms of throughput, transfer characteristics, dimensional scaling and dependence on electrode metals. The demonstrated insensitivity of electrical performance to the electrode metals lifts constrains on choosing metal inks for ink-jet printing.

Second, Monte Carlo models on the basis of percolation theory have been established, and high-efficiency algorithms have been proposed for investigations of large-size stick systems in order to facilitate studies of TFTs with channel length up to 1000 times that of the SWCNTs. The Monte Carlo simulations have led to fundamental understanding on stick percolation, including high-precision percolation threshold, universal finite-size scaling function, and dependence of critical conductivity exponents on assignment of component resistance. They have further generated understanding of practical issues regarding heterogeneous percolation systems and the doping effects in SWCNT TFTs.

Third, Monte Carlo simulations are conducted to explore new device structures for performance improvement of SWCNT TFTs. In particular, a novel device structure featuring composite SWCNT networks in the channel is predicted by the simulation and subsequently confirmed experimentally by another research group. Through Monte Carlo simulations, the compatibility of previously-proposed long-strip-channel SWCNT TFTs with ink-jet printing has also been demonstrated.

Finally, relatively sophisticated ink-jet printing techniques have been developed for SWCNT TFTs with long-strip channels. This research spans from SWCNT ink formulation to device design and fabrication. SWCNT TFTs are finally ink-jet printed on both silicon wafers and flexible Kapton substrates with fairly high electrical performance.

• 337.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Siegen, Germany. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Inkjet Printing of 2D Layered Materials2014In: ChemPhysChem, ISSN 1439-4235, E-ISSN 1439-7641, Vol. 15, no 16, p. 3427-3434Article in journal (Refereed)

Inkjet printing of 2D layered materials, such as graphene and MoS2, has attracted great interests for emerging electronics. However, incompatible rheology, low concentration, severe aggregation and toxicity of solvents constitute critical challenges which hamper the manufacturing efficiency and product quality. Here, we introduce a simple and general technology concept (distillation-assisted solvent exchange) to efficiently overcome these challenges. By implementing the concept, we have demonstrated excellent jetting performance, ideal printing patterns and a variety of promising applications for inkjet printing of 2D layered materials.

• 338.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Univ Grenoble Alpes, France. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
All-solid-state micro-supercapacitors based on inkjet printed graphene electrodes2016In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 109, no 12, article id 123901Article in journal (Refereed)

The all-solid-state graphene-based in-plane micro-supercapacitors are fabricated simply through reliable inkjet printing of pristine graphene in interdigitated structure on silicon wafers to serve as both electrodes and current collectors, and a following drop casting of polymer electrolytes (polyvinyl alcohol/H3PO4). Benefiting from the printing processing, an attractive porous electrode microstructure with a large number of vertically orientated graphene flakes is observed. The devices exhibit commendable areal capacitance over 0.1 mF/cm(2) and a long cycle life of over 1000 times. The simple and scalable fabrication technique for efficient micro-supercapacitors is promising for on-chip energy storage applications in emerging electronics.

• 339.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Siegen, Germany. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Inkjet Printing of MoS22014In: Advanced Functional Materials, ISSN 1616-301X, E-ISSN 1616-3028, Vol. 24, no 41, p. 6524-6531Article in journal (Refereed)

A simple and efficient inkjet printing technology is developed for molybdenum disulfide (MoS2), one of the most attractive two-dimensional layered materials. The technology effectively addresses critical issues associated with normal MoS2 liquid dispersions (such as incompatible rheology, low concentration, and solvent toxicity), and hence can directly and reliably write uniform patterns of high-quality (5-7 nm thick) MoS2 nanosheets at a resolution of tens of micrometers. The technology efficiency facilitates the integration of printed MoS2 patterns with other components (such as electrodes), and hence allows fabricating various functional devices, including thin film transistors, photoluminescence patterns, and photodetectors, in a simple, massive and cost-effective manner while retains the unique properties of MoS2. The technology has great potential in a variety of applications, such as photonics, optoelectronics, sensors, and energy storage.

• 340.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Precise percolation thresholds of two-dimensional random systems comprising overlapping ellipses2016In: Physica A: Statistical Mechanics and its Applications, ISSN 0378-4371, E-ISSN 1873-2119, Vol. 462, p. 940-950Article in journal (Refereed)

This work explores the percolation thresholds of continuum systems consisting of randomly-oriented overlapping ellipses. High-precision percolation thresholds for various homogeneous ellipse systems with different aspect ratios are obtained from extensive Monte Carlo simulations based on the incorporation of Vieillard-Baron's contact function of two identical ellipses with our efficient algorithm for continuum percolation. In addition, we generalize Vieillard-Baron's contact function from identical ellipses to unequal ellipses, and extend the Monte Carlo algorithm to heterogeneous ellipse systems where the ellipses have different dimensions and/or aspect ratios. Based on the concept of modified excluded area, a general law is verified for precise prediction of percolation threshold for many heterogeneous ellipse systems. In particular, the study of heterogeneous ellipse systems gains insight into the apparent percolation threshold symmetry observed earlier in systems comprising unequal circles (Consiglio et al., 2004).

• 341.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Threshold of hierarchical percolating systems2012In: Physical Review E. Statistical, Nonlinear, and Soft Matter Physics, ISSN 1539-3755, E-ISSN 1550-2376, Vol. 85, no 2, p. 021109-Article in journal (Refereed)

Many modern nanostructured materials and doped polymers are morphologically too complex to be interpreted by classical percolation theory. Here, we develop the concept of a hierarchical percolating (percolation-within-percolation) system to describe such complex materials and illustrate how to generalize the conventional percolation to double-level percolation. Based on Monte Carlo simulations, we find that the double-level percolation threshold is close to, but definitely larger than, the product of the local percolation thresholds for the two enclosed single-level systems. The deviation may offer alternative insights into physics concerning infinite clusters and open up new research directions for percolation theory.

• 342.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Uppsala University, Sweden. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT). Uppsala University, Sweden.
Ink-jet printed thin-film transistors with carbon nanotube channels shaped in long strips2011In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 109, no 8, article id 084915Article in journal (Refereed)

The present work reports on the development of a class of sophisticated thin-film transistors (TFTs) based on ink-jet printing of pristine single-walled carbon nanotubes (SWCNTs) for the channel formation. The transistors are manufactured on oxidized silicon wafer and flexible plastic substrates at ambient conditions. For this purpose, ink-jet printing techniques are developed aiming at high-throughput production of SWCNT thin-film channels shaped in long strips. Stable SWCNT inks with proper fluidic characteristics are formulated by polymer addition. The present work unveils, through Monte Carlo simulation and in the light of heterogeneous percolation, the underlying physics of the superiority of long-strip channels for SWCNT TFTs. It further predicts the compatibility of such a channel structure with ink-jet printing taking into account the minimum dimensions achievable by commercially available printers. The printed devices exhibit improved electrical performance and scalability, compared to previously reported ink-jet printed SWCNT TFTs. The present work demonstrates that ink-jet printed SWCNT TFTs of long-strip channels are promising building blocks for flexible electronics.

• 343.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Material Physics, Functional Materials, FNM. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Material Physics, Functional Materials, FNM. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
A simple route towards high-concentration surfactant-free graphene dispersions2012In: Carbon, ISSN 0008-6223, E-ISSN 1873-3891, Vol. 50, no 8, p. 3113-3116Article in journal (Refereed)

A simple solvent exchange method is introduced to prepare high-concentration and surfactant-free graphene liquid dispersion. Natural graphite flakes are first exfoliated into graphene in dimethylformamide (DMF). DMF is then exchanged by terpineol through distillation, relying on their large difference in boiling points. Graphene can then be concentrated thanks to the volume difference between DMF and terpineol. The concentrated graphene dispersions are used to fabricate transparent conductive thin films, which possess comparable properties to those prepared by more complex methods.

• 344.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Functional Materials, FNM. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Efficient inkjet printing of graphene2013In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 25, no 29, p. 3985-3992Article in journal (Refereed)

An efficient and mature inkjet printing technology is introduced for mass production of coffee-ring-free patterns of high-quality graphene at high resolution (unmarked scale bars are 100 μm). Typically, several passes of printing and a simple baking allow fabricating a variety of good-performance electronic devices, including transparent conductors, embedded resistors, thin film transistors, and micro-supercapacitors.

• 345.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Conductivity exponents in stick percolation2010In: Physical Review E. Statistical, Nonlinear, and Soft Matter Physics: Statistical Physics, Plasmas, Fluids, and Related Interdisciplinary Topics, ISSN 1063-651X, E-ISSN 1095-3787, Vol. 81, no 021120Article in journal (Refereed)

On the basis of Monte Carlo simulations, the present work systematically investigates how conductivity exponents depend on the ratio of stick-stick junction resistance to stick resistance for two-dimensional stick percolation. Simulation results suggest that the critical conductivity exponent extracted from size-dependent conductivities of systems exactly at the percolation threshold is independent of the resistance ratio and has a constant value of 1.280 +/- 0.014. In contrast, the apparent conductivity exponent extracted from density-dependent conductivities of systems well above the percolation threshold monotonically varies with the resistance ratio, following an error function, and lies in the vicinity of the critical exponent.

• 346.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Finite-size scaling in stick percolation2009In: Physical Review E. Statistical, Nonlinear, and Soft Matter Physics: Statistical Physics, Plasmas, Fluids, and Related Interdisciplinary Topics, ISSN 1063-651X, E-ISSN 1095-3787, Vol. 80, no 4Article in journal (Refereed)

This work presents the generalization of the concept of universal finite-size scaling functions to continuum percolation. A high-efficiency algorithm for Monte Carlo simulations is developed to investigate, with extensive realizations, the finite-size scaling behavior of stick percolation in large-size systems. The percolation threshold of high precision is determined for isotropic widthless stick systems as N(c)l(2)=5.637 26 +/- 0.000 02, with N-c as the critical density and l as the stick length. Simulation results indicate that by introducing a nonuniversal metric factor A=0.106 910 +/- 0.000 009, the spanning probability of stick percolation on square systems with free boundary conditions falls on the same universal scaling function as that for lattice percolation.

• 347.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Understanding doping effects in biosensing using carbon nanotube network field-effect transistors2009In: Physical Review B. Condensed Matter and Materials Physics, ISSN 1098-0121, E-ISSN 1550-235X, Vol. 79, no 155434Article in journal (Refereed)

Systematic theoretical studies based on a comprehensive heterogeneous stick percolation model are performed to gain insights into the essence of doping effects in electrical sensing of biomolecules, such as proteins and DNA fragments, using carbon nanotube network field-effect transistors (CNNFETs). The present work demonstrates that the electrical response to doping of CNNFETs is primarily caused by conductance change at the electrode-nanotube contacts, in contrast to that in the channel as assumed previously. However, the presence of intertube junctions in the channel could reduce the sensitivity of CNNFET-based biosensors and is partially responsible for the experimentally observed channel-length dependent sensitivity.

• 348.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Contact-electrode insensitive rectifiers based on carbon nanotube network transistors2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, p. 500-502Article in journal (Refereed)

This letter presents rectifiers based on the diode connection of carbon nanotube network (CNN) transistors. Despite a low density of carbon nanotubes in the CNNs, the devices can achieve excellent performance with a forward/reverse current ratio reaching 10(5). By casting nanotube suspension on oxidized Si substrates with predefined electrodes, CNN-based field-effect transistors are readily prepared. By short-circuiting the source and gate terminals, CNN-based rectifiers are realized with the rectification characteristics independent of whether Pd or Al is employed as the contact electrodes. This independence is especially attractive for applications of CNN-based transistors/rectifiers in flexible electronics with various printing techniques.

• 349.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Percolation in random networks of heterogeneous nanotubes2007In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 91, no 253127Article in journal (Refereed)

The electrical performance of random carbon nanotube network transistors is found by Monte Carlo simulation to strongly depend on the nature of the conduction path percolating the network. When the network is percolated only by semiconducting nanotube pathways (OSPs), the transistors can directly achieve both high on current and large on/off current ratio. Based on percolation theory, the present work predicts that there exist specific nanotube coverage domains within which OSP has the highest probability and becomes predominant. Simulation results show that the coverage domains depend on the network dimension, nanotube length, and the fraction of metallic nanotubes.

• 350.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Distinguishing self-gated rectification action from ordinary diode rectification in back-gated carbon nanotube devices2008In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 92, no 133111Article in journal (Refereed)

Self-gating leading to rectification action is frequently observed in two-terminal devices built from individual or networked single-walled carbon nanotubes (SWCNTs) on oxidized Si substrates. The current-voltage (I-V) curves of these SWCNT devices remain unaltered when switching the measurement probes. For ordinary diodes, the I-V curves are symmetric about the origin of the coordinates when exchanging the probes. Numerical simulations suggest that the self-gated rectification action should result from the floating semiconducting substrate which acts as a back gate. Self-gating effect is clearly not unique for SWCNT devices. As expected, it is absent for devices fabricated on insulating substrates.

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