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  • 451.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gudmundsson, Valur
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Towards Schottky-Barrier Source/Drain MOSFETs2008In: 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 / [ed] Yu M, An X, NEW YORK: IEEE , 2008, p. 146-149Conference paper (Refereed)
    Abstract [en]

    This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of silicide growth. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. In the past two years several groups have demonstrated high-performance SB MOSFETs, which places the technology as a promising candidate for future generations of CMOS technology.

  • 452.
    Östling, Mikael
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Haralson, Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    High performance SiGeC HBT technology for radio frequency applications2004In: 2004 Asia-Pacific Radio Science Conference - Proceedings, 2004, p. 480-483Conference paper (Refereed)
    Abstract [en]

    In this paper, the current status of SiGeC bipolar technologies for high-speed and wireless applications is reviewed. The key process features and radio frequency (RF) performance of advanced SiGe bipolar processes are summarized. The different approaches to form a self-aligned base-emitter structure with minimum parasitics are discussed. SiGe:C epitaxy allows very good profile control of the narrow base doping peak, which enables cut-off frequencies above 300 GHz. Downscaling of device dimensions for improved RF performance is also investigated using TCAD simulations. Finally, novel device structures using SOI substrates are discussed.

  • 453.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Naiini, Maziar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Olyaei, Maryam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bethge, O.
    Bertagnolli, E.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Atomic layer deposition-based interface engineering for high-k/metal gate stacks2012In: ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, IEEE , 2012, p. 6467643-Conference paper (Refereed)
    Abstract [en]

    This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO2), Aluminum-Oxide (Al2O3), Lanthanum-Lutetium-Oxide (LaLuO3) and Lanthanum-Oxide (La 2O3) for CMOS-based device technology are investigated in combination with Silicon (Si) and Germanium (Ge) substrates. Additionally, the use of ALD for deposition of a high-k dielectric gate stack on Graphene is discussed.

  • 454.
    Östling, Mikael
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Koo, S. M.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Khartsev, Sergiy
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grishin, Alexander M.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ferroelectric thin films on silicon carbide for next-generation nonvolatile memory and sensor devices2004In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 469-70, p. 444-449Article in journal (Refereed)
    Abstract [en]

    Silicon carbide semiconductor technology has emerged as a very good candidate to replace traditional Si devices in special applications such as low loss power switching and high temperature electronics. Ferroelectric thin films exhibit interesting properties for use in semiconductor technology due to the spontaneous polarization which can be switched by an externally applied electric field, and thus are attractive for nonvolatile memory and sensor applications. In this work, the successful realization of ferroelectric thin films in SiC devices is described. The first experimental prototype devices are presented and discussed: A novel integration technique of junction metal-oxide-semiconductor field effect transistors (JMOSFETs) and nonvolatile FETs (NVFETs) on a single 4H-SiC substrate is presented. A constant current control device is based on the SiC JMOSFET. The drain current is effectively controlled and kept constant by a buried junction gate. A new high temperature SiC NVFET with a similar temperature stable current drive is also demonstrated. The nonvolatile memory device, based on the ferroelectric gate stack, was shown to operate up to 300 C with memory effect retained up to 200degreesC.

  • 455.
    Östling, Mikael
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Koo, Sang-Mo
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Lee, Sang-Kwon
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grishin, Alex
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Thin films in silicon carbide semiconductor devices2004In: Proceedings of SPIE, the International Society for Optical Engineering, ISSN 0277-786X, E-ISSN 1996-756X, Vol. 5774, p. 5-10Article in journal (Refereed)
    Abstract [en]

    Silicon carbide (SiC) semiconductor devices have been established during the last decade as very useful high power, high speed and high temperature devices because of their inherent outstanding semiconductor materials properties. Due to its large band gap, SiC possesses a very high breakdown field and low intrinsic carrier concentration which according makes A high voltage and high temperature operation possible. SiC is also suitable for high frequency device applications, because of the high saturation drift velocity and low permittivity. Thin film technology for various functions in the devices has been heavily researched. Suitable thin film technologies for Ohmic and low-resistive contact formation, passivation and new functionality utilizing ferroelectric materials have been developed. In ferroelectrics, the spontaneous polarization can be switched by an externally applied electric field, and thus are attractive for non-volatile memory and sensor applications. A novel integration of Junction-MOSFETs (JMOSFETs) and Nonvolatile FETs (NVFETs) on a single 4H-SiC substrate is realized. SiC JMOSFET controls the drain current effectively from the buried junction Late thereby allowing for a constant current level at elevated temperatures. SiC NVFET has similar functions with non-volatile memory capability due to ferroelectric gate stack. which operated up to 300degreesC with memory function retained up to 200degreesC.

  • 456.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Koo, S.-M.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Danielsson, Erik
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SiC Device Technologies2005In: Encyclopedia of RF and Microwave Engineering: vol 5 / [ed] Kai Cang, Wiley-Blackwell, 2005, 1, p. 4613-Chapter in book (Refereed)
  • 457.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Silicon carbide devices and processes - Present status and future perspective2006In: Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems / [ed] Napieralski, A, 2006, p. 34-42Conference paper (Refereed)
    Abstract [en]

    Silicon carbide electronic devices are already commercially available in a few application areas such as high voltage rectifiers and emerging rf power amplifiers. Over the past 15 years a very rapid progress of both materials and device quality has been seen and is very encouraging for the near future application market. Prototype devices show amazing improvement each year in all device categories as well as a markedly improved wafer quality. However, materials defect issues are still limiting economically viable production of large area devices with high yield. In this paper a thorough review of progress in SiC device process technology and presents the state-of-the art SiC devices as well as new application areas such as ferroelectric field effect transistors.

  • 458.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Luo, Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gudmundsson, Valur
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology2010In: ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2010, p. 41-45Conference paper (Refereed)
    Abstract [en]

    An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier height (SBH), S/D to gate underlap, top Si layer thickness, oxide thickness and so on should be optimized. Recently, a lot of efforts have been invested in MSD MOSFETs based on Pt- and Ni-silicide implementation and several promising results have been reported in literature. The experimental work as well as the results of Monte Carlo simulations by this research team and by other research teams is discussed in this paper. It will be shown that the present results place MSD MOSFETs as a competitive candidate for future generations of CMOS technology.

  • 459.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Luo, Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gudmundsson, Valur
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts2010In: 2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings, 2010, p. 9-13Conference paper (Refereed)
    Abstract [en]

    This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.

  • 460.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Luo, Jun Hang
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gudmundsson, Valur
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Technology challenges in silicon devices beyond the 16 nm node2011In: Proceedings of the 18th International Conference: Mixed Design of Integrated Circuits and Systems, MIXDES 2011, 2011, p. 27-31Conference paper (Refereed)
    Abstract [en]

    An overview of metallic source/drain (MSD) contacts in nano-scaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nano-scaled CMOS, i.e. extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier height (SBH), S/D to gate underlap, top Si layer thickness, oxide thickness should be optimized. Recently, efforts have been invested in MSD MOSFETs based on Pt- and Ni-silicide implementation and several promising results have been reported in literature. The experimental work as well as the results of Monte Carlo simulations by several investigators, including the authors, is discussed in this paper. It will be shown that the present results place MSD MOSFETs as a competitive candidate for future generations of CMOS technology.

  • 461.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Editorial Selected papers from the 15th Ultimate Integration on Silicon (ULIS) conference2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 108, p. 1-1Article in journal (Refereed)
  • 462.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SELECTED PAPERS FROM THE ESSDERC 2011 CONFERENCE Foreword2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 1-1Article in journal (Other academic)
  • 463.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shili
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Critical technology issues for deca-nanometer MOSFETs2007In: ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2007, p. 27-30Conference paper (Refereed)
    Abstract [en]

    An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-K gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed.

  • 464.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellstrom, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shili
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Device integration issues towards 10 nm MOSFETs2006In: 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, NEW YORK, NY: IEEE , 2006, p. 25-30Conference paper (Refereed)
    Abstract [en]

    An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high K gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO(2)/Al(2)O(3). Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated, Finally ultra thin body Sol devices with high mobility SiGe channels are demonstrated.

  • 465.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Isheden, Christian
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Seger, Johan
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Novel integration concepts for sige-based rf-MOSFETs2005In: Proc. Electrochem. Soc., 2005, p. 270-284Conference paper (Refereed)
    Abstract [en]

    An overview of critical integration issues for future generation rf-MOSFETs is presented. The process requirements and implementation of selective epitaxy for the source and drain regions is given. In-situ doping of highly boron doped recessed SiGe S/D is demonstrated. Channel region engineering is discussed and 50 nm strained SiGe pMOSFETs are demonstrated. Implementation of high-κ gate dielectrics is presented and device performance is demonstrated for surface channel MOSFETs with a gate stack based on ALD-formed HfO2/Al 2O3. Low frequency noise properties for those devices are analyzed. Contact metallization issues are critical for ultra scaled devices and here the implementation of NiSi on SiGe(C) regions as well as on ultra thin body SOI MOSFETs are presented. Finally, a spacer pattering technology using optical lithography to fabricate sub-50 nm high-frequency MOSFETs is demonstrated.

  • 466.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, GunnarKTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    ESSDERC 2011 Proceedings2011Conference proceedings (editor) (Refereed)
  • 467.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Speed Electronics2010In: Ion Beams in Nanoscience and Technology / [ed] Ragnar Hellborg, Harry J. Whitlow, Yanweng Zhang, Springer Berlin/Heidelberg, 2010, 1, p. 457-Chapter in book (Other academic)
  • 468.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Foreword2011In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 60, no 1Article in journal (Refereed)
  • 469.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    State of the art Power Switching Devices in SiC and their Applications2016In: 2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), IEEE, 2016, p. 122-123Conference paper (Refereed)
    Abstract [en]

    This paper gives an overview of the current state of the art device technology for SiC discrete devices and applications. The superior switching performance is discusses as well as the energy efficiency of SiC devices. New emerging applications of SiC devices are also discussed focusing on high temperature capability such as integrated digital and analog circuits up to 600 C. Finally, MEMS and Bio applications will be briefly reviewed.

78910 451 - 469 of 469
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